arch/arm/dts/socfpga.dtsi

   1 /*
   2  *  Copyright (C) 2012 Altera <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include "skeleton.dtsi"
   8 #include <dt-bindings/reset/altr,rst-mgr.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         aliases {
  15                 ethernet0 = &gmac0;
  16                 ethernet1 = &gmac1;
  17                 serial0 = &uart0;
  18                 serial1 = &uart1;
  19                 timer0 = &timer0;
  20                 timer1 = &timer1;
  21                 timer2 = &timer2;
  22                 timer3 = &timer3;
  23                 spi0 = &qspi;
  24                 spi1 = &spi0;
  25                 spi2 = &spi1;
  26                 mmc = &mmc;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         compatible = "arm,cortex-a9";
  35                         device_type = "cpu";
  36                         reg = <0>;
  37                         next-level-cache = <&L2>;
  38                 };
  39                 cpu@1 {
  40                         compatible = "arm,cortex-a9";
  41                         device_type = "cpu";
  42                         reg = <1>;
  43                         next-level-cache = <&L2>;
  44                 };
  45         };
  46
  47         intc: intc@fffed000 {
  48                 compatible = "arm,cortex-a9-gic";
  49                 #interrupt-cells = <3>;
  50                 interrupt-controller;
  51                 reg = <0xfffed000 0x1000>,
  52                       <0xfffec100 0x100>;
  53         };
  54
  55         soc {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 compatible = "simple-bus";
  59                 device_type = "soc";
  60                 interrupt-parent = <&intc>;
  61                 ranges;
  62
  63                 amba {
  64                         compatible = "arm,amba-bus";
  65                         #address-cells = <1>;
  66                         #size-cells = <1>;
  67                         ranges;
  68
  69                         pdma: pdma@ffe01000 {
  70                                 compatible = "arm,pl330", "arm,primecell";
  71                                 reg = <0xffe01000 0x1000>;
  72                                 interrupts = <0 104 4>,
  73                                              <0 105 4>,
  74                                              <0 106 4>,
  75                                              <0 107 4>,
  76                                              <0 108 4>,
  77                                              <0 109 4>,
  78                                              <0 110 4>,
  79                                              <0 111 4>;
  80                                 #dma-cells = <1>;
  81                                 #dma-channels = <8>;
  82                                 #dma-requests = <32>;
  83                                 clocks = <&l4_main_clk>;
  84                                 clock-names = "apb_pclk";
  85                         };
  86                 };
  87
  88                 can0: can@ffc00000 {
  89                         compatible = "bosch,d_can";
  90                         reg = <0xffc00000 0x1000>;
  91                         interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
  92                         clocks = <&can0_clk>;
  93                         status = "disabled";
  94                 };
  95
  96                 can1: can@ffc01000 {
  97                         compatible = "bosch,d_can";
  98                         reg = <0xffc01000 0x1000>;
  99                         interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
 100                         clocks = <&can1_clk>;
 101                         status = "disabled";
 102                 };
 103
 104                 clkmgr@ffd04000 {
 105                                 compatible = "altr,clk-mgr";
 106                                 reg = <0xffd04000 0x1000>;
 107
 108                                 clocks {
 109                                         #address-cells = <1>;
 110                                         #size-cells = <0>;
 111
 112                                         osc1: osc1 {
 113                                                 #clock-cells = <0>;
 114                                                 compatible = "fixed-clock";
 115                                         };
 116
 117                                         osc2: osc2 {
 118                                                 #clock-cells = <0>;
 119                                                 compatible = "fixed-clock";
 120                                         };
 121
 122                                         f2s_periph_ref_clk: f2s_periph_ref_clk {
 123                                                 #clock-cells = <0>;
 124                                                 compatible = "fixed-clock";
 125                                         };
 126
 127                                         f2s_sdram_ref_clk: f2s_sdram_ref_clk {
 128                                                 #clock-cells = <0>;
 129                                                 compatible = "fixed-clock";
 130                                         };
 131
 132                                         main_pll: main_pll {
 133                                                 #address-cells = <1>;
 134                                                 #size-cells = <0>;
 135                                                 #clock-cells = <0>;
 136                                                 compatible = "altr,socfpga-pll-clock";
 137                                                 clocks = <&osc1>;
 138                                                 reg = <0x40>;
 139
 140                                                 mpuclk: mpuclk {
 141                                                         #clock-cells = <0>;
 142                                                         compatible = "altr,socfpga-perip-clk";
 143                                                         clocks = <&main_pll>;
 144                                                         div-reg = <0xe0 0 9>;
 145                                                         reg = <0x48>;
 146                                                 };
 147
 148                                                 mainclk: mainclk {
 149                                                         #clock-cells = <0>;
 150                                                         compatible = "altr,socfpga-perip-clk";
 151                                                         clocks = <&main_pll>;
 152                                                         div-reg = <0xe4 0 9>;
 153                                                         reg = <0x4C>;
 154                                                 };
 155
 156                                                 dbg_base_clk: dbg_base_clk {
 157                                                         #clock-cells = <0>;
 158                                                         compatible = "altr,socfpga-perip-clk";
 159                                                         clocks = <&main_pll>;
 160                                                         div-reg = <0xe8 0 9>;
 161                                                         reg = <0x50>;
 162                                                 };
 163
 164                                                 main_qspi_clk: main_qspi_clk {
 165                                                         #clock-cells = <0>;
 166                                                         compatible = "altr,socfpga-perip-clk";
 167                                                         clocks = <&main_pll>;
 168                                                         reg = <0x54>;
 169                                                 };
 170
 171                                                 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
 172                                                         #clock-cells = <0>;
 173                                                         compatible = "altr,socfpga-perip-clk";
 174                                                         clocks = <&main_pll>;
 175                                                         reg = <0x58>;
 176                                                 };
 177
 178                                                 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
 179                                                         #clock-cells = <0>;
 180                                                         compatible = "altr,socfpga-perip-clk";
 181                                                         clocks = <&main_pll>;
 182                                                         reg = <0x5C>;
 183                                                 };
 184                                         };
 185
 186                                         periph_pll: periph_pll {
 187                                                 #address-cells = <1>;
 188                                                 #size-cells = <0>;
 189                                                 #clock-cells = <0>;
 190                                                 compatible = "altr,socfpga-pll-clock";
 191                                                 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
 192                                                 reg = <0x80>;
 193
 194                                                 emac0_clk: emac0_clk {
 195                                                         #clock-cells = <0>;
 196                                                         compatible = "altr,socfpga-perip-clk";
 197                                                         clocks = <&periph_pll>;
 198                                                         reg = <0x88>;
 199                                                 };
 200
 201                                                 emac1_clk: emac1_clk {
 202                                                         #clock-cells = <0>;
 203                                                         compatible = "altr,socfpga-perip-clk";
 204                                                         clocks = <&periph_pll>;
 205                                                         reg = <0x8C>;
 206                                                 };
 207
 208                                                 per_qspi_clk: per_qsi_clk {
 209                                                         #clock-cells = <0>;
 210                                                         compatible = "altr,socfpga-perip-clk";
 211                                                         clocks = <&periph_pll>;
 212                                                         reg = <0x90>;
 213                                                 };
 214
 215                                                 per_nand_mmc_clk: per_nand_mmc_clk {
 216                                                         #clock-cells = <0>;
 217                                                         compatible = "altr,socfpga-perip-clk";
 218                                                         clocks = <&periph_pll>;
 219                                                         reg = <0x94>;
 220                                                 };
 221
 222                                                 per_base_clk: per_base_clk {
 223                                                         #clock-cells = <0>;
 224                                                         compatible = "altr,socfpga-perip-clk";
 225                                                         clocks = <&periph_pll>;
 226                                                         reg = <0x98>;
 227                                                 };
 228
 229                                                 h2f_usr1_clk: h2f_usr1_clk {
 230                                                         #clock-cells = <0>;
 231                                                         compatible = "altr,socfpga-perip-clk";
 232                                                         clocks = <&periph_pll>;
 233                                                         reg = <0x9C>;
 234                                                 };
 235                                         };
 236
 237                                         sdram_pll: sdram_pll {
 238                                                 #address-cells = <1>;
 239                                                 #size-cells = <0>;
 240                                                 #clock-cells = <0>;
 241                                                 compatible = "altr,socfpga-pll-clock";
 242                                                 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
 243                                                 reg = <0xC0>;
 244
 245                                                 ddr_dqs_clk: ddr_dqs_clk {
 246                                                         #clock-cells = <0>;
 247                                                         compatible = "altr,socfpga-perip-clk";
 248                                                         clocks = <&sdram_pll>;
 249                                                         reg = <0xC8>;
 250                                                 };
 251
 252                                                 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
 253                                                         #clock-cells = <0>;
 254                                                         compatible = "altr,socfpga-perip-clk";
 255                                                         clocks = <&sdram_pll>;
 256                                                         reg = <0xCC>;
 257                                                 };
 258
 259                                                 ddr_dq_clk: ddr_dq_clk {
 260                                                         #clock-cells = <0>;
 261                                                         compatible = "altr,socfpga-perip-clk";
 262                                                         clocks = <&sdram_pll>;
 263                                                         reg = <0xD0>;
 264                                                 };
 265
 266                                                 h2f_usr2_clk: h2f_usr2_clk {
 267                                                         #clock-cells = <0>;
 268                                                         compatible = "altr,socfpga-perip-clk";
 269                                                         clocks = <&sdram_pll>;
 270                                                         reg = <0xD4>;
 271                                                 };
 272                                         };
 273
 274                                         mpu_periph_clk: mpu_periph_clk {
 275                                                 #clock-cells = <0>;
 276                                                 compatible = "altr,socfpga-perip-clk";
 277                                                 clocks = <&mpuclk>;
 278                                                 fixed-divider = <4>;
 279                                         };
 280
 281                                         mpu_l2_ram_clk: mpu_l2_ram_clk {
 282                                                 #clock-cells = <0>;
 283                                                 compatible = "altr,socfpga-perip-clk";
 284                                                 clocks = <&mpuclk>;
 285                                                 fixed-divider = <2>;
 286                                         };
 287
 288                                         l4_main_clk: l4_main_clk {
 289                                                 #clock-cells = <0>;
 290                                                 compatible = "altr,socfpga-gate-clk";
 291                                                 clocks = <&mainclk>;
 292                                                 clk-gate = <0x60 0>;
 293                                         };
 294
 295                                         l3_main_clk: l3_main_clk {
 296                                                 #clock-cells = <0>;
 297                                                 compatible = "altr,socfpga-perip-clk";
 298                                                 clocks = <&mainclk>;
 299                                                 fixed-divider = <1>;
 300                                         };
 301
 302                                         l3_mp_clk: l3_mp_clk {
 303                                                 #clock-cells = <0>;
 304                                                 compatible = "altr,socfpga-gate-clk";
 305                                                 clocks = <&mainclk>;
 306                                                 div-reg = <0x64 0 2>;
 307                                                 clk-gate = <0x60 1>;
 308                                         };
 309
 310                                         l3_sp_clk: l3_sp_clk {
 311                                                 #clock-cells = <0>;
 312                                                 compatible = "altr,socfpga-gate-clk";
 313                                                 clocks = <&mainclk>;
 314                                                 div-reg = <0x64 2 2>;
 315                                         };
 316
 317                                         l4_mp_clk: l4_mp_clk {
 318                                                 #clock-cells = <0>;
 319                                                 compatible = "altr,socfpga-gate-clk";
 320                                                 clocks = <&mainclk>, <&per_base_clk>;
 321                                                 div-reg = <0x64 4 3>;
 322                                                 clk-gate = <0x60 2>;
 323                                         };
 324
 325                                         l4_sp_clk: l4_sp_clk {
 326                                                 #clock-cells = <0>;
 327                                                 compatible = "altr,socfpga-gate-clk";
 328                                                 clocks = <&mainclk>, <&per_base_clk>;
 329                                                 div-reg = <0x64 7 3>;
 330                                                 clk-gate = <0x60 3>;
 331                                         };
 332
 333                                         dbg_at_clk: dbg_at_clk {
 334                                                 #clock-cells = <0>;
 335                                                 compatible = "altr,socfpga-gate-clk";
 336                                                 clocks = <&dbg_base_clk>;
 337                                                 div-reg = <0x68 0 2>;
 338                                                 clk-gate = <0x60 4>;
 339                                         };
 340
 341                                         dbg_clk: dbg_clk {
 342                                                 #clock-cells = <0>;
 343                                                 compatible = "altr,socfpga-gate-clk";
 344                                                 clocks = <&dbg_base_clk>;
 345                                                 div-reg = <0x68 2 2>;
 346                                                 clk-gate = <0x60 5>;
 347                                         };
 348
 349                                         dbg_trace_clk: dbg_trace_clk {
 350                                                 #clock-cells = <0>;
 351                                                 compatible = "altr,socfpga-gate-clk";
 352                                                 clocks = <&dbg_base_clk>;
 353                                                 div-reg = <0x6C 0 3>;
 354                                                 clk-gate = <0x60 6>;
 355                                         };
 356
 357                                         dbg_timer_clk: dbg_timer_clk {
 358                                                 #clock-cells = <0>;
 359                                                 compatible = "altr,socfpga-gate-clk";
 360                                                 clocks = <&dbg_base_clk>;
 361                                                 clk-gate = <0x60 7>;
 362                                         };
 363
 364                                         cfg_clk: cfg_clk {
 365                                                 #clock-cells = <0>;
 366                                                 compatible = "altr,socfpga-gate-clk";
 367                                                 clocks = <&cfg_h2f_usr0_clk>;
 368                                                 clk-gate = <0x60 8>;
 369                                         };
 370
 371                                         h2f_user0_clk: h2f_user0_clk {
 372                                                 #clock-cells = <0>;
 373                                                 compatible = "altr,socfpga-gate-clk";
 374                                                 clocks = <&cfg_h2f_usr0_clk>;
 375                                                 clk-gate = <0x60 9>;
 376                                         };
 377
 378                                         emac_0_clk: emac_0_clk {
 379                                                 #clock-cells = <0>;
 380                                                 compatible = "altr,socfpga-gate-clk";
 381                                                 clocks = <&emac0_clk>;
 382                                                 clk-gate = <0xa0 0>;
 383                                         };
 384
 385                                         emac_1_clk: emac_1_clk {
 386                                                 #clock-cells = <0>;
 387                                                 compatible = "altr,socfpga-gate-clk";
 388                                                 clocks = <&emac1_clk>;
 389                                                 clk-gate = <0xa0 1>;
 390                                         };
 391
 392                                         usb_mp_clk: usb_mp_clk {
 393                                                 #clock-cells = <0>;
 394                                                 compatible = "altr,socfpga-gate-clk";
 395                                                 clocks = <&per_base_clk>;
 396                                                 clk-gate = <0xa0 2>;
 397                                                 div-reg = <0xa4 0 3>;
 398                                         };
 399
 400                                         spi_m_clk: spi_m_clk {
 401                                                 #clock-cells = <0>;
 402                                                 compatible = "altr,socfpga-gate-clk";
 403                                                 clocks = <&per_base_clk>;
 404                                                 clk-gate = <0xa0 3>;
 405                                                 div-reg = <0xa4 3 3>;
 406                                         };
 407
 408                                         can0_clk: can0_clk {
 409                                                 #clock-cells = <0>;
 410                                                 compatible = "altr,socfpga-gate-clk";
 411                                                 clocks = <&per_base_clk>;
 412                                                 clk-gate = <0xa0 4>;
 413                                                 div-reg = <0xa4 6 3>;
 414                                         };
 415
 416                                         can1_clk: can1_clk {
 417                                                 #clock-cells = <0>;
 418                                                 compatible = "altr,socfpga-gate-clk";
 419                                                 clocks = <&per_base_clk>;
 420                                                 clk-gate = <0xa0 5>;
 421                                                 div-reg = <0xa4 9 3>;
 422                                         };
 423
 424                                         gpio_db_clk: gpio_db_clk {
 425                                                 #clock-cells = <0>;
 426                                                 compatible = "altr,socfpga-gate-clk";
 427                                                 clocks = <&per_base_clk>;
 428                                                 clk-gate = <0xa0 6>;
 429                                                 div-reg = <0xa8 0 24>;
 430                                         };
 431
 432                                         h2f_user1_clk: h2f_user1_clk {
 433                                                 #clock-cells = <0>;
 434                                                 compatible = "altr,socfpga-gate-clk";
 435                                                 clocks = <&h2f_usr1_clk>;
 436                                                 clk-gate = <0xa0 7>;
 437                                         };
 438
 439                                         sdmmc_clk: sdmmc_clk {
 440                                                 #clock-cells = <0>;
 441                                                 compatible = "altr,socfpga-gate-clk";
 442                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 443                                                 clk-gate = <0xa0 8>;
 444                                                 clk-phase = <0 135>;
 445                                         };
 446
 447                                         nand_x_clk: nand_x_clk {
 448                                                 #clock-cells = <0>;
 449                                                 compatible = "altr,socfpga-gate-clk";
 450                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 451                                                 clk-gate = <0xa0 9>;
 452                                         };
 453
 454                                         nand_clk: nand_clk {
 455                                                 #clock-cells = <0>;
 456                                                 compatible = "altr,socfpga-gate-clk";
 457                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 458                                                 clk-gate = <0xa0 10>;
 459                                                 fixed-divider = <4>;
 460                                         };
 461
 462                                         qspi_clk: qspi_clk {
 463                                                 #clock-cells = <0>;
 464                                                 compatible = "altr,socfpga-gate-clk";
 465                                                 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
 466                                                 clk-gate = <0xa0 11>;
 467                                         };
 468                                 };
 469                         };
 470
 471                 gmac0: ethernet@ff700000 {
 472                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 473                         altr,sysmgr-syscon = <&sysmgr 0x60 0>;
 474                         reg = <0xff700000 0x2000>;
 475                         interrupts = <0 115 4>;
 476                         interrupt-names = "macirq";
 477                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 478                         clocks = <&emac0_clk>;
 479                         clock-names = "stmmaceth";
 480                         resets = <&rst EMAC0_RESET>;
 481                         reset-names = "stmmaceth";
 482                         snps,multicast-filter-bins = <256>;
 483                         snps,perfect-filter-entries = <128>;
 484                         status = "disabled";
 485                 };
 486
 487                 gmac1: ethernet@ff702000 {
 488                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 489                         altr,sysmgr-syscon = <&sysmgr 0x60 2>;
 490                         reg = <0xff702000 0x2000>;
 491                         interrupts = <0 120 4>;
 492                         interrupt-names = "macirq";
 493                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 494                         clocks = <&emac1_clk>;
 495                         clock-names = "stmmaceth";
 496                         resets = <&rst EMAC1_RESET>;
 497                         reset-names = "stmmaceth";
 498                         snps,multicast-filter-bins = <256>;
 499                         snps,perfect-filter-entries = <128>;
 500                         status = "disabled";
 501                 };
 502
 503                 i2c0: i2c@ffc04000 {
 504                         #address-cells = <1>;
 505                         #size-cells = <0>;
 506                         compatible = "snps,designware-i2c";
 507                         reg = <0xffc04000 0x1000>;
 508                         clocks = <&l4_sp_clk>;
 509                         interrupts = <0 158 0x4>;
 510                         status = "disabled";
 511                 };
 512
 513                 i2c1: i2c@ffc05000 {
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                         compatible = "snps,designware-i2c";
 517                         reg = <0xffc05000 0x1000>;
 518                         clocks = <&l4_sp_clk>;
 519                         interrupts = <0 159 0x4>;
 520                         status = "disabled";
 521                 };
 522
 523                 i2c2: i2c@ffc06000 {
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         compatible = "snps,designware-i2c";
 527                         reg = <0xffc06000 0x1000>;
 528                         clocks = <&l4_sp_clk>;
 529                         interrupts = <0 160 0x4>;
 530                         status = "disabled";
 531                 };
 532
 533                 i2c3: i2c@ffc07000 {
 534                         #address-cells = <1>;
 535                         #size-cells = <0>;
 536                         compatible = "snps,designware-i2c";
 537                         reg = <0xffc07000 0x1000>;
 538                         clocks = <&l4_sp_clk>;
 539                         interrupts = <0 161 0x4>;
 540                         status = "disabled";
 541                 };
 542
 543                 gpio0: gpio@ff708000 {
 544                         #address-cells = <1>;
 545                         #size-cells = <0>;
 546                         compatible = "snps,dw-apb-gpio";
 547                         reg = <0xff708000 0x1000>;
 548                         clocks = <&per_base_clk>;
 549                         status = "disabled";
 550
 551                         porta: gpio-controller@0 {
 552                                 compatible = "snps,dw-apb-gpio-port";
 553                                 gpio-controller;
 554                                 #gpio-cells = <2>;
 555                                 snps,nr-gpios = <29>;
 556                                 reg = <0>;
 557                                 interrupt-controller;
 558                                 #interrupt-cells = <2>;
 559                                 interrupts = <0 164 4>;
 560                         };
 561                 };
 562
 563                 gpio1: gpio@ff709000 {
 564                         #address-cells = <1>;
 565                         #size-cells = <0>;
 566                         compatible = "snps,dw-apb-gpio";
 567                         reg = <0xff709000 0x1000>;
 568                         clocks = <&per_base_clk>;
 569                         status = "disabled";
 570
 571                         portb: gpio-controller@0 {
 572                                 compatible = "snps,dw-apb-gpio-port";
 573                                 gpio-controller;
 574                                 #gpio-cells = <2>;
 575                                 snps,nr-gpios = <29>;
 576                                 reg = <0>;
 577                                 interrupt-controller;
 578                                 #interrupt-cells = <2>;
 579                                 interrupts = <0 165 4>;
 580                         };
 581                 };
 582
 583                 gpio2: gpio@ff70a000 {
 584                         #address-cells = <1>;
 585                         #size-cells = <0>;
 586                         compatible = "snps,dw-apb-gpio";
 587                         reg = <0xff70a000 0x1000>;
 588                         clocks = <&per_base_clk>;
 589                         status = "disabled";
 590
 591                         portc: gpio-controller@0 {
 592                                 compatible = "snps,dw-apb-gpio-port";
 593                                 gpio-controller;
 594                                 #gpio-cells = <2>;
 595                                 snps,nr-gpios = <27>;
 596                                 reg = <0>;
 597                                 interrupt-controller;
 598                                 #interrupt-cells = <2>;
 599                                 interrupts = <0 166 4>;
 600                         };
 601                 };
 602
 603                 sdr: sdr@ffc25000 {
 604                         compatible = "syscon";
 605                         reg = <0xffc25000 0x1000>;
 606                 };
 607
 608                 sdramedac {
 609                         compatible = "altr,sdram-edac";
 610                         altr,sdr-syscon = <&sdr>;
 611                         interrupts = <0 39 4>;
 612                 };
 613
 614                 L2: l2-cache@fffef000 {
 615                         compatible = "arm,pl310-cache";
 616                         reg = <0xfffef000 0x1000>;
 617                         interrupts = <0 38 0x04>;
 618                         cache-unified;
 619                         cache-level = <2>;
 620                         arm,tag-latency = <1 1 1>;
 621                         arm,data-latency = <2 1 1>;
 622                 };
 623
 624                 mmc: dwmmc0@ff704000 {
 625                         compatible = "altr,socfpga-dw-mshc";
 626                         reg = <0xff704000 0x1000>;
 627                         interrupts = <0 139 4>;
 628                         fifo-depth = <0x400>;
 629                         #address-cells = <1>;
 630                         #size-cells = <0>;
 631                         clocks = <&l4_mp_clk>, <&sdmmc_clk>;
 632                         clock-names = "biu", "ciu";
 633                 };
 634
 635                 qspi: spi@ff705000 {
 636                         compatible = "cadence,qspi";
 637                         #address-cells = <1>;
 638                         #size-cells = <0>;
 639                         reg = <0xff705000 0x1000>,
 640                                 <0xffa00000 0x1000>;
 641                         interrupts = <0 151 4>;
 642                         clocks = <&qspi_clk>;
 643                         ext-decoder = <0>;  /* external decoder */
 644                         num-cs = <4>;
 645                         fifo-depth = <128>;
 646                         sram-size = <128>;
 647                         bus-num = <2>;
 648                         status = "disabled";
 649                 };
 650
 651                 spi0: spi@fff00000 {
 652                         compatible = "snps,dw-apb-ssi";
 653                         #address-cells = <1>;
 654                         #size-cells = <0>;
 655                         reg = <0xfff00000 0x1000>;
 656                         interrupts = <0 154 4>;
 657                         num-cs = <4>;
 658                         bus-num = <0>;
 659                         tx-dma-channel = <&pdma 16>;
 660                         rx-dma-channel = <&pdma 17>;
 661                         clocks = <&per_base_clk>;
 662                         status = "disabled";
 663                 };
 664
 665                 spi1: spi@fff01000 {
 666                         compatible = "snps,dw-apb-ssi";
 667                         #address-cells = <1>;
 668                         #size-cells = <0>;
 669                         reg = <0xfff01000 0x1000>;
 670                         interrupts = <0 156 4>;
 671                         num-cs = <4>;
 672                         bus-num = <1>;
 673                         tx-dma-channel = <&pdma 20>;
 674                         rx-dma-channel = <&pdma 21>;
 675                         clocks = <&per_base_clk>;
 676                         status = "disabled";
 677                 };
 678
 679                 /* Local timer */
 680                 timer@fffec600 {
 681                         compatible = "arm,cortex-a9-twd-timer";
 682                         reg = <0xfffec600 0x100>;
 683                         interrupts = <1 13 0xf04>;
 684                         clocks = <&mpu_periph_clk>;
 685                 };
 686
 687                 timer0: timer0@ffc08000 {
 688                         compatible = "snps,dw-apb-timer";
 689                         interrupts = <0 167 4>;
 690                         reg = <0xffc08000 0x1000>;
 691                         clocks = <&l4_sp_clk>;
 692                         clock-names = "timer";
 693                 };
 694
 695                 timer1: timer1@ffc09000 {
 696                         compatible = "snps,dw-apb-timer";
 697                         interrupts = <0 168 4>;
 698                         reg = <0xffc09000 0x1000>;
 699                         clocks = <&l4_sp_clk>;
 700                         clock-names = "timer";
 701                 };
 702
 703                 timer2: timer2@ffd00000 {
 704                         compatible = "snps,dw-apb-timer";
 705                         interrupts = <0 169 4>;
 706                         reg = <0xffd00000 0x1000>;
 707                         clocks = <&osc1>;
 708                         clock-names = "timer";
 709                 };
 710
 711                 timer3: timer3@ffd01000 {
 712                         compatible = "snps,dw-apb-timer";
 713                         interrupts = <0 170 4>;
 714                         reg = <0xffd01000 0x1000>;
 715                         clocks = <&osc1>;
 716                         clock-names = "timer";
 717                 };
 718
 719                 uart0: serial0@ffc02000 {
 720                         compatible = "snps,dw-apb-uart";
 721                         reg = <0xffc02000 0x1000>;
 722                         interrupts = <0 162 4>;
 723                         reg-shift = <2>;
 724                         reg-io-width = <4>;
 725                         clocks = <&l4_sp_clk>;
 726                 };
 727
 728                 uart1: serial1@ffc03000 {
 729                         compatible = "snps,dw-apb-uart";
 730                         reg = <0xffc03000 0x1000>;
 731                         interrupts = <0 163 4>;
 732                         reg-shift = <2>;
 733                         reg-io-width = <4>;
 734                         clocks = <&l4_sp_clk>;
 735                 };
 736
 737                 rst: rstmgr@ffd05000 {
 738                         #reset-cells = <1>;
 739                         compatible = "altr,rst-mgr";
 740                         reg = <0xffd05000 0x1000>;
 741                 };
 742
 743                 usbphy0: usbphy@0 {
 744                         #phy-cells = <0>;
 745                         compatible = "usb-nop-xceiv";
 746                         status = "okay";
 747                 };
 748
 749                 usb0: usb@ffb00000 {
 750                         compatible = "snps,dwc2";
 751                         reg = <0xffb00000 0xffff>;
 752                         interrupts = <0 125 4>;
 753                         clocks = <&usb_mp_clk>;
 754                         clock-names = "otg";
 755                         phys = <&usbphy0>;
 756                         phy-names = "usb2-phy";
 757                         status = "disabled";
 758                 };
 759
 760                 usb1: usb@ffb40000 {
 761                         compatible = "snps,dwc2";
 762                         reg = <0xffb40000 0xffff>;
 763                         interrupts = <0 128 4>;
 764                         clocks = <&usb_mp_clk>;
 765                         clock-names = "otg";
 766                         phys = <&usbphy0>;
 767                         phy-names = "usb2-phy";
 768                         status = "disabled";
 769                 };
 770
 771                 watchdog0: watchdog@ffd02000 {
 772                         compatible = "snps,dw-wdt";
 773                         reg = <0xffd02000 0x1000>;
 774                         interrupts = <0 171 4>;
 775                         clocks = <&osc1>;
 776                         status = "disabled";
 777                 };
 778
 779                 watchdog1: watchdog@ffd03000 {
 780                         compatible = "snps,dw-wdt";
 781                         reg = <0xffd03000 0x1000>;
 782                         interrupts = <0 172 4>;
 783                         clocks = <&osc1>;
 784                         status = "disabled";
 785                 };
 786
 787                 sysmgr: sysmgr@ffd08000 {
 788                         compatible = "altr,sys-mgr", "syscon";
 789                         reg = <0xffd08000 0x4000>;
 790                 };
 791         };
 792 };