arch/arm/include/asm/arch-at91/at91sam9_smc.h

   1 /*
   2  * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h]
   3  *
   4  * Copyright (C) 2007 Andrew Victor
   5  * Copyright (C) 2007 Atmel Corporation.
   6  *
   7  * Static Memory Controllers (SMC) - System peripherals registers.
   8  * Based on AT91SAM9261 datasheet revision D.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef AT91SAM9_SMC_H
  14 #define AT91SAM9_SMC_H
  15
  16 #ifdef __ASSEMBLY__
  17
  18 #ifndef ATMEL_BASE_SMC
  19 #define ATMEL_BASE_SMC  ATMEL_BASE_SMC0
  20 #endif
  21
  22 #define AT91_ASM_SMC_SETUP0     ATMEL_BASE_SMC
  23 #define AT91_ASM_SMC_PULSE0     (ATMEL_BASE_SMC + 0x04)
  24 #define AT91_ASM_SMC_CYCLE0     (ATMEL_BASE_SMC + 0x08)
  25 #define AT91_ASM_SMC_MODE0      (ATMEL_BASE_SMC + 0x0C)
  26
  27 #else
  28
  29 typedef struct  at91_cs {
  30         u32     setup;          /* 0x00 SMC Setup Register */
  31         u32     pulse;          /* 0x04 SMC Pulse Register */
  32         u32     cycle;          /* 0x08 SMC Cycle Register */
  33         u32     mode;           /* 0x0C SMC Mode Register */
  34 } at91_cs_t;
  35
  36 typedef struct  at91_smc {
  37         at91_cs_t       cs[8];
  38 } at91_smc_t;
  39
  40 #endif /*  __ASSEMBLY__ */
  41
  42 #define AT91_SMC_SETUP_NWE(x)           (x & 0x3f)
  43 #define AT91_SMC_SETUP_NCS_WR(x)        ((x & 0x3f) << 8)
  44 #define AT91_SMC_SETUP_NRD(x)           ((x & 0x3f) << 16)
  45 #define AT91_SMC_SETUP_NCS_RD(x)        ((x & 0x3f) << 24)
  46
  47 #define AT91_SMC_PULSE_NWE(x)           (x & 0x7f)
  48 #define AT91_SMC_PULSE_NCS_WR(x)        ((x & 0x7f) << 8)
  49 #define AT91_SMC_PULSE_NRD(x)           ((x & 0x7f) << 16)
  50 #define AT91_SMC_PULSE_NCS_RD(x)        ((x & 0x7f) << 24)
  51
  52 #define AT91_SMC_CYCLE_NWE(x)           (x & 0x1ff)
  53 #define AT91_SMC_CYCLE_NRD(x)           ((x & 0x1ff) << 16)
  54
  55 #define AT91_SMC_MODE_RM_NCS            0x00000000
  56 #define AT91_SMC_MODE_RM_NRD            0x00000001
  57 #define AT91_SMC_MODE_WM_NCS            0x00000000
  58 #define AT91_SMC_MODE_WM_NWE            0x00000002
  59
  60 #define AT91_SMC_MODE_EXNW_DISABLE      0x00000000
  61 #define AT91_SMC_MODE_EXNW_FROZEN       0x00000020
  62 #define AT91_SMC_MODE_EXNW_READY        0x00000030
  63
  64 #define AT91_SMC_MODE_BAT               0x00000100
  65 #define AT91_SMC_MODE_DBW_8             0x00000000
  66 #define AT91_SMC_MODE_DBW_16            0x00001000
  67 #define AT91_SMC_MODE_DBW_32            0x00002000
  68 #define AT91_SMC_MODE_TDF_CYCLE(x)      ((x & 0xf) << 16)
  69 #define AT91_SMC_MODE_TDF               0x00100000
  70 #define AT91_SMC_MODE_PMEN              0x01000000
  71 #define AT91_SMC_MODE_PS_4              0x00000000
  72 #define AT91_SMC_MODE_PS_8              0x10000000
  73 #define AT91_SMC_MODE_PS_16             0x20000000
  74 #define AT91_SMC_MODE_PS_32             0x30000000
  75
  76 #ifdef CONFIG_AT91_LEGACY
  77
  78 #define AT91_SMC_SETUP(n)       (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
  79 #define         AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
  80 #define                 AT91_SMC_NWESETUP_(x)   ((x) << 0)
  81 #define         AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
  82 #define                 AT91_SMC_NCS_WRSETUP_(x)        ((x) << 8)
  83 #define         AT91_SMC_NRDSETUP       (0x3f << 16)                    /* NRD Setup Length */
  84 #define                 AT91_SMC_NRDSETUP_(x)   ((x) << 16)
  85 #define         AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
  86 #define                 AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
  87
  88 #define AT91_SMC_PULSE(n)       (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
  89 #define         AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
  90 #define                 AT91_SMC_NWEPULSE_(x)   ((x) << 0)
  91 #define         AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
  92 #define                 AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
  93 #define         AT91_SMC_NRDPULSE       (0x7f << 16)                    /* NRD Pulse Length */
  94 #define                 AT91_SMC_NRDPULSE_(x)   ((x) << 16)
  95 #define         AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
  96 #define                 AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
  97
  98 #define AT91_SMC_CYCLE(n)       (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
  99 #define         AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
 100 #define                 AT91_SMC_NWECYCLE_(x)   ((x) << 0)
 101 #define         AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
 102 #define                 AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
 103
 104 #define AT91_SMC_MODE(n)        (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
 105 #define         AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
 106 #define         AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
 107 #define         AT91_SMC_EXNWMODE       (3 <<  4)                       /* NWAIT Mode */
 108 #define                 AT91_SMC_EXNWMODE_DISABLE       (0 << 4)
 109 #define                 AT91_SMC_EXNWMODE_FROZEN        (2 << 4)
 110 #define                 AT91_SMC_EXNWMODE_READY         (3 << 4)
 111 #define         AT91_SMC_BAT            (1 <<  8)                       /* Byte Access Type */
 112 #define                 AT91_SMC_BAT_SELECT             (0 << 8)
 113 #define                 AT91_SMC_BAT_WRITE              (1 << 8)
 114 #define         AT91_SMC_DBW            (3 << 12)                       /* Data Bus Width */
 115 #define                 AT91_SMC_DBW_8                  (0 << 12)
 116 #define                 AT91_SMC_DBW_16                 (1 << 12)
 117 #define                 AT91_SMC_DBW_32                 (2 << 12)
 118 #define         AT91_SMC_TDF            (0xf << 16)                     /* Data Float Time. */
 119 #define                 AT91_SMC_TDF_(x)                ((x) << 16)
 120 #define         AT91_SMC_TDFMODE        (1 << 20)                       /* TDF Optimization - Enabled */
 121 #define         AT91_SMC_PMEN           (1 << 24)                       /* Page Mode Enabled */
 122 #define         AT91_SMC_PS             (3 << 28)                       /* Page Size */
 123 #define                 AT91_SMC_PS_4                   (0 << 28)
 124 #define                 AT91_SMC_PS_8                   (1 << 28)
 125 #define                 AT91_SMC_PS_16                  (2 << 28)
 126 #define                 AT91_SMC_PS_32                  (3 << 28)
 127
 128 #if defined(AT91_SMC1)          /* The AT91SAM9263 has 2 Static Memory contollers */
 129 #define AT91_SMC1_SETUP(n)      (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
 130 #define AT91_SMC1_PULSE(n)      (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
 131 #define AT91_SMC1_CYCLE(n)      (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
 132 #define AT91_SMC1_MODE(n)       (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
 133 #endif
 134
 135 #endif
 136 #endif