2 * Freescale i.MX6Q GPMI Register Definitions
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #ifndef __MX6Q_REGS_GPMI_H__
27 #define __MX6Q_REGS_GPMI_H__
29 #define MXS_GPMI_BASE 0x00112000
33 mx6_reg_32(hw_gpmi_ctrl0); /* 0x000 */
34 reg_32(hw_gpmi_compare); /* 0x010 */
35 mx6_reg_32(hw_gpmi_eccctrl); /* 0x020 */
36 reg_32(hw_gpmi_ecccount); /* 0x030 */
37 reg_32(hw_gpmi_payload); /* 0x040 */
38 reg_32(hw_gpmi_auxiliary); /* 0x050 */
39 mx6_reg_32(hw_gpmi_ctrl1); /* 0x060 */
40 reg_32(hw_gpmi_timing0); /* 0x070 */
41 reg_32(hw_gpmi_timing1); /* 0x080 */
42 reg_32(hw_gpmi_timing2); /* 0x090 */
43 reg_32(hw_gpmi_data); /* 0x0a0 */
44 reg_32(hw_gpmi_stat); /* 0x0b0 */
45 reg_32(hw_gpmi_debug); /* 0x0c0 */
46 reg_32(hw_gpmi_version); /* 0x0d0 */
47 reg_32(hw_gpmi_debug2); /* 0x0e0 */
48 reg_32(hw_gpmi_debug3); /* 0x0f0 */
49 reg_32(hw_gpmi_rd_ddr_dll_ctrl); /* 0x100 */
50 reg_32(hw_gpmi_wr_ddr_dll_ctrl); /* 0x110 */
51 reg_32(hw_gpmi_rd_ddr_dll_sts); /* 0x120 */
52 reg_32(hw_gpmi_wr_ddr_dll_sts); /* 0x130 */
57 #define GPMI_CTRL0_SFTRST (1 << 31)
58 #define GPMI_CTRL0_CLKGATE (1 << 30)
59 #define GPMI_CTRL0_RUN (1 << 29)
60 #define GPMI_CTRL0_DEV_IRQ_EN (1 << 28)
61 #define GPMI_CTRL0_LOCK_CS (1 << 27)
62 #define GPMI_CTRL0_UDMA (1 << 26)
63 #define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24)
64 #define GPMI_CTRL0_COMMAND_MODE_OFFSET 24
65 #define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24)
66 #define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24)
67 #define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24)
68 #define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24)
69 #define GPMI_CTRL0_WORD_LENGTH (1 << 23)
70 #define GPMI_CTRL0_CS_MASK (0x7 << 20)
71 #define GPMI_CTRL0_CS_OFFSET 20
72 #define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17)
73 #define GPMI_CTRL0_ADDRESS_OFFSET 17
74 #define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17)
75 #define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17)
76 #define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17)
77 #define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
78 #define GPMI_CTRL0_XFER_COUNT_MASK 0xffff
79 #define GPMI_CTRL0_XFER_COUNT_OFFSET 0
81 #define GPMI_COMPARE_MASK_MASK (0xffff << 16)
82 #define GPMI_COMPARE_MASK_OFFSET 16
83 #define GPMI_COMPARE_REFERENCE_MASK 0xffff
84 #define GPMI_COMPARE_REFERENCE_OFFSET 0
86 #define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16)
87 #define GPMI_ECCCTRL_HANDLE_OFFSET 16
88 #define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13)
89 #define GPMI_ECCCTRL_ECC_CMD_OFFSET 13
90 #define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13)
91 #define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13)
92 #define GPMI_ECCCTRL_ENABLE_ECC (1 << 12)
93 #define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff
94 #define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0
95 #define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100
96 #define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff
98 #define GPMI_ECCCOUNT_COUNT_MASK 0xffff
99 #define GPMI_ECCCOUNT_COUNT_OFFSET 0
101 #define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2)
102 #define GPMI_PAYLOAD_ADDRESS_OFFSET 2
104 #define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2)
105 #define GPMI_AUXILIARY_ADDRESS_OFFSET 2
107 #define GPMI_CTRL1_DECOUPLE_CS (1 << 24)
108 #define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22)
109 #define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22
110 #define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20)
111 #define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19)
112 #define GPMI_CTRL1_BCH_MODE (1 << 18)
113 #define GPMI_CTRL1_DLL_ENABLE (1 << 17)
114 #define GPMI_CTRL1_HALF_PERIOD (1 << 16)
115 #define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12)
116 #define GPMI_CTRL1_RDN_DELAY_OFFSET 12
117 #define GPMI_CTRL1_DMA2ECC_MODE (1 << 11)
118 #define GPMI_CTRL1_DEV_IRQ (1 << 10)
119 #define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9)
120 #define GPMI_CTRL1_BURST_EN (1 << 8)
121 #define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7)
122 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4)
123 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4
124 #define GPMI_CTRL1_DEV_RESET (1 << 3)
125 #define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)
126 #define GPMI_CTRL1_CAMERA_MODE (1 << 1)
127 #define GPMI_CTRL1_GPMI_MODE (1 << 0)
129 #define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16)
130 #define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16
131 #define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8)
132 #define GPMI_TIMING0_DATA_HOLD_OFFSET 8
133 #define GPMI_TIMING0_DATA_SETUP_MASK 0xff
134 #define GPMI_TIMING0_DATA_SETUP_OFFSET 0
136 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16)
137 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16
139 #define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24)
140 #define GPMI_TIMING2_UDMA_TRP_OFFSET 24
141 #define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16)
142 #define GPMI_TIMING2_UDMA_ENV_OFFSET 16
143 #define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8)
144 #define GPMI_TIMING2_UDMA_HOLD_OFFSET 8
145 #define GPMI_TIMING2_UDMA_SETUP_MASK 0xff
146 #define GPMI_TIMING2_UDMA_SETUP_OFFSET 0
148 #define GPMI_DATA_DATA_MASK 0xffffffff
149 #define GPMI_DATA_DATA_OFFSET 0
151 #define GPMI_STAT_READY_BUSY_MASK (0xff << 24)
152 #define GPMI_STAT_READY_BUSY_OFFSET 24
153 #define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16)
154 #define GPMI_STAT_RDY_TIMEOUT_OFFSET 16
155 #define GPMI_STAT_DEV7_ERROR (1 << 15)
156 #define GPMI_STAT_DEV6_ERROR (1 << 14)
157 #define GPMI_STAT_DEV5_ERROR (1 << 13)
158 #define GPMI_STAT_DEV4_ERROR (1 << 12)
159 #define GPMI_STAT_DEV3_ERROR (1 << 11)
160 #define GPMI_STAT_DEV2_ERROR (1 << 10)
161 #define GPMI_STAT_DEV1_ERROR (1 << 9)
162 #define GPMI_STAT_DEV0_ERROR (1 << 8)
163 #define GPMI_STAT_ATA_IRQ (1 << 4)
164 #define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3)
165 #define GPMI_STAT_FIFO_EMPTY (1 << 2)
166 #define GPMI_STAT_FIFO_FULL (1 << 1)
167 #define GPMI_STAT_PRESENT (1 << 0)
169 #define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24)
170 #define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24
171 #define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16)
172 #define GPMI_DEBUG_DMA_SENSE_OFFSET 16
173 #define GPMI_DEBUG_DMAREQ_MASK (0xff << 8)
174 #define GPMI_DEBUG_DMAREQ_OFFSET 8
175 #define GPMI_DEBUG_CMD_END_MASK 0xff
176 #define GPMI_DEBUG_CMD_END_OFFSET 0
178 #define GPMI_VERSION_MAJOR_MASK (0xff << 24)
179 #define GPMI_VERSION_MAJOR_OFFSET 24
180 #define GPMI_VERSION_MINOR_MASK (0xff << 16)
181 #define GPMI_VERSION_MINOR_OFFSET 16
182 #define GPMI_VERSION_STEP_MASK 0xffff
183 #define GPMI_VERSION_STEP_OFFSET 0
185 #define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24)
186 #define GPMI_DEBUG2_UDMA_STATE_OFFSET 24
187 #define GPMI_DEBUG2_BUSY (1 << 23)
188 #define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20)
189 #define GPMI_DEBUG2_PIN_STATE_OFFSET 20
190 #define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20)
191 #define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20)
192 #define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20)
193 #define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20)
194 #define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20)
195 #define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20)
196 #define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20)
197 #define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20)
198 #define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16)
199 #define GPMI_DEBUG2_MAIN_STATE_OFFSET 16
200 #define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16)
201 #define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16)
202 #define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16)
203 #define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16)
204 #define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16)
205 #define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16)
206 #define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16)
207 #define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16)
208 #define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16)
209 #define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16)
210 #define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16)
211 #define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12)
212 #define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12
213 #define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11)
214 #define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10)
215 #define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9)
216 #define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8)
217 #define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7)
218 #define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6)
219 #define GPMI_DEBUG2_RDN_TAP_MASK 0x3f
220 #define GPMI_DEBUG2_RDN_TAP_OFFSET 0
222 #define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16)
223 #define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16
224 #define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff
225 #define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0
227 #endif /* __MX6Q_REGS_GPMI_H__ */