2 * Freescale i.MX23/i.MX28 specific functions
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __SYS_PROTO_H__
11 #define __SYS_PROTO_H__
13 #include <asm/imx-common/regs-common.h>
15 int mxs_reset_block(struct mxs_register_32 *reg);
16 int mxs_wait_mask_set(struct mxs_register_32 *reg,
18 unsigned int timeout);
19 int mxs_wait_mask_clr(struct mxs_register_32 *reg,
21 unsigned int timeout);
23 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
25 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
27 #ifdef CONFIG_SPL_BUILD
29 #if defined(CONFIG_SOC_MX23)
30 #include <asm/arch/iomux-mx23.h>
31 #elif defined(CONFIG_SOC_MX28)
32 #include <asm/arch/iomux-mx28.h>
35 void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
36 const iomux_cfg_t *iomux_setup,
37 const unsigned int iomux_size);
46 static const struct mxs_pair mxs_boot_modes[] = {
47 #if defined(CONFIG_SOC_MX23)
48 { 0x00, 0x0f, "USB" },
49 { 0x01, 0x1f, "I2C, master" },
50 { 0x02, 0x1f, "SSP SPI #1, master, NOR" },
51 { 0x03, 0x1f, "SSP SPI #2, master, NOR" },
52 { 0x04, 0x1f, "NAND" },
53 { 0x06, 0x1f, "JTAG" },
54 { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
55 { 0x09, 0x1f, "SSP SD/MMC #0" },
56 { 0x0a, 0x1f, "SSP SD/MMC #1" },
57 { 0x00, 0x00, "Reserved/Unknown/Wrong" },
58 #elif defined(CONFIG_SOC_MX28)
59 { 0x00, 0x0f, "USB #0" },
60 { 0x01, 0x1f, "I2C #0, master, 3V3" },
61 { 0x11, 0x1f, "I2C #0, master, 1V8" },
62 { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
63 { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
64 { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
65 { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
66 { 0x04, 0x1f, "NAND, 3V3" },
67 { 0x14, 0x1f, "NAND, 1V8" },
68 { 0x06, 0x1f, "JTAG" },
69 { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
70 { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
71 { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
72 { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
73 { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
74 { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
75 { 0x00, 0x00, "Reserved/Unknown/Wrong" },
79 #define MXS_BM_USB 0x00
80 #define MXS_BM_I2C_MASTER_3V3 0x01
81 #define MXS_BM_I2C_MASTER_1V8 0x11
82 #define MXS_BM_SPI2_MASTER_3V3_NOR 0x02
83 #define MXS_BM_SPI2_MASTER_1V8_NOR 0x12
84 #define MXS_BM_SPI3_MASTER_3V3_NOR 0x03
85 #define MXS_BM_SPI3_MASTER_1V8_NOR 0x13
86 #define MXS_BM_NAND_3V3 0x04
87 #define MXS_BM_NAND_1V8 0x14
88 #define MXS_BM_JTAG 0x06
89 #define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08
90 #define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18
91 #define MXS_BM_SDMMC0_3V3 0x09
92 #define MXS_BM_SDMMC0_1V8 0x19
93 #define MXS_BM_SDMMC1_3V3 0x0a
94 #define MXS_BM_SDMMC1_1V8 0x1a
97 uint8_t boot_mode_idx;
98 uint32_t mem_dram_size;
101 int mxs_dram_init(void);
103 #endif /* __SYS_PROTO_H__ */