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1 /*
2  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16
17 /* Tegra30 clock PLL tables */
18
19 #ifndef _TEGRA30_CLOCK_TABLES_H_
20 #define _TEGRA30_CLOCK_TABLES_H_
21
22 /* The PLLs supported by the hardware */
23 enum clock_id {
24         CLOCK_ID_FIRST,
25         CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
26         CLOCK_ID_MEMORY,
27         CLOCK_ID_PERIPH,
28         CLOCK_ID_AUDIO,
29         CLOCK_ID_USB,
30         CLOCK_ID_DISPLAY,
31
32         /* now the simple ones */
33         CLOCK_ID_FIRST_SIMPLE,
34         CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
35         CLOCK_ID_EPCI,
36         CLOCK_ID_SFROM32KHZ,
37
38         /* These are the base clocks (inputs to the Tegra SOC) */
39         CLOCK_ID_32KHZ,
40         CLOCK_ID_OSC,
41
42         CLOCK_ID_COUNT, /* number of PLLs */
43         CLOCK_ID_DISPLAY2,      /* Tegra3, placeholder */
44         CLOCK_ID_NONE = -1,
45 };
46
47 /* The clocks supported by the hardware */
48 enum periph_id {
49         PERIPH_ID_FIRST,
50
51         /* Low word: 31:0 */
52         PERIPH_ID_CPU = PERIPH_ID_FIRST,
53         PERIPH_ID_COP,
54         PERIPH_ID_TRIGSYS,
55         PERIPH_ID_RESERVED3,
56         PERIPH_ID_RESERVED4,
57         PERIPH_ID_TMR,
58         PERIPH_ID_UART1,
59         PERIPH_ID_UART2,
60
61         /* 8 */
62         PERIPH_ID_GPIO,
63         PERIPH_ID_SDMMC2,
64         PERIPH_ID_SPDIF,
65         PERIPH_ID_I2S1,
66         PERIPH_ID_I2C1,
67         PERIPH_ID_NDFLASH,
68         PERIPH_ID_SDMMC1,
69         PERIPH_ID_SDMMC4,
70
71         /* 16 */
72         PERIPH_ID_RESERVED16,
73         PERIPH_ID_PWM,
74         PERIPH_ID_I2S2,
75         PERIPH_ID_EPP,
76         PERIPH_ID_VI,
77         PERIPH_ID_2D,
78         PERIPH_ID_USBD,
79         PERIPH_ID_ISP,
80
81         /* 24 */
82         PERIPH_ID_3D,
83         PERIPH_ID_RESERVED24,
84         PERIPH_ID_DISP2,
85         PERIPH_ID_DISP1,
86         PERIPH_ID_HOST1X,
87         PERIPH_ID_VCP,
88         PERIPH_ID_I2S0,
89         PERIPH_ID_CACHE2,
90
91         /* Middle word: 63:32 */
92         PERIPH_ID_MEM,
93         PERIPH_ID_AHBDMA,
94         PERIPH_ID_APBDMA,
95         PERIPH_ID_RESERVED35,
96         PERIPH_ID_KBC,
97         PERIPH_ID_STAT_MON,
98         PERIPH_ID_PMC,
99         PERIPH_ID_FUSE,
100
101         /* 40 */
102         PERIPH_ID_KFUSE,
103         PERIPH_ID_SBC1,
104         PERIPH_ID_SNOR,
105         PERIPH_ID_RESERVED43,
106         PERIPH_ID_SBC2,
107         PERIPH_ID_RESERVED45,
108         PERIPH_ID_SBC3,
109         PERIPH_ID_DVC_I2C,
110
111         /* 48 */
112         PERIPH_ID_DSI,
113         PERIPH_ID_TVO,
114         PERIPH_ID_MIPI,
115         PERIPH_ID_HDMI,
116         PERIPH_ID_CSI,
117         PERIPH_ID_TVDAC,
118         PERIPH_ID_I2C2,
119         PERIPH_ID_UART3,
120
121         /* 56 */
122         PERIPH_ID_RESERVED56,
123         PERIPH_ID_EMC,
124         PERIPH_ID_USB2,
125         PERIPH_ID_USB3,
126         PERIPH_ID_MPE,
127         PERIPH_ID_VDE,
128         PERIPH_ID_BSEA,
129         PERIPH_ID_BSEV,
130
131         /* Upper word 95:64 */
132         PERIPH_ID_SPEEDO,
133         PERIPH_ID_UART4,
134         PERIPH_ID_UART5,
135         PERIPH_ID_I2C3,
136         PERIPH_ID_SBC4,
137         PERIPH_ID_SDMMC3,
138         PERIPH_ID_PCIE,
139         PERIPH_ID_OWR,
140
141         /* 72 */
142         PERIPH_ID_AFI,
143         PERIPH_ID_CORESIGHT,
144         PERIPH_ID_PCIEXCLK,
145         PERIPH_ID_AVPUCQ,
146         PERIPH_ID_RESERVED76,
147         PERIPH_ID_RESERVED77,
148         PERIPH_ID_RESERVED78,
149         PERIPH_ID_DTV,
150
151         /* 80 */
152         PERIPH_ID_NANDSPEED,
153         PERIPH_ID_I2CSLOW,
154         PERIPH_ID_DSIB,
155         PERIPH_ID_RESERVED83,
156         PERIPH_ID_IRAMA,
157         PERIPH_ID_IRAMB,
158         PERIPH_ID_IRAMC,
159         PERIPH_ID_IRAMD,
160
161         /* 88 */
162         PERIPH_ID_CRAM2,
163         PERIPH_ID_RESERVED89,
164         PERIPH_ID_MDOUBLER,
165         PERIPH_ID_RESERVED91,
166         PERIPH_ID_SUSOUT,
167         PERIPH_ID_RESERVED93,
168         PERIPH_ID_RESERVED94,
169         PERIPH_ID_RESERVED95,
170
171         PERIPH_ID_VW_FIRST,
172         /* V word: 31:0 */
173         PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
174         PERIPH_ID_CPULP,
175         PERIPH_ID_3D2,
176         PERIPH_ID_MSELECT,
177         PERIPH_ID_TSENSOR,
178         PERIPH_ID_I2S3,
179         PERIPH_ID_I2S4,
180         PERIPH_ID_I2C4,
181
182         /* 08 */
183         PERIPH_ID_SBC5,
184         PERIPH_ID_SBC6,
185         PERIPH_ID_AUDIO,
186         PERIPH_ID_APBIF,
187         PERIPH_ID_DAM0,
188         PERIPH_ID_DAM1,
189         PERIPH_ID_DAM2,
190         PERIPH_ID_HDA2CODEC2X,
191
192         /* 16 */
193         PERIPH_ID_ATOMICS,
194         PERIPH_ID_EX_RESERVED17,
195         PERIPH_ID_EX_RESERVED18,
196         PERIPH_ID_EX_RESERVED19,
197         PERIPH_ID_EX_RESERVED20,
198         PERIPH_ID_EX_RESERVED21,
199         PERIPH_ID_EX_RESERVED22,
200         PERIPH_ID_ACTMON,
201
202         /* 24 */
203         PERIPH_ID_EX_RESERVED24,
204         PERIPH_ID_EX_RESERVED25,
205         PERIPH_ID_EX_RESERVED26,
206         PERIPH_ID_EX_RESERVED27,
207         PERIPH_ID_SATA,
208         PERIPH_ID_HDA,
209         PERIPH_ID_EX_RESERVED30,
210         PERIPH_ID_EX_RESERVED31,
211
212         /* W word: 31:0 */
213         PERIPH_ID_HDA2HDMICODEC,
214         PERIPH_ID_SATACOLD,
215         PERIPH_ID_RESERVED0_PCIERX0,
216         PERIPH_ID_RESERVED1_PCIERX1,
217         PERIPH_ID_RESERVED2_PCIERX2,
218         PERIPH_ID_RESERVED3_PCIERX3,
219         PERIPH_ID_RESERVED4_PCIERX4,
220         PERIPH_ID_RESERVED5_PCIERX5,
221
222         /* 40 */
223         PERIPH_ID_CEC,
224         PERIPH_ID_RESERVED6_PCIE2,
225         PERIPH_ID_RESERVED7_EMC,
226         PERIPH_ID_RESERVED8_HDMI,
227         PERIPH_ID_RESERVED9_SATA,
228         PERIPH_ID_RESERVED10_MIPI,
229         PERIPH_ID_EX_RESERVED46,
230         PERIPH_ID_EX_RESERVED47,
231
232         PERIPH_ID_COUNT,
233         PERIPH_ID_NONE = -1,
234 };
235
236 enum pll_out_id {
237         PLL_OUT1,
238         PLL_OUT2,
239         PLL_OUT3,
240         PLL_OUT4
241 };
242
243 /*
244  * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
245  * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
246  * confusion bewteen PERIPH_ID_... and PERIPHC_...
247  *
248  * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
249  * confusing.
250  */
251 enum periphc_internal_id {
252         /* 0x00 */
253         PERIPHC_I2S1,
254         PERIPHC_I2S2,
255         PERIPHC_SPDIF_OUT,
256         PERIPHC_SPDIF_IN,
257         PERIPHC_PWM,
258         PERIPHC_05h,
259         PERIPHC_SBC2,
260         PERIPHC_SBC3,
261
262         /* 0x08 */
263         PERIPHC_08h,
264         PERIPHC_I2C1,
265         PERIPHC_DVC_I2C,
266         PERIPHC_0bh,
267         PERIPHC_0ch,
268         PERIPHC_SBC1,
269         PERIPHC_DISP1,
270         PERIPHC_DISP2,
271
272         /* 0x10 */
273         PERIPHC_CVE,
274         PERIPHC_11h,
275         PERIPHC_VI,
276         PERIPHC_13h,
277         PERIPHC_SDMMC1,
278         PERIPHC_SDMMC2,
279         PERIPHC_G3D,
280         PERIPHC_G2D,
281
282         /* 0x18 */
283         PERIPHC_NDFLASH,
284         PERIPHC_SDMMC4,
285         PERIPHC_VFIR,
286         PERIPHC_EPP,
287         PERIPHC_MPE,
288         PERIPHC_MIPI,
289         PERIPHC_UART1,
290         PERIPHC_UART2,
291
292         /* 0x20 */
293         PERIPHC_HOST1X,
294         PERIPHC_21h,
295         PERIPHC_TVO,
296         PERIPHC_HDMI,
297         PERIPHC_24h,
298         PERIPHC_TVDAC,
299         PERIPHC_I2C2,
300         PERIPHC_EMC,
301
302         /* 0x28 */
303         PERIPHC_UART3,
304         PERIPHC_29h,
305         PERIPHC_VI_SENSOR,
306         PERIPHC_2bh,
307         PERIPHC_2ch,
308         PERIPHC_SBC4,
309         PERIPHC_I2C3,
310         PERIPHC_SDMMC3,
311
312         /* 0x30 */
313         PERIPHC_UART4,
314         PERIPHC_UART5,
315         PERIPHC_VDE,
316         PERIPHC_OWR,
317         PERIPHC_NOR,
318         PERIPHC_CSITE,
319         PERIPHC_I2S0,
320         PERIPHC_37h,
321
322         PERIPHC_VW_FIRST,
323         /* 0x38 */
324         PERIPHC_G3D2 = PERIPHC_VW_FIRST,
325         PERIPHC_MSELECT,
326         PERIPHC_TSENSOR,
327         PERIPHC_I2S3,
328         PERIPHC_I2S4,
329         PERIPHC_I2C4,
330         PERIPHC_SBC5,
331         PERIPHC_SBC6,
332
333         /* 0x40 */
334         PERIPHC_AUDIO,
335         PERIPHC_41h,
336         PERIPHC_DAM0,
337         PERIPHC_DAM1,
338         PERIPHC_DAM2,
339         PERIPHC_HDA2CODEC2X,
340         PERIPHC_ACTMON,
341         PERIPHC_EXTPERIPH1,
342
343         /* 0x48 */
344         PERIPHC_EXTPERIPH2,
345         PERIPHC_EXTPERIPH3,
346         PERIPHC_NANDSPEED,
347         PERIPHC_I2CSLOW,
348         PERIPHC_SYS,
349         PERIPHC_SPEEDO,
350         PERIPHC_4eh,
351         PERIPHC_4fh,
352
353         /* 0x50 */
354         PERIPHC_50h,
355         PERIPHC_51h,
356         PERIPHC_52h,
357         PERIPHC_53h,
358         PERIPHC_SATAOOB,
359         PERIPHC_SATA,
360         PERIPHC_HDA,
361
362         PERIPHC_COUNT,
363
364         PERIPHC_NONE = -1,
365 };
366
367 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
368 #define PERIPH_REG(id) \
369         (id < PERIPH_ID_VW_FIRST) ? \
370                 ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
371
372 /* Mask value for a clock (within PERIPH_REG(id)) */
373 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
374
375 /* return 1 if a PLL ID is in range */
376 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
377
378 /* return 1 if a peripheral ID is in range */
379 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
380                 (id) < PERIPH_ID_COUNT)
381
382 #endif  /* _TEGRA30_CLOCK_TABLES_H_ */