3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/system.h>
10 #include <asm/cache.h>
11 #include <linux/compiler.h>
13 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
15 DECLARE_GLOBAL_DATA_PTR;
17 void __arm_init_before_mmu(void)
20 void arm_init_before_mmu(void)
21 __attribute__((weak, alias("__arm_init_before_mmu")));
23 __weak void arm_init_domains(void)
27 void set_section_dcache(int section, enum dcache_option option)
29 u32 *page_table = (u32 *)gd->arch.tlb_addr;
32 value = (section << MMU_SECTION_SHIFT) | (3 << 10);
34 page_table[section] = value;
37 void __mmu_page_table_flush(unsigned long start, unsigned long stop)
39 debug("%s: Warning: not implemented\n", __func__);
42 void mmu_page_table_flush(unsigned long start, unsigned long stop)
43 __attribute__((weak, alias("__mmu_page_table_flush")));
45 void mmu_set_region_dcache_behaviour(u32 start, int size,
46 enum dcache_option option)
48 u32 *page_table = (u32 *)gd->arch.tlb_addr;
51 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
52 start = start >> MMU_SECTION_SHIFT;
53 debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
55 for (upto = start; upto < end; upto++)
56 set_section_dcache(upto, option);
57 mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
60 __weak void dram_bank_mmu_setup(int bank)
65 debug("%s: bank: %d\n", __func__, bank);
66 for (i = bd->bi_dram[bank].start >> 20;
67 i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
69 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
70 set_section_dcache(i, DCACHE_WRITETHROUGH);
72 set_section_dcache(i, DCACHE_WRITEBACK);
77 /* to activate the MMU we need to set up virtual memory: use 1M areas */
78 static inline void mmu_setup(void)
83 arm_init_before_mmu();
84 /* Set up an identity-mapping for all 4GB, rw for everyone */
85 for (i = 0; i < 4096; i++)
86 set_section_dcache(i, DCACHE_OFF);
88 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
89 dram_bank_mmu_setup(i);
93 /* Copy the page table address to cp15 */
94 "mcr p15, 0, %0, c2, c0, 0\n"
95 /* Set the access control to all-supervisor */
96 "mcr p15, 0, %1, c3, c0, 0\n"
98 : "r"(gd->arch.tlb_addr), "r"(~0)
104 /* and enable the mmu */
105 reg = get_cr(); /* get control reg. */
109 static int mmu_enabled(void)
111 return get_cr() & CR_M;
114 /* cache_bit must be either CR_I or CR_C */
115 static void cache_enable(uint32_t cache_bit)
119 /* The data cache is not active unless the mmu is enabled too */
120 if ((cache_bit == CR_C) && !mmu_enabled())
122 reg = get_cr(); /* get control reg. */
123 set_cr(reg | cache_bit);
126 /* cache_bit must be either CR_I or CR_C */
127 static void cache_disable(uint32_t cache_bit)
133 if (cache_bit == CR_C) {
134 /* if cache isn;t enabled no need to disable */
135 if ((reg & CR_C) != CR_C)
137 /* if disabling data cache, disable mmu too */
141 if (cache_bit == (CR_C | CR_M))
143 set_cr(reg & ~cache_bit);
147 #ifdef CONFIG_SYS_ICACHE_OFF
148 void icache_enable (void)
153 void icache_disable (void)
158 int icache_status (void)
160 return 0; /* always off */
163 void icache_enable(void)
168 void icache_disable(void)
173 int icache_status(void)
175 return (get_cr() & CR_I) != 0;
179 #ifdef CONFIG_SYS_DCACHE_OFF
180 void dcache_enable (void)
185 void dcache_disable (void)
190 int dcache_status (void)
192 return 0; /* always off */
195 void dcache_enable(void)
200 void dcache_disable(void)
205 int dcache_status(void)
207 return (get_cr() & CR_C) != 0;