arch/arm/mach-socfpga/spl.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/pl310.h>
  10 #include <asm/u-boot.h>
  11 #include <asm/utils.h>
  12 #include <image.h>
  13 #include <asm/arch/reset_manager.h>
  14 #include <spl.h>
  15 #include <asm/arch/system_manager.h>
  16 #include <asm/arch/freeze_controller.h>
  17 #include <asm/arch/clock_manager.h>
  18 #include <asm/arch/scan_manager.h>
  19 #include <asm/arch/sdram.h>
  20 #include <asm/arch/scu.h>
  21 #include <asm/arch/nic301.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 static struct pl310_regs *const pl310 =
  26         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  27 static struct scu_registers *scu_regs =
  28         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  29 static struct nic301_registers *nic301_regs =
  30         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  31
  32 static void socfpga_nic301_slave_ns(void)
  33 {
  34         writel(0x1, &nic301_regs->lwhps2fpgaregs);
  35         writel(0x1, &nic301_regs->hps2fpgaregs);
  36         writel(0x1, &nic301_regs->acp);
  37         writel(0x1, &nic301_regs->rom);
  38         writel(0x1, &nic301_regs->ocram);
  39         writel(0x1, &nic301_regs->sdrdata);
  40 }
  41
  42 void board_init_f(ulong dummy)
  43 {
  44         struct socfpga_system_manager *sysmgr_regs =
  45                 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  46         unsigned long reg;
  47         /*
  48          * First C code to run. Clear fake OCRAM ECC first as SBE
  49          * and DBE might triggered during power on
  50          */
  51         reg = readl(&sysmgr_regs->eccgrp_ocram);
  52         if (reg & SYSMGR_ECC_OCRAM_SERR)
  53                 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
  54                        &sysmgr_regs->eccgrp_ocram);
  55         if (reg & SYSMGR_ECC_OCRAM_DERR)
  56                 writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
  57                        &sysmgr_regs->eccgrp_ocram);
  58
  59         memset(__bss_start, 0, __bss_end - __bss_start);
  60
  61         socfpga_nic301_slave_ns();
  62
  63         /* Configure ARM MPU SNSAC register. */
  64         setbits_le32(&scu_regs->sacr, 0xfff);
  65
  66         /* Remap SDRAM to 0x0 */
  67         writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
  68         writel(0x1, &pl310->pl310_addr_filter_start);
  69
  70         board_init_r(NULL, 0);
  71 }
  72
  73 u32 spl_boot_device(void)
  74 {
  75         return BOOT_DEVICE_RAM;
  76 }
  77
  78 /*
  79  * Board initialization after bss clearance
  80  */
  81 void spl_board_init(void)
  82 {
  83         unsigned long sdram_size;
  84 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
  85         const struct cm_config *cm_default_cfg = cm_get_default_config();
  86 #endif
  87
  88         debug("Freezing all I/O banks\n");
  89         /* freeze all IO banks */
  90         sys_mgr_frzctrl_freeze_req();
  91
  92         socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
  93         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
  94         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
  95
  96         timer_init();
  97
  98         debug("Reconfigure Clock Manager\n");
  99         /* reconfigure the PLLs */
 100         cm_basic_init(cm_default_cfg);
 101
 102         /* Enable bootrom to configure IOs. */
 103         sysmgr_config_warmrstcfgio(1);
 104
 105         /* configure the IOCSR / IO buffer settings */
 106         if (scan_mgr_configure_iocsr())
 107                 hang();
 108
 109         sysmgr_config_warmrstcfgio(0);
 110
 111         /* configure the pin muxing through system manager */
 112         sysmgr_config_warmrstcfgio(1);
 113         sysmgr_pinmux_init();
 114         sysmgr_config_warmrstcfgio(0);
 115
 116 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
 117
 118         /* de-assert reset for peripherals and bridges based on handoff */
 119         reset_deassert_peripherals_handoff();
 120
 121         debug("Unfreezing/Thaw all I/O banks\n");
 122         /* unfreeze / thaw all IO banks */
 123         sys_mgr_frzctrl_thaw_req();
 124
 125         /* enable console uart printing */
 126         preloader_console_init();
 127
 128         if (sdram_mmr_init_full(0xffffffff) != 0) {
 129                 puts("SDRAM init failed.\n");
 130                 hang();
 131         }
 132
 133         debug("SDRAM: Calibrating PHY\n");
 134         /* SDRAM calibration */
 135         if (sdram_calibration_full() == 0) {
 136                 puts("SDRAM calibration failed.\n");
 137                 hang();
 138         }
 139
 140         sdram_size = sdram_calculate_size();
 141         debug("SDRAM: %ld MiB\n", sdram_size >> 20);
 142
 143         /* Sanity check ensure correct SDRAM size specified */
 144         if (get_ram_size(0, sdram_size) != sdram_size) {
 145                 puts("SDRAM size check failed!\n");
 146                 hang();
 147         }
 148 }