2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
36 #include <asm/fsl_law.h>
37 #include <asm/fsl_serdes.h>
40 DECLARE_GLOBAL_DATA_PTR;
43 extern qe_iop_conf_t qe_iop_conf_tab[];
44 extern void qe_config_iopin(u8 port, u8 pin, int dir,
45 int open_drain, int assign);
46 extern void qe_init(uint qe_base);
47 extern void qe_reset(void);
49 static void config_qe_ioports(void)
52 int dir, open_drain, assign;
55 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
56 port = qe_iop_conf_tab[i].port;
57 pin = qe_iop_conf_tab[i].pin;
58 dir = qe_iop_conf_tab[i].dir;
59 open_drain = qe_iop_conf_tab[i].open_drain;
60 assign = qe_iop_conf_tab[i].assign;
61 qe_config_iopin(port, pin, dir, open_drain, assign);
67 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
71 for (portnum = 0; portnum < 4; portnum++) {
78 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
79 iop_conf_t *eiopc = iopc + 32;
84 * index 0 refers to pin 31,
85 * index 31 refers to pin 0
87 while (iopc < eiopc) {
107 volatile ioport_t *iop = ioport_addr (cpm, portnum);
111 * the (somewhat confused) paragraph at the
112 * bottom of page 35-5 warns that there might
113 * be "unknown behaviour" when programming
114 * PSORx and PDIRx, if PPARx = 1, so I
115 * decided this meant I had to disable the
116 * dedicated function first, and enable it
120 iop->psor = (iop->psor & tpmsk) | psor;
121 iop->podr = (iop->podr & tpmsk) | podr;
122 iop->pdat = (iop->pdat & tpmsk) | pdat;
123 iop->pdir = (iop->pdir & tpmsk) | pdir;
131 * Breathe some life into the CPU...
133 * Set up the memory map
134 * initialize a bunch of registers
137 #ifdef CONFIG_FSL_CORENET
138 static void corenet_tb_init(void)
140 volatile ccsr_rcpm_t *rcpm =
141 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
142 volatile ccsr_pic_t *pic =
143 (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
144 u32 whoami = in_be32(&pic->whoami);
146 /* Enable the timebase register for this core */
147 out_be32(&rcpm->ctbenrl, (1 << whoami));
151 void cpu_init_f (void)
153 extern void m8560_cpm_reset (void);
154 #ifdef CONFIG_MPC8548
155 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
156 uint svr = get_svr();
159 * CPU2 errata workaround: A core hang possible while executing
160 * a msync instruction and a snoopable transaction from an I/O
161 * master tagged to make quick forward progress is present.
162 * Fixed in silicon rev 2.1.
164 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
165 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
172 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
175 init_early_memctl_regs();
177 #if defined(CONFIG_CPM2)
181 /* Config QE ioports */
184 #if defined(CONFIG_FSL_DMA)
187 #ifdef CONFIG_FSL_CORENET
190 init_used_tlb_cams();
195 * Initialize L2 as cache.
197 * The newer 8548, etc, parts have twice as much cache, but
198 * use the same bit-encoding as the older 8555, etc, parts.
204 #ifdef CONFIG_SYS_LBC_LCRR
205 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
210 #if defined(CONFIG_L2_CACHE)
211 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
212 volatile uint cache_ctl;
218 ver = SVR_SOC_VER(svr);
221 cache_ctl = l2cache->l2ctl;
223 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
224 if (cache_ctl & MPC85xx_L2CTL_L2E) {
225 /* Clear L2 SRAM memory-mapped base address */
226 out_be32(&l2cache->l2srbar0, 0x0);
227 out_be32(&l2cache->l2srbar1, 0x0);
229 /* set MBECCDIS=0, SBECCDIS=0 */
230 clrbits_be32(&l2cache->l2errdis,
231 (MPC85xx_L2ERRDIS_MBECC |
232 MPC85xx_L2ERRDIS_SBECC));
234 /* set L2E=0, L2SRAM=0 */
235 clrbits_be32(&l2cache->l2ctl,
237 MPC85xx_L2CTL_L2SRAM_ENTIRE));
241 l2siz_field = (cache_ctl >> 28) & 0x3;
243 switch (l2siz_field) {
245 printf(" unknown size (0x%08x)\n", cache_ctl);
249 if (ver == SVR_8540 || ver == SVR_8560 ||
250 ver == SVR_8541 || ver == SVR_8541_E ||
251 ver == SVR_8555 || ver == SVR_8555_E) {
253 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
254 cache_ctl = 0xc4000000;
257 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
261 if (ver == SVR_8540 || ver == SVR_8560 ||
262 ver == SVR_8541 || ver == SVR_8541_E ||
263 ver == SVR_8555 || ver == SVR_8555_E) {
265 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
266 cache_ctl = 0xc8000000;
269 /* set L2E=1, L2I=1, & L2SRAM=0 */
270 cache_ctl = 0xc0000000;
275 /* set L2E=1, L2I=1, & L2SRAM=0 */
276 cache_ctl = 0xc0000000;
280 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
281 puts("already enabled");
282 l2srbar = l2cache->l2srbar0;
283 #ifdef CONFIG_SYS_INIT_L2_ADDR
284 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
285 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
286 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
287 l2cache->l2srbar0 = l2srbar;
288 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
290 #endif /* CONFIG_SYS_INIT_L2_ADDR */
294 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
298 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
299 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
301 /* invalidate the L2 cache */
302 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
303 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
306 #ifdef CONFIG_SYS_CACHE_STASHING
307 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
308 mtspr(SPRN_L2CSR1, (32 + 1));
311 /* enable the cache */
312 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
314 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
315 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
317 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
323 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
328 #if defined(CONFIG_SYS_HAS_SERDES)
329 /* needs to be in ram since code uses global static vars */
333 #if defined(CONFIG_MP)
337 #ifdef CONFIG_SYS_LBC_LCRR
339 * Modify the CLKDIV field of LCRR register to improve the writing
340 * speed for NOR flash.
342 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
343 __raw_readl(&lbc->lcrr);
350 extern void setup_ivors(void);
352 void arch_preboot_os(void)
357 * We are changing interrupt offsets and are about to boot the OS so
358 * we need to make sure we disable all async interrupts. EE is already
359 * disabled by the time we get called.
362 msr &= ~(MSR_ME|MSR_CE|MSR_DE);
368 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
369 int sata_initialize(void)
371 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
372 return __sata_initialize();