arch/powerpc/cpu/mpc8xx/i2c.c

   1 /*
   2  * (C) Copyright 2000
   3  * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
   4  *
   5  * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   6  * Marius Groeger <mgroeger@sysgo.de>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  *
  10  * Back ported to the 8xx platform (from the 8260 platform) by
  11  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  12  */
  13
  14 #include <common.h>
  15
  16 #ifdef CONFIG_HARD_I2C
  17
  18 #include <commproc.h>
  19 #include <i2c.h>
  20 #ifdef CONFIG_LWMON
  21 #include <watchdog.h>
  22 #endif
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 /* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
  27 #define TOUT_LOOP 1000000
  28
  29 #define NUM_RX_BDS 4
  30 #define NUM_TX_BDS 4
  31 #define MAX_TX_SPACE 256
  32 #define I2C_RXTX_LEN 128        /* maximum tx/rx buffer length */
  33
  34 typedef struct I2C_BD {
  35         unsigned short status;
  36         unsigned short length;
  37         unsigned char *addr;
  38 } I2C_BD;
  39
  40 #define BD_I2C_TX_START 0x0400  /* special status for i2c: Start condition */
  41
  42 #define BD_I2C_TX_CL    0x0001  /* collision error */
  43 #define BD_I2C_TX_UN    0x0002  /* underflow error */
  44 #define BD_I2C_TX_NAK   0x0004  /* no acknowledge error */
  45 #define BD_I2C_TX_ERR   (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
  46
  47 #define BD_I2C_RX_ERR   BD_SC_OV
  48
  49 typedef void (*i2c_ecb_t) (int, int);   /* error callback function */
  50
  51 /* This structure keeps track of the bd and buffer space usage. */
  52 typedef struct i2c_state {
  53         int rx_idx;             /* index   to next free Rx BD */
  54         int tx_idx;             /* index   to next free Tx BD */
  55         void *rxbd;             /* pointer to next free Rx BD */
  56         void *txbd;             /* pointer to next free Tx BD */
  57         int tx_space;           /* number  of Tx bytes left   */
  58         unsigned char *tx_buf;  /* pointer to free Tx area    */
  59         i2c_ecb_t err_cb;       /* error callback function    */
  60 } i2c_state_t;
  61
  62
  63 /* flags for i2c_send() and i2c_receive() */
  64 #define I2CF_ENABLE_SECONDARY   0x01  /* secondary_address is valid           */
  65 #define I2CF_START_COND         0x02  /* tx: generate start condition         */
  66 #define I2CF_STOP_COND          0x04  /* tx: generate stop  condition         */
  67
  68 /* return codes */
  69 #define I2CERR_NO_BUFFERS       0x01  /* no more BDs or buffer space          */
  70 #define I2CERR_MSG_TOO_LONG     0x02  /* tried to send/receive to much data   */
  71 #define I2CERR_TIMEOUT          0x03  /* timeout in i2c_doio()                */
  72 #define I2CERR_QUEUE_EMPTY      0x04  /* i2c_doio called without send/receive */
  73
  74 /* error callback flags */
  75 #define I2CECB_RX_ERR           0x10  /* this is a receive error              */
  76 #define     I2CECB_RX_ERR_OV    0x02  /* receive overrun error                */
  77 #define     I2CECB_RX_MASK      0x0f  /* mask for error bits                  */
  78 #define I2CECB_TX_ERR           0x20  /* this is a transmit error             */
  79 #define     I2CECB_TX_CL        0x01  /* transmit collision error             */
  80 #define     I2CECB_TX_UN        0x02  /* transmit underflow error             */
  81 #define     I2CECB_TX_NAK       0x04  /* transmit no ack error                */
  82 #define     I2CECB_TX_MASK      0x0f  /* mask for error bits                  */
  83 #define I2CECB_TIMEOUT          0x40  /* this is a timeout error              */
  84
  85 /*
  86  * Returns the best value of I2BRG to meet desired clock speed of I2C with
  87  * input parameters (clock speed, filter, and predivider value).
  88  * It returns computer speed value and the difference between it and desired
  89  * speed.
  90  */
  91 static inline int
  92 i2c_roundrate(int hz, int speed, int filter, int modval,
  93               int *brgval, int *totspeed)
  94 {
  95         int moddiv = 1 << (5 - (modval & 3)), brgdiv, div;
  96
  97         debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
  98                 hz, speed, filter, modval);
  99
 100         div = moddiv * speed;
 101         brgdiv = (hz + div - 1) / div;
 102
 103         debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv);
 104
 105         *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter);
 106
 107         if ((*brgval < 0) || (*brgval > 255)) {
 108                 debug("\t\trejected brgval=%d\n", *brgval);
 109                 return -1;
 110         }
 111
 112         brgdiv = 2 * (*brgval + 3 + (2 * filter));
 113         div = moddiv * brgdiv;
 114         *totspeed = hz / div;
 115
 116         debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed);
 117
 118         return 0;
 119 }
 120
 121 /*
 122  * Sets the I2C clock predivider and divider to meet required clock speed.
 123  */
 124 static int i2c_setrate(int hz, int speed)
 125 {
 126         immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 127         volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c;
 128         int     brgval,
 129                 modval, /* 0-3 */
 130                 bestspeed_diff = speed,
 131                 bestspeed_brgval = 0,
 132                 bestspeed_modval = 0,
 133                 bestspeed_filter = 0,
 134                 totspeed,
 135                 filter = 0;     /* Use this fixed value */
 136
 137         for (modval = 0; modval < 4; modval++) {
 138                 if (i2c_roundrate
 139                     (hz, speed, filter, modval, &brgval, &totspeed) == 0) {
 140                         int diff = speed - totspeed;
 141
 142                         if ((diff >= 0) && (diff < bestspeed_diff)) {
 143                                 bestspeed_diff = diff;
 144                                 bestspeed_modval = modval;
 145                                 bestspeed_brgval = brgval;
 146                                 bestspeed_filter = filter;
 147                         }
 148                 }
 149         }
 150
 151         debug("[I2C] Best is:\n");
 152         debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
 153                 hz,
 154                 speed,
 155                 bestspeed_filter,
 156                 bestspeed_modval,
 157                 bestspeed_brgval,
 158                 bestspeed_diff);
 159
 160         i2c->i2c_i2mod |=
 161                 ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
 162         i2c->i2c_i2brg = bestspeed_brgval & 0xff;
 163
 164         debug("[I2C] i2mod=%08x i2brg=%08x\n",
 165                 i2c->i2c_i2mod,
 166                 i2c->i2c_i2brg);
 167
 168         return 1;
 169 }
 170
 171 void i2c_init(int speed, int slaveaddr)
 172 {
 173         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 174         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 175         volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
 176         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 177         ulong rbase, tbase;
 178         volatile I2C_BD *rxbd, *txbd;
 179         uint dpaddr;
 180
 181 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 182         /* call board specific i2c bus reset routine before accessing the   */
 183         /* environment, which might be in a chip on that bus. For details   */
 184         /* about this problem see doc/I2C_Edge_Conditions.                  */
 185         i2c_init_board();
 186 #endif
 187
 188 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 189         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 190 #else
 191         /* Disable relocation */
 192         iip->iic_rpbase = 0;
 193 #endif
 194
 195 #ifdef CONFIG_SYS_ALLOC_DPRAM
 196         dpaddr = iip->iic_rbase;
 197         if (dpaddr == 0) {
 198                 /* need to allocate dual port ram */
 199                 dpaddr = dpram_alloc_align((NUM_RX_BDS * sizeof(I2C_BD)) +
 200                                            (NUM_TX_BDS * sizeof(I2C_BD)) +
 201                                            MAX_TX_SPACE, 8);
 202         }
 203 #else
 204         dpaddr = CPM_I2C_BASE;
 205 #endif
 206
 207         /*
 208          * initialise data in dual port ram:
 209          *
 210          * dpaddr->rbase -> rx BD         (NUM_RX_BDS * sizeof(I2C_BD) bytes)
 211          *         tbase -> tx BD         (NUM_TX_BDS * sizeof(I2C_BD) bytes)
 212          *                  tx buffer     (MAX_TX_SPACE bytes)
 213          */
 214
 215         rbase = dpaddr;
 216         tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
 217
 218         /* Initialize Port B I2C pins. */
 219         cp->cp_pbpar |= 0x00000030;
 220         cp->cp_pbdir |= 0x00000030;
 221         cp->cp_pbodr |= 0x00000030;
 222
 223         /* Disable interrupts */
 224         i2c->i2c_i2mod = 0x00;
 225         i2c->i2c_i2cmr = 0x00;
 226         i2c->i2c_i2cer = 0xff;
 227         i2c->i2c_i2add = slaveaddr;
 228
 229         /*
 230          * Set the I2C BRG Clock division factor from desired i2c rate
 231          * and current CPU rate (we assume sccr dfbgr field is 0;
 232          * divide BRGCLK by 1)
 233          */
 234         debug("[I2C] Setting rate...\n");
 235         i2c_setrate(gd->cpu_clk, CONFIG_SYS_I2C_SPEED);
 236
 237         /* Set I2C controller in master mode */
 238         i2c->i2c_i2com = 0x01;
 239
 240         /* Set SDMA bus arbitration level to 5 (SDCR) */
 241         immap->im_siu_conf.sc_sdcr = 0x0001;
 242
 243         /* Initialize Tx/Rx parameters */
 244         iip->iic_rbase = rbase;
 245         iip->iic_tbase = tbase;
 246         rxbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_rbase]);
 247         txbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_tbase]);
 248
 249         debug("[I2C] rbase = %04x\n", iip->iic_rbase);
 250         debug("[I2C] tbase = %04x\n", iip->iic_tbase);
 251         debug("[I2C] rxbd = %08x\n", (int)rxbd);
 252         debug("[I2C] txbd = %08x\n", (int)txbd);
 253
 254         /* Set big endian byte order */
 255         iip->iic_tfcr = 0x10;
 256         iip->iic_rfcr = 0x10;
 257
 258         /* Set maximum receive size. */
 259         iip->iic_mrblr = I2C_RXTX_LEN;
 260
 261 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 262         /*
 263          *  Initialize required parameters if using microcode patch.
 264          */
 265         iip->iic_rbptr = iip->iic_rbase;
 266         iip->iic_tbptr = iip->iic_tbase;
 267         iip->iic_rstate = 0;
 268         iip->iic_tstate = 0;
 269 #else
 270         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 271         do {
 272                 __asm__ __volatile__("eieio");
 273         } while (cp->cp_cpcr & CPM_CR_FLG);
 274 #endif
 275
 276         /* Clear events and interrupts */
 277         i2c->i2c_i2cer = 0xff;
 278         i2c->i2c_i2cmr = 0x00;
 279 }
 280
 281 static void i2c_newio(i2c_state_t *state)
 282 {
 283         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 284         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 285         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 286
 287         debug("[I2C] i2c_newio\n");
 288
 289 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 290         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 291 #endif
 292         state->rx_idx = 0;
 293         state->tx_idx = 0;
 294         state->rxbd = (void *)&cp->cp_dpmem[iip->iic_rbase];
 295         state->txbd = (void *)&cp->cp_dpmem[iip->iic_tbase];
 296         state->tx_space = MAX_TX_SPACE;
 297         state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
 298         state->err_cb = NULL;
 299
 300         debug("[I2C] rxbd = %08x\n", (int)state->rxbd);
 301         debug("[I2C] txbd = %08x\n", (int)state->txbd);
 302         debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf);
 303
 304         /* clear the buffer memory */
 305         memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
 306 }
 307
 308 static int
 309 i2c_send(i2c_state_t *state,
 310          unsigned char address,
 311          unsigned char secondary_address,
 312          unsigned int flags, unsigned short size, unsigned char *dataout)
 313 {
 314         volatile I2C_BD *txbd;
 315         int i, j;
 316
 317         debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
 318                 address, secondary_address, flags, size);
 319
 320         /* trying to send message larger than BD */
 321         if (size > I2C_RXTX_LEN)
 322                 return I2CERR_MSG_TOO_LONG;
 323
 324         /* no more free bds */
 325         if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
 326                 return I2CERR_NO_BUFFERS;
 327
 328         txbd = (I2C_BD *) state->txbd;
 329         txbd->addr = state->tx_buf;
 330
 331         debug("[I2C] txbd = %08x\n", (int)txbd);
 332
 333         if (flags & I2CF_START_COND) {
 334                 debug("[I2C] Formatting addresses...\n");
 335                 if (flags & I2CF_ENABLE_SECONDARY) {
 336                         /* Length of msg + dest addr */
 337                         txbd->length = size + 2;
 338
 339                         txbd->addr[0] = address << 1;
 340                         txbd->addr[1] = secondary_address;
 341                         i = 2;
 342                 } else {
 343                         /* Length of msg + dest addr */
 344                         txbd->length = size + 1;
 345                         /* Write dest addr to BD */
 346                         txbd->addr[0] = address << 1;
 347                         i = 1;
 348                 }
 349         } else {
 350                 txbd->length = size;    /* Length of message */
 351                 i = 0;
 352         }
 353
 354         /* set up txbd */
 355         txbd->status = BD_SC_READY;
 356         if (flags & I2CF_START_COND)
 357                 txbd->status |= BD_I2C_TX_START;
 358         if (flags & I2CF_STOP_COND)
 359                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 360
 361         /* Copy data to send into buffer */
 362         debug("[I2C] copy data...\n");
 363         for(j = 0; j < size; i++, j++)
 364                 txbd->addr[i] = dataout[j];
 365
 366         debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 367                 txbd->length,
 368                 txbd->status,
 369                 txbd->addr[0],
 370                 txbd->addr[1]);
 371
 372         /* advance state */
 373         state->tx_buf += txbd->length;
 374         state->tx_space -= txbd->length;
 375         state->tx_idx++;
 376         state->txbd = (void *) (txbd + 1);
 377
 378         return 0;
 379 }
 380
 381 static int
 382 i2c_receive(i2c_state_t *state,
 383             unsigned char address,
 384             unsigned char secondary_address,
 385             unsigned int flags,
 386             unsigned short size_to_expect, unsigned char *datain)
 387 {
 388         volatile I2C_BD *rxbd, *txbd;
 389
 390         debug("[I2C] i2c_receive %02d %02d %02d\n",
 391                 address, secondary_address, flags);
 392
 393         /* Expected to receive too much */
 394         if (size_to_expect > I2C_RXTX_LEN)
 395                 return I2CERR_MSG_TOO_LONG;
 396
 397         /* no more free bds */
 398         if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
 399             || state->tx_space < 2)
 400                 return I2CERR_NO_BUFFERS;
 401
 402         rxbd = (I2C_BD *) state->rxbd;
 403         txbd = (I2C_BD *) state->txbd;
 404
 405         debug("[I2C] rxbd = %08x\n", (int)rxbd);
 406         debug("[I2C] txbd = %08x\n", (int)txbd);
 407
 408         txbd->addr = state->tx_buf;
 409
 410         /* set up TXBD for destination address */
 411         if (flags & I2CF_ENABLE_SECONDARY) {
 412                 txbd->length = 2;
 413                 txbd->addr[0] = address << 1;   /* Write data */
 414                 txbd->addr[1] = secondary_address;      /* Internal address */
 415                 txbd->status = BD_SC_READY;
 416         } else {
 417                 txbd->length = 1 + size_to_expect;
 418                 txbd->addr[0] = (address << 1) | 0x01;
 419                 txbd->status = BD_SC_READY;
 420                 memset(&txbd->addr[1], 0, txbd->length);
 421         }
 422
 423         /* set up rxbd for reception */
 424         rxbd->status = BD_SC_EMPTY;
 425         rxbd->length = size_to_expect;
 426         rxbd->addr = datain;
 427
 428         txbd->status |= BD_I2C_TX_START;
 429         if (flags & I2CF_STOP_COND) {
 430                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 431                 rxbd->status |= BD_SC_WRAP;
 432         }
 433
 434         debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 435                 txbd->length,
 436                 txbd->status,
 437                 txbd->addr[0],
 438                 txbd->addr[1]);
 439         debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 440                 rxbd->length,
 441                 rxbd->status,
 442                 rxbd->addr[0],
 443                 rxbd->addr[1]);
 444
 445         /* advance state */
 446         state->tx_buf += txbd->length;
 447         state->tx_space -= txbd->length;
 448         state->tx_idx++;
 449         state->txbd = (void *) (txbd + 1);
 450         state->rx_idx++;
 451         state->rxbd = (void *) (rxbd + 1);
 452
 453         return 0;
 454 }
 455
 456
 457 static int i2c_doio(i2c_state_t *state)
 458 {
 459         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 460         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 461         volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
 462         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 463         volatile I2C_BD *txbd, *rxbd;
 464         volatile int j = 0;
 465
 466         debug("[I2C] i2c_doio\n");
 467
 468 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 469         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 470 #endif
 471
 472         if (state->tx_idx <= 0 && state->rx_idx <= 0) {
 473                 debug("[I2C] No I/O is queued\n");
 474                 return I2CERR_QUEUE_EMPTY;
 475         }
 476
 477         iip->iic_rbptr = iip->iic_rbase;
 478         iip->iic_tbptr = iip->iic_tbase;
 479
 480         /* Enable I2C */
 481         debug("[I2C] Enabling I2C...\n");
 482         i2c->i2c_i2mod |= 0x01;
 483
 484         /* Begin transmission */
 485         i2c->i2c_i2com |= 0x80;
 486
 487         /* Loop until transmit & receive completed */
 488
 489         if (state->tx_idx > 0) {
 490                 txbd = ((I2C_BD*)state->txbd) - 1;
 491
 492                 debug("[I2C] Transmitting...(txbd=0x%08lx)\n",
 493                         (ulong)txbd);
 494
 495                 while ((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
 496                         if (ctrlc())
 497                                 return (-1);
 498
 499                         __asm__ __volatile__("eieio");
 500                 }
 501         }
 502
 503         if ((state->rx_idx > 0) && (j < TOUT_LOOP)) {
 504                 rxbd = ((I2C_BD*)state->rxbd) - 1;
 505
 506                 debug("[I2C] Receiving...(rxbd=0x%08lx)\n",
 507                         (ulong)rxbd);
 508
 509                 while ((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
 510                         if (ctrlc())
 511                                 return (-1);
 512
 513                         __asm__ __volatile__("eieio");
 514                 }
 515         }
 516
 517         /* Turn off I2C */
 518         i2c->i2c_i2mod &= ~0x01;
 519
 520         if (state->err_cb != NULL) {
 521                 int n, i, b;
 522
 523                 /*
 524                  * if we have an error callback function, look at the
 525                  * error bits in the bd status and pass them back
 526                  */
 527
 528                 if ((n = state->tx_idx) > 0) {
 529                         for (i = 0; i < n; i++) {
 530                                 txbd = ((I2C_BD *) state->txbd) - (n - i);
 531                                 if ((b = txbd->status & BD_I2C_TX_ERR) != 0)
 532                                         (*state->err_cb) (I2CECB_TX_ERR | b,
 533                                                           i);
 534                         }
 535                 }
 536
 537                 if ((n = state->rx_idx) > 0) {
 538                         for (i = 0; i < n; i++) {
 539                                 rxbd = ((I2C_BD *) state->rxbd) - (n - i);
 540                                 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0)
 541                                         (*state->err_cb) (I2CECB_RX_ERR | b,
 542                                                           i);
 543                         }
 544                 }
 545
 546                 if (j >= TOUT_LOOP)
 547                         (*state->err_cb) (I2CECB_TIMEOUT, 0);
 548         }
 549
 550         return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0;
 551 }
 552
 553 static int had_tx_nak;
 554
 555 static void i2c_test_callback(int flags, int xnum)
 556 {
 557         if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK))
 558                 had_tx_nak = 1;
 559 }
 560
 561 int i2c_probe(uchar chip)
 562 {
 563         i2c_state_t state;
 564         int rc;
 565         uchar buf[1];
 566
 567         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 568
 569         i2c_newio(&state);
 570
 571         state.err_cb = i2c_test_callback;
 572         had_tx_nak = 0;
 573
 574         rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1,
 575                          buf);
 576
 577         if (rc != 0)
 578                 return (rc);
 579
 580         rc = i2c_doio(&state);
 581
 582         if ((rc != 0) && (rc != I2CERR_TIMEOUT))
 583                 return (rc);
 584
 585         return (had_tx_nak);
 586 }
 587
 588 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 589 {
 590         i2c_state_t state;
 591         uchar xaddr[4];
 592         int rc;
 593
 594 #ifdef CONFIG_LWMON
 595         WATCHDOG_RESET();
 596 #endif
 597
 598         xaddr[0] = (addr >> 24) & 0xFF;
 599         xaddr[1] = (addr >> 16) & 0xFF;
 600         xaddr[2] = (addr >> 8) & 0xFF;
 601         xaddr[3] = addr & 0xFF;
 602
 603 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 604         /*
 605          * EEPROM chips that implement "address overflow" are ones like
 606          * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
 607          * extra bits end up in the "chip address" bit slots.  This makes
 608          * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
 609          *
 610          * Note that we consider the length of the address field to still
 611          * be one byte because the extra address bits are hidden in the
 612          * chip address.
 613          */
 614         chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 615 #endif
 616
 617         i2c_newio(&state);
 618
 619         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
 620                       &xaddr[4 - alen]);
 621         if (rc != 0) {
 622                 printf("i2c_read: i2c_send failed (%d)\n", rc);
 623                 return 1;
 624         }
 625
 626         rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
 627         if (rc != 0) {
 628                 printf("i2c_read: i2c_receive failed (%d)\n", rc);
 629                 return 1;
 630         }
 631
 632         rc = i2c_doio(&state);
 633         if (rc != 0) {
 634                 printf("i2c_read: i2c_doio failed (%d)\n", rc);
 635                 return 1;
 636         }
 637         return 0;
 638 }
 639
 640 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 641 {
 642         i2c_state_t state;
 643         uchar xaddr[4];
 644         int rc;
 645
 646         xaddr[0] = (addr >> 24) & 0xFF;
 647         xaddr[1] = (addr >> 16) & 0xFF;
 648         xaddr[2] = (addr >> 8) & 0xFF;
 649         xaddr[3] = addr & 0xFF;
 650
 651 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 652         /*
 653          * EEPROM chips that implement "address overflow" are ones like
 654          * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
 655          * extra bits end up in the "chip address" bit slots.  This makes
 656          * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
 657          *
 658          * Note that we consider the length of the address field to still
 659          * be one byte because the extra address bits are hidden in the
 660          * chip address.
 661          */
 662         chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 663 #endif
 664
 665         i2c_newio(&state);
 666
 667         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
 668                       &xaddr[4 - alen]);
 669         if (rc != 0) {
 670                 printf("i2c_write: first i2c_send failed (%d)\n", rc);
 671                 return 1;
 672         }
 673
 674         rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
 675         if (rc != 0) {
 676                 printf("i2c_write: second i2c_send failed (%d)\n", rc);
 677                 return 1;
 678         }
 679
 680         rc = i2c_doio(&state);
 681         if (rc != 0) {
 682                 printf("i2c_write: i2c_doio failed (%d)\n", rc);
 683                 return 1;
 684         }
 685         return 0;
 686 }
 687
 688 #endif /* CONFIG_HARD_I2C */