arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  */
  12
  13 #include <common.h>
  14 #include <asm/fsl_ddr_sdram.h>
  15
  16 #include "ddr.h"
  17
  18 #define _DDR_ADDR CONFIG_SYS_MPC8xxx_DDR_ADDR
  19
  20 static u32 fsl_ddr_get_version(void)
  21 {
  22         ccsr_ddr_t *ddr;
  23         u32 ver_major_minor_errata;
  24
  25         ddr = (void *)_DDR_ADDR;
  26         ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
  27         ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
  28
  29         return ver_major_minor_errata;
  30 }
  31
  32 unsigned int picos_to_mclk(unsigned int picos);
  33
  34 /*
  35  * Determine Rtt value.
  36  *
  37  * This should likely be either board or controller specific.
  38  *
  39  * Rtt(nominal) - DDR2:
  40  *      0 = Rtt disabled
  41  *      1 = 75 ohm
  42  *      2 = 150 ohm
  43  *      3 = 50 ohm
  44  * Rtt(nominal) - DDR3:
  45  *      0 = Rtt disabled
  46  *      1 = 60 ohm
  47  *      2 = 120 ohm
  48  *      3 = 40 ohm
  49  *      4 = 20 ohm
  50  *      5 = 30 ohm
  51  *
  52  * FIXME: Apparently 8641 needs a value of 2
  53  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  54  *
  55  * FIXME: There was some effort down this line earlier:
  56  *
  57  *      unsigned int i;
  58  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  59  *              if (popts->dimmslot[i].num_valid_cs
  60  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  61  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  62  *                      rtt = 2;
  63  *                      break;
  64  *              }
  65  *      }
  66  */
  67 static inline int fsl_ddr_get_rtt(void)
  68 {
  69         int rtt;
  70
  71 #if defined(CONFIG_FSL_DDR1)
  72         rtt = 0;
  73 #elif defined(CONFIG_FSL_DDR2)
  74         rtt = 3;
  75 #else
  76         rtt = 0;
  77 #endif
  78
  79         return rtt;
  80 }
  81
  82 /*
  83  * compute the CAS write latency according to DDR3 spec
  84  * CWL = 5 if tCK >= 2.5ns
  85  *       6 if 2.5ns > tCK >= 1.875ns
  86  *       7 if 1.875ns > tCK >= 1.5ns
  87  *       8 if 1.5ns > tCK >= 1.25ns
  88  *       9 if 1.25ns > tCK >= 1.07ns
  89  *       10 if 1.07ns > tCK >= 0.935ns
  90  *       11 if 0.935ns > tCK >= 0.833ns
  91  *       12 if 0.833ns > tCK >= 0.75ns
  92  */
  93 static inline unsigned int compute_cas_write_latency(void)
  94 {
  95         unsigned int cwl;
  96         const unsigned int mclk_ps = get_memory_clk_period_ps();
  97
  98         if (mclk_ps >= 2500)
  99                 cwl = 5;
 100         else if (mclk_ps >= 1875)
 101                 cwl = 6;
 102         else if (mclk_ps >= 1500)
 103                 cwl = 7;
 104         else if (mclk_ps >= 1250)
 105                 cwl = 8;
 106         else if (mclk_ps >= 1070)
 107                 cwl = 9;
 108         else if (mclk_ps >= 935)
 109                 cwl = 10;
 110         else if (mclk_ps >= 833)
 111                 cwl = 11;
 112         else if (mclk_ps >= 750)
 113                 cwl = 12;
 114         else {
 115                 cwl = 12;
 116                 printf("Warning: CWL is out of range\n");
 117         }
 118         return cwl;
 119 }
 120
 121 /* Chip Select Configuration (CSn_CONFIG) */
 122 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 123                                const memctl_options_t *popts,
 124                                const dimm_params_t *dimm_params)
 125 {
 126         unsigned int cs_n_en = 0; /* Chip Select enable */
 127         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 128         unsigned int intlv_ctl = 0; /* Interleaving control */
 129         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 130         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 131         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 132         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 133         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 134         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 135         int go_config = 0;
 136
 137         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 138         switch (i) {
 139         case 0:
 140                 if (dimm_params[dimm_number].n_ranks > 0) {
 141                         go_config = 1;
 142                         /* These fields only available in CS0_CONFIG */
 143                         if (!popts->memctl_interleaving)
 144                                 break;
 145                         switch (popts->memctl_interleaving_mode) {
 146                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 147                         case FSL_DDR_PAGE_INTERLEAVING:
 148                         case FSL_DDR_BANK_INTERLEAVING:
 149                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 150                                 intlv_en = popts->memctl_interleaving;
 151                                 intlv_ctl = popts->memctl_interleaving_mode;
 152                                 break;
 153                         default:
 154                                 break;
 155                         }
 156                 }
 157                 break;
 158         case 1:
 159                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 160                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 161                         go_config = 1;
 162                 break;
 163         case 2:
 164                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 165                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 166                         go_config = 1;
 167                 break;
 168         case 3:
 169                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 170                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 171                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 172                         go_config = 1;
 173                 break;
 174         default:
 175                 break;
 176         }
 177         if (go_config) {
 178                 unsigned int n_banks_per_sdram_device;
 179                 cs_n_en = 1;
 180                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 181                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 182                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 183                 n_banks_per_sdram_device
 184                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 185                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 186                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 187                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 188         }
 189         ddr->cs[i].config = (0
 190                 | ((cs_n_en & 0x1) << 31)
 191                 | ((intlv_en & 0x3) << 29)
 192                 | ((intlv_ctl & 0xf) << 24)
 193                 | ((ap_n_en & 0x1) << 23)
 194
 195                 /* XXX: some implementation only have 1 bit starting at left */
 196                 | ((odt_rd_cfg & 0x7) << 20)
 197
 198                 /* XXX: Some implementation only have 1 bit starting at left */
 199                 | ((odt_wr_cfg & 0x7) << 16)
 200
 201                 | ((ba_bits_cs_n & 0x3) << 14)
 202                 | ((row_bits_cs_n & 0x7) << 8)
 203                 | ((col_bits_cs_n & 0x7) << 0)
 204                 );
 205         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 206 }
 207
 208 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 209 /* FIXME: 8572 */
 210 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 211 {
 212         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 213
 214         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 215         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 216 }
 217
 218 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 219
 220 #if !defined(CONFIG_FSL_DDR1)
 221 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 222 {
 223 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 224         if (dimm_params[0].n_ranks == 4)
 225                 return 1;
 226 #endif
 227
 228 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 229         if ((dimm_params[0].n_ranks == 2) &&
 230                 (dimm_params[1].n_ranks == 2))
 231                 return 1;
 232
 233 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 234         if (dimm_params[0].n_ranks == 4)
 235                 return 1;
 236 #endif
 237 #endif
 238         return 0;
 239 }
 240
 241 /*
 242  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 243  *
 244  * Avoid writing for DDR I.  The new PQ38 DDR controller
 245  * dreams up non-zero default values to be backwards compatible.
 246  */
 247 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 248                                 const memctl_options_t *popts,
 249                                 const dimm_params_t *dimm_params)
 250 {
 251         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 252         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 253         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 254         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 255         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 256
 257         /* Active powerdown exit timing (tXARD and tXARDS). */
 258         unsigned char act_pd_exit_mclk;
 259         /* Precharge powerdown exit timing (tXP). */
 260         unsigned char pre_pd_exit_mclk;
 261         /* ODT powerdown exit timing (tAXPD). */
 262         unsigned char taxpd_mclk;
 263         /* Mode register set cycle time (tMRD). */
 264         unsigned char tmrd_mclk;
 265
 266 #ifdef CONFIG_FSL_DDR3
 267         /*
 268          * (tXARD and tXARDS). Empirical?
 269          * The DDR3 spec has not tXARD,
 270          * we use the tXP instead of it.
 271          * tXP=max(3nCK, 7.5ns) for DDR3.
 272          * spec has not the tAXPD, we use
 273          * tAXPD=1, need design to confirm.
 274          */
 275         int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
 276         unsigned int data_rate = get_ddr_freq(0);
 277         tmrd_mclk = 4;
 278         /* set the turnaround time */
 279
 280         /*
 281          * for single quad-rank DIMM and two dual-rank DIMMs
 282          * to avoid ODT overlap
 283          */
 284         if (avoid_odt_overlap(dimm_params)) {
 285                 twwt_mclk = 2;
 286                 trrt_mclk = 1;
 287         }
 288         /* for faster clock, need more time for data setup */
 289         trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 290
 291         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 292                 twrt_mclk = 1;
 293
 294         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 295                 act_pd_exit_mclk = 1;
 296                 pre_pd_exit_mclk = 1;
 297                 taxpd_mclk = 1;
 298         } else {
 299                 /* act_pd_exit_mclk = tXARD, see above */
 300                 act_pd_exit_mclk = picos_to_mclk(tXP);
 301                 /* Mode register MR0[A12] is '1' - fast exit */
 302                 pre_pd_exit_mclk = act_pd_exit_mclk;
 303                 taxpd_mclk = 1;
 304         }
 305 #else /* CONFIG_FSL_DDR2 */
 306         /*
 307          * (tXARD and tXARDS). Empirical?
 308          * tXARD = 2 for DDR2
 309          * tXP=2
 310          * tAXPD=8
 311          */
 312         act_pd_exit_mclk = 2;
 313         pre_pd_exit_mclk = 2;
 314         taxpd_mclk = 8;
 315         tmrd_mclk = 2;
 316 #endif
 317
 318         if (popts->trwt_override)
 319                 trwt_mclk = popts->trwt;
 320
 321         ddr->timing_cfg_0 = (0
 322                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 323                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 324                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 325                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 326                 | ((act_pd_exit_mclk & 0x7) << 20)  /* ACT_PD_EXIT */
 327                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 328                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 329                 | ((tmrd_mclk & 0xf) << 0)      /* MRS_CYC */
 330                 );
 331         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 332 }
 333 #endif  /* defined(CONFIG_FSL_DDR2) */
 334
 335 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 336 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 337                                const memctl_options_t *popts,
 338                                const common_timing_params_t *common_dimm,
 339                                unsigned int cas_latency)
 340 {
 341         /* Extended precharge to activate interval (tRP) */
 342         unsigned int ext_pretoact = 0;
 343         /* Extended Activate to precharge interval (tRAS) */
 344         unsigned int ext_acttopre = 0;
 345         /* Extended activate to read/write interval (tRCD) */
 346         unsigned int ext_acttorw = 0;
 347         /* Extended refresh recovery time (tRFC) */
 348         unsigned int ext_refrec;
 349         /* Extended MCAS latency from READ cmd */
 350         unsigned int ext_caslat = 0;
 351         /* Extended last data to precharge interval (tWR) */
 352         unsigned int ext_wrrec = 0;
 353         /* Control Adjust */
 354         unsigned int cntl_adj = 0;
 355
 356         ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
 357         ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
 358         ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
 359         ext_caslat = (2 * cas_latency - 1) >> 4;
 360         ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
 361         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 362         ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
 363                 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 364
 365         ddr->timing_cfg_3 = (0
 366                 | ((ext_pretoact & 0x1) << 28)
 367                 | ((ext_acttopre & 0x3) << 24)
 368                 | ((ext_acttorw & 0x1) << 22)
 369                 | ((ext_refrec & 0x1F) << 16)
 370                 | ((ext_caslat & 0x3) << 12)
 371                 | ((ext_wrrec & 0x1) << 8)
 372                 | ((cntl_adj & 0x7) << 0)
 373                 );
 374         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 375 }
 376
 377 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 378 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 379                                const memctl_options_t *popts,
 380                                const common_timing_params_t *common_dimm,
 381                                unsigned int cas_latency)
 382 {
 383         /* Precharge-to-activate interval (tRP) */
 384         unsigned char pretoact_mclk;
 385         /* Activate to precharge interval (tRAS) */
 386         unsigned char acttopre_mclk;
 387         /*  Activate to read/write interval (tRCD) */
 388         unsigned char acttorw_mclk;
 389         /* CASLAT */
 390         unsigned char caslat_ctrl;
 391         /*  Refresh recovery time (tRFC) ; trfc_low */
 392         unsigned char refrec_ctrl;
 393         /* Last data to precharge minimum interval (tWR) */
 394         unsigned char wrrec_mclk;
 395         /* Activate-to-activate interval (tRRD) */
 396         unsigned char acttoact_mclk;
 397         /* Last write data pair to read command issue interval (tWTR) */
 398         unsigned char wrtord_mclk;
 399         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 400         static const u8 wrrec_table[] = {
 401                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 402
 403         pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
 404         acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
 405         acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
 406
 407         /*
 408          * Translate CAS Latency to a DDR controller field value:
 409          *
 410          *      CAS Lat DDR I   DDR II  Ctrl
 411          *      Clocks  SPD Bit SPD Bit Value
 412          *      ------- ------- ------- -----
 413          *      1.0     0               0001
 414          *      1.5     1               0010
 415          *      2.0     2       2       0011
 416          *      2.5     3               0100
 417          *      3.0     4       3       0101
 418          *      3.5     5               0110
 419          *      4.0             4       0111
 420          *      4.5                     1000
 421          *      5.0             5       1001
 422          */
 423 #if defined(CONFIG_FSL_DDR1)
 424         caslat_ctrl = (cas_latency + 1) & 0x07;
 425 #elif defined(CONFIG_FSL_DDR2)
 426         caslat_ctrl = 2 * cas_latency - 1;
 427 #else
 428         /*
 429          * if the CAS latency more than 8 cycle,
 430          * we need set extend bit for it at
 431          * TIMING_CFG_3[EXT_CASLAT]
 432          */
 433         caslat_ctrl = 2 * cas_latency - 1;
 434 #endif
 435
 436         refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
 437         wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
 438
 439         if (wrrec_mclk > 16)
 440                 printf("Error: WRREC doesn't support more than 16 clocks\n");
 441         else
 442                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 443         if (popts->otf_burst_chop_en)
 444                 wrrec_mclk += 2;
 445
 446         acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
 447         /*
 448          * JEDEC has min requirement for tRRD
 449          */
 450 #if defined(CONFIG_FSL_DDR3)
 451         if (acttoact_mclk < 4)
 452                 acttoact_mclk = 4;
 453 #endif
 454         wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
 455         /*
 456          * JEDEC has some min requirements for tWTR
 457          */
 458 #if defined(CONFIG_FSL_DDR2)
 459         if (wrtord_mclk < 2)
 460                 wrtord_mclk = 2;
 461 #elif defined(CONFIG_FSL_DDR3)
 462         if (wrtord_mclk < 4)
 463                 wrtord_mclk = 4;
 464 #endif
 465         if (popts->otf_burst_chop_en)
 466                 wrtord_mclk += 2;
 467
 468         ddr->timing_cfg_1 = (0
 469                 | ((pretoact_mclk & 0x0F) << 28)
 470                 | ((acttopre_mclk & 0x0F) << 24)
 471                 | ((acttorw_mclk & 0xF) << 20)
 472                 | ((caslat_ctrl & 0xF) << 16)
 473                 | ((refrec_ctrl & 0xF) << 12)
 474                 | ((wrrec_mclk & 0x0F) << 8)
 475                 | ((acttoact_mclk & 0x0F) << 4)
 476                 | ((wrtord_mclk & 0x0F) << 0)
 477                 );
 478         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 479 }
 480
 481 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 482 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 483                                const memctl_options_t *popts,
 484                                const common_timing_params_t *common_dimm,
 485                                unsigned int cas_latency,
 486                                unsigned int additive_latency)
 487 {
 488         /* Additive latency */
 489         unsigned char add_lat_mclk;
 490         /* CAS-to-preamble override */
 491         unsigned short cpo;
 492         /* Write latency */
 493         unsigned char wr_lat;
 494         /*  Read to precharge (tRTP) */
 495         unsigned char rd_to_pre;
 496         /* Write command to write data strobe timing adjustment */
 497         unsigned char wr_data_delay;
 498         /* Minimum CKE pulse width (tCKE) */
 499         unsigned char cke_pls;
 500         /* Window for four activates (tFAW) */
 501         unsigned short four_act;
 502
 503         /* FIXME add check that this must be less than acttorw_mclk */
 504         add_lat_mclk = additive_latency;
 505         cpo = popts->cpo_override;
 506
 507 #if defined(CONFIG_FSL_DDR1)
 508         /*
 509          * This is a lie.  It should really be 1, but if it is
 510          * set to 1, bits overlap into the old controller's
 511          * otherwise unused ACSM field.  If we leave it 0, then
 512          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 513          */
 514         wr_lat = 0;
 515 #elif defined(CONFIG_FSL_DDR2)
 516         wr_lat = cas_latency - 1;
 517 #else
 518         wr_lat = compute_cas_write_latency();
 519 #endif
 520
 521         rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
 522         /*
 523          * JEDEC has some min requirements for tRTP
 524          */
 525 #if defined(CONFIG_FSL_DDR2)
 526         if (rd_to_pre  < 2)
 527                 rd_to_pre  = 2;
 528 #elif defined(CONFIG_FSL_DDR3)
 529         if (rd_to_pre < 4)
 530                 rd_to_pre = 4;
 531 #endif
 532         if (additive_latency)
 533                 rd_to_pre += additive_latency;
 534         if (popts->otf_burst_chop_en)
 535                 rd_to_pre += 2; /* according to UM */
 536
 537         wr_data_delay = popts->write_data_delay;
 538         cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
 539         four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
 540
 541         ddr->timing_cfg_2 = (0
 542                 | ((add_lat_mclk & 0xf) << 28)
 543                 | ((cpo & 0x1f) << 23)
 544                 | ((wr_lat & 0xf) << 19)
 545                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 546                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 547                 | ((cke_pls & 0x7) << 6)
 548                 | ((four_act & 0x3f) << 0)
 549                 );
 550         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 551 }
 552
 553 /* DDR SDRAM Register Control Word */
 554 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 555                                const memctl_options_t *popts,
 556                                const common_timing_params_t *common_dimm)
 557 {
 558         if (common_dimm->all_dimms_registered &&
 559             !common_dimm->all_dimms_unbuffered) {
 560                 if (popts->rcw_override) {
 561                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 562                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 563                 } else {
 564                         ddr->ddr_sdram_rcw_1 =
 565                                 common_dimm->rcw[0] << 28 | \
 566                                 common_dimm->rcw[1] << 24 | \
 567                                 common_dimm->rcw[2] << 20 | \
 568                                 common_dimm->rcw[3] << 16 | \
 569                                 common_dimm->rcw[4] << 12 | \
 570                                 common_dimm->rcw[5] << 8 | \
 571                                 common_dimm->rcw[6] << 4 | \
 572                                 common_dimm->rcw[7];
 573                         ddr->ddr_sdram_rcw_2 =
 574                                 common_dimm->rcw[8] << 28 | \
 575                                 common_dimm->rcw[9] << 24 | \
 576                                 common_dimm->rcw[10] << 20 | \
 577                                 common_dimm->rcw[11] << 16 | \
 578                                 common_dimm->rcw[12] << 12 | \
 579                                 common_dimm->rcw[13] << 8 | \
 580                                 common_dimm->rcw[14] << 4 | \
 581                                 common_dimm->rcw[15];
 582                 }
 583                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 584                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 585         }
 586 }
 587
 588 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 589 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 590                                const memctl_options_t *popts,
 591                                const common_timing_params_t *common_dimm)
 592 {
 593         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 594         unsigned int sren;              /* Self refresh enable (during sleep) */
 595         unsigned int ecc_en;            /* ECC enable. */
 596         unsigned int rd_en;             /* Registered DIMM enable */
 597         unsigned int sdram_type;        /* Type of SDRAM */
 598         unsigned int dyn_pwr;           /* Dynamic power management mode */
 599         unsigned int dbw;               /* DRAM dta bus width */
 600         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 601         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 602         unsigned int threet_en;         /* Enable 3T timing */
 603         unsigned int twot_en;           /* Enable 2T timing */
 604         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 605         unsigned int x32_en = 0;        /* x32 enable */
 606         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 607         unsigned int hse;               /* Global half strength override */
 608         unsigned int mem_halt = 0;      /* memory controller halt */
 609         unsigned int bi = 0;            /* Bypass initialization */
 610
 611         mem_en = 1;
 612         sren = popts->self_refresh_in_sleep;
 613         if (common_dimm->all_dimms_ecc_capable) {
 614                 /* Allow setting of ECC only if all DIMMs are ECC. */
 615                 ecc_en = popts->ecc_mode;
 616         } else {
 617                 ecc_en = 0;
 618         }
 619
 620         if (common_dimm->all_dimms_registered &&
 621             !common_dimm->all_dimms_unbuffered) {
 622                 rd_en = 1;
 623                 twot_en = 0;
 624         } else {
 625                 rd_en = 0;
 626                 twot_en = popts->twot_en;
 627         }
 628
 629         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 630
 631         dyn_pwr = popts->dynamic_power;
 632         dbw = popts->data_bus_width;
 633         /* 8-beat burst enable DDR-III case
 634          * we must clear it when use the on-the-fly mode,
 635          * must set it when use the 32-bits bus mode.
 636          */
 637         if (sdram_type == SDRAM_TYPE_DDR3) {
 638                 if (popts->burst_length == DDR_BL8)
 639                         eight_be = 1;
 640                 if (popts->burst_length == DDR_OTF)
 641                         eight_be = 0;
 642                 if (dbw == 0x1)
 643                         eight_be = 1;
 644         }
 645
 646         threet_en = popts->threet_en;
 647         ba_intlv_ctl = popts->ba_intlv_ctl;
 648         hse = popts->half_strength_driver_enable;
 649
 650         ddr->ddr_sdram_cfg = (0
 651                         | ((mem_en & 0x1) << 31)
 652                         | ((sren & 0x1) << 30)
 653                         | ((ecc_en & 0x1) << 29)
 654                         | ((rd_en & 0x1) << 28)
 655                         | ((sdram_type & 0x7) << 24)
 656                         | ((dyn_pwr & 0x1) << 21)
 657                         | ((dbw & 0x3) << 19)
 658                         | ((eight_be & 0x1) << 18)
 659                         | ((ncap & 0x1) << 17)
 660                         | ((threet_en & 0x1) << 16)
 661                         | ((twot_en & 0x1) << 15)
 662                         | ((ba_intlv_ctl & 0x7F) << 8)
 663                         | ((x32_en & 0x1) << 5)
 664                         | ((pchb8 & 0x1) << 4)
 665                         | ((hse & 0x1) << 3)
 666                         | ((mem_halt & 0x1) << 1)
 667                         | ((bi & 0x1) << 0)
 668                         );
 669         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 670 }
 671
 672 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 673 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 674                                const memctl_options_t *popts,
 675                                const unsigned int unq_mrs_en)
 676 {
 677         unsigned int frc_sr = 0;        /* Force self refresh */
 678         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 679         unsigned int dll_rst_dis;       /* DLL reset disable */
 680         unsigned int dqs_cfg;           /* DQS configuration */
 681         unsigned int odt_cfg = 0;       /* ODT configuration */
 682         unsigned int num_pr;            /* Number of posted refreshes */
 683         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 684         unsigned int x4_en = 0;         /* x4 DRAM enable */
 685         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 686         unsigned int ap_en;             /* Address Parity Enable */
 687         unsigned int d_init;            /* DRAM data initialization */
 688         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 689         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 690         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 691         int i;
 692
 693         dll_rst_dis = 1;        /* Make this configurable */
 694         dqs_cfg = popts->dqs_config;
 695         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 696                 if (popts->cs_local_opts[i].odt_rd_cfg
 697                         || popts->cs_local_opts[i].odt_wr_cfg) {
 698                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 699                         break;
 700                 }
 701         }
 702
 703         num_pr = 1;     /* Make this configurable */
 704
 705         /*
 706          * 8572 manual says
 707          *     {TIMING_CFG_1[PRETOACT]
 708          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 709          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 710          *      << DDR_SDRAM_INTERVAL[REFINT]
 711          */
 712 #if defined(CONFIG_FSL_DDR3)
 713         obc_cfg = popts->otf_burst_chop_en;
 714 #else
 715         obc_cfg = 0;
 716 #endif
 717
 718 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 719         slow = get_ddr_freq(0) < 1249000000;
 720 #endif
 721
 722         if (popts->registered_dimm_en) {
 723                 rcw_en = 1;
 724                 ap_en = popts->ap_en;
 725         } else {
 726                 ap_en = 0;
 727         }
 728
 729         x4_en = popts->x4_en ? 1 : 0;
 730
 731 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 732         /* Use the DDR controller to auto initialize memory. */
 733         d_init = popts->ecc_init_using_memctl;
 734         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 735         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 736 #else
 737         /* Memory will be initialized via DMA, or not at all. */
 738         d_init = 0;
 739 #endif
 740
 741 #if defined(CONFIG_FSL_DDR3)
 742         md_en = popts->mirrored_dimm;
 743 #endif
 744         qd_en = popts->quad_rank_present ? 1 : 0;
 745         ddr->ddr_sdram_cfg_2 = (0
 746                 | ((frc_sr & 0x1) << 31)
 747                 | ((sr_ie & 0x1) << 30)
 748                 | ((dll_rst_dis & 0x1) << 29)
 749                 | ((dqs_cfg & 0x3) << 26)
 750                 | ((odt_cfg & 0x3) << 21)
 751                 | ((num_pr & 0xf) << 12)
 752                 | ((slow & 1) << 11)
 753                 | (x4_en << 10)
 754                 | (qd_en << 9)
 755                 | (unq_mrs_en << 8)
 756                 | ((obc_cfg & 0x1) << 6)
 757                 | ((ap_en & 0x1) << 5)
 758                 | ((d_init & 0x1) << 4)
 759                 | ((rcw_en & 0x1) << 2)
 760                 | ((md_en & 0x1) << 0)
 761                 );
 762         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 763 }
 764
 765 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 766 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 767                                 const memctl_options_t *popts,
 768                                 const common_timing_params_t *common_dimm,
 769                                 const unsigned int unq_mrs_en)
 770 {
 771         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 772         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 773
 774 #if defined(CONFIG_FSL_DDR3)
 775         int i;
 776         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 777         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 778         unsigned int asr = 0;   /* auto self-refresh disable */
 779         unsigned int cwl = compute_cas_write_latency() - 5;
 780         unsigned int pasr = 0;  /* partial array self refresh disable */
 781
 782         if (popts->rtt_override)
 783                 rtt_wr = popts->rtt_wr_override_value;
 784         else
 785                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 786
 787         if (common_dimm->extended_op_srt)
 788                 srt = common_dimm->extended_op_srt;
 789
 790         esdmode2 = (0
 791                 | ((rtt_wr & 0x3) << 9)
 792                 | ((srt & 0x1) << 7)
 793                 | ((asr & 0x1) << 6)
 794                 | ((cwl & 0x7) << 3)
 795                 | ((pasr & 0x7) << 0));
 796 #endif
 797         ddr->ddr_sdram_mode_2 = (0
 798                                  | ((esdmode2 & 0xFFFF) << 16)
 799                                  | ((esdmode3 & 0xFFFF) << 0)
 800                                  );
 801         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 802
 803 #ifdef CONFIG_FSL_DDR3
 804         if (unq_mrs_en) {       /* unique mode registers are supported */
 805                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 806                         if (popts->rtt_override)
 807                                 rtt_wr = popts->rtt_wr_override_value;
 808                         else
 809                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 810
 811                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 812                         esdmode2 |= (rtt_wr & 0x3) << 9;
 813                         switch (i) {
 814                         case 1:
 815                                 ddr->ddr_sdram_mode_4 = (0
 816                                         | ((esdmode2 & 0xFFFF) << 16)
 817                                         | ((esdmode3 & 0xFFFF) << 0)
 818                                         );
 819                                 break;
 820                         case 2:
 821                                 ddr->ddr_sdram_mode_6 = (0
 822                                         | ((esdmode2 & 0xFFFF) << 16)
 823                                         | ((esdmode3 & 0xFFFF) << 0)
 824                                         );
 825                                 break;
 826                         case 3:
 827                                 ddr->ddr_sdram_mode_8 = (0
 828                                         | ((esdmode2 & 0xFFFF) << 16)
 829                                         | ((esdmode3 & 0xFFFF) << 0)
 830                                         );
 831                                 break;
 832                         }
 833                 }
 834                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
 835                         ddr->ddr_sdram_mode_4);
 836                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
 837                         ddr->ddr_sdram_mode_6);
 838                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
 839                         ddr->ddr_sdram_mode_8);
 840         }
 841 #endif
 842 }
 843
 844 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
 845 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 846                                const memctl_options_t *popts,
 847                                const common_timing_params_t *common_dimm)
 848 {
 849         unsigned int refint;    /* Refresh interval */
 850         unsigned int bstopre;   /* Precharge interval */
 851
 852         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
 853
 854         bstopre = popts->bstopre;
 855
 856         /* refint field used 0x3FFF in earlier controllers */
 857         ddr->ddr_sdram_interval = (0
 858                                    | ((refint & 0xFFFF) << 16)
 859                                    | ((bstopre & 0x3FFF) << 0)
 860                                    );
 861         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 862 }
 863
 864 #if defined(CONFIG_FSL_DDR3)
 865 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 866 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 867                                const memctl_options_t *popts,
 868                                const common_timing_params_t *common_dimm,
 869                                unsigned int cas_latency,
 870                                unsigned int additive_latency,
 871                                const unsigned int unq_mrs_en)
 872 {
 873         unsigned short esdmode;         /* Extended SDRAM mode */
 874         unsigned short sdmode;          /* SDRAM mode */
 875
 876         /* Mode Register - MR1 */
 877         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
 878         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
 879         unsigned int rtt;
 880         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
 881         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
 882         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
 883         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 884                                                        1=Disable (Test/Debug) */
 885
 886         /* Mode Register - MR0 */
 887         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
 888         unsigned int wr = 0;    /* Write Recovery */
 889         unsigned int dll_rst;   /* DLL Reset */
 890         unsigned int mode;      /* Normal=0 or Test=1 */
 891         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
 892         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
 893         unsigned int bt;
 894         unsigned int bl;        /* BL: Burst Length */
 895
 896         unsigned int wr_mclk;
 897         /*
 898          * DDR_SDRAM_MODE doesn't support 9,11,13,15
 899          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
 900          * for this table
 901          */
 902         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
 903
 904         const unsigned int mclk_ps = get_memory_clk_period_ps();
 905         int i;
 906
 907         if (popts->rtt_override)
 908                 rtt = popts->rtt_override_value;
 909         else
 910                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
 911
 912         if (additive_latency == (cas_latency - 1))
 913                 al = 1;
 914         if (additive_latency == (cas_latency - 2))
 915                 al = 2;
 916
 917         if (popts->quad_rank_present)
 918                 dic = 1;        /* output driver impedance 240/7 ohm */
 919
 920         /*
 921          * The esdmode value will also be used for writing
 922          * MR1 during write leveling for DDR3, although the
 923          * bits specifically related to the write leveling
 924          * scheme will be handled automatically by the DDR
 925          * controller. so we set the wrlvl_en = 0 here.
 926          */
 927         esdmode = (0
 928                 | ((qoff & 0x1) << 12)
 929                 | ((tdqs_en & 0x1) << 11)
 930                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 931                 | ((wrlvl_en & 0x1) << 7)
 932                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 933                 | ((dic & 0x2) << 4)   /* DIC field is split */
 934                 | ((al & 0x3) << 3)
 935                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 936                 | ((dic & 0x1) << 1)   /* DIC field is split */
 937                 | ((dll_en & 0x1) << 0)
 938                 );
 939
 940         /*
 941          * DLL control for precharge PD
 942          * 0=slow exit DLL off (tXPDLL)
 943          * 1=fast exit DLL on (tXP)
 944          */
 945         dll_on = 1;
 946
 947         wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps;
 948         if (wr_mclk <= 16) {
 949                 wr = wr_table[wr_mclk - 5];
 950         } else {
 951                 printf("Error: unsupported write recovery for mode register "
 952                        "wr_mclk = %d\n", wr_mclk);
 953         }
 954
 955         dll_rst = 0;    /* dll no reset */
 956         mode = 0;       /* normal mode */
 957
 958         /* look up table to get the cas latency bits */
 959         if (cas_latency >= 5 && cas_latency <= 16) {
 960                 unsigned char cas_latency_table[] = {
 961                         0x2,    /* 5 clocks */
 962                         0x4,    /* 6 clocks */
 963                         0x6,    /* 7 clocks */
 964                         0x8,    /* 8 clocks */
 965                         0xa,    /* 9 clocks */
 966                         0xc,    /* 10 clocks */
 967                         0xe,    /* 11 clocks */
 968                         0x1,    /* 12 clocks */
 969                         0x3,    /* 13 clocks */
 970                         0x5,    /* 14 clocks */
 971                         0x7,    /* 15 clocks */
 972                         0x9,    /* 16 clocks */
 973                 };
 974                 caslat = cas_latency_table[cas_latency - 5];
 975         } else {
 976                 printf("Error: unsupported cas latency for mode register\n");
 977         }
 978
 979         bt = 0; /* Nibble sequential */
 980
 981         switch (popts->burst_length) {
 982         case DDR_BL8:
 983                 bl = 0;
 984                 break;
 985         case DDR_OTF:
 986                 bl = 1;
 987                 break;
 988         case DDR_BC4:
 989                 bl = 2;
 990                 break;
 991         default:
 992                 printf("Error: invalid burst length of %u specified. "
 993                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
 994                         popts->burst_length);
 995                 bl = 1;
 996                 break;
 997         }
 998
 999         sdmode = (0
1000                   | ((dll_on & 0x1) << 12)
1001                   | ((wr & 0x7) << 9)
1002                   | ((dll_rst & 0x1) << 8)
1003                   | ((mode & 0x1) << 7)
1004                   | (((caslat >> 1) & 0x7) << 4)
1005                   | ((bt & 0x1) << 3)
1006                   | ((caslat & 1) << 2)
1007                   | ((bl & 0x3) << 0)
1008                   );
1009
1010         ddr->ddr_sdram_mode = (0
1011                                | ((esdmode & 0xFFFF) << 16)
1012                                | ((sdmode & 0xFFFF) << 0)
1013                                );
1014
1015         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1016
1017         if (unq_mrs_en) {       /* unique mode registers are supported */
1018                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1019                         if (popts->rtt_override)
1020                                 rtt = popts->rtt_override_value;
1021                         else
1022                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1023
1024                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1025                         esdmode |= (0
1026                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1027                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1028                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1029                                 );
1030                         switch (i) {
1031                         case 1:
1032                                 ddr->ddr_sdram_mode_3 = (0
1033                                        | ((esdmode & 0xFFFF) << 16)
1034                                        | ((sdmode & 0xFFFF) << 0)
1035                                        );
1036                                 break;
1037                         case 2:
1038                                 ddr->ddr_sdram_mode_5 = (0
1039                                        | ((esdmode & 0xFFFF) << 16)
1040                                        | ((sdmode & 0xFFFF) << 0)
1041                                        );
1042                                 break;
1043                         case 3:
1044                                 ddr->ddr_sdram_mode_7 = (0
1045                                        | ((esdmode & 0xFFFF) << 16)
1046                                        | ((sdmode & 0xFFFF) << 0)
1047                                        );
1048                                 break;
1049                         }
1050                 }
1051                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1052                         ddr->ddr_sdram_mode_3);
1053                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1054                         ddr->ddr_sdram_mode_5);
1055                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1056                         ddr->ddr_sdram_mode_5);
1057         }
1058 }
1059
1060 #else /* !CONFIG_FSL_DDR3 */
1061
1062 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1063 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1064                                const memctl_options_t *popts,
1065                                const common_timing_params_t *common_dimm,
1066                                unsigned int cas_latency,
1067                                unsigned int additive_latency,
1068                                const unsigned int unq_mrs_en)
1069 {
1070         unsigned short esdmode;         /* Extended SDRAM mode */
1071         unsigned short sdmode;          /* SDRAM mode */
1072
1073         /*
1074          * FIXME: This ought to be pre-calculated in a
1075          * technology-specific routine,
1076          * e.g. compute_DDR2_mode_register(), and then the
1077          * sdmode and esdmode passed in as part of common_dimm.
1078          */
1079
1080         /* Extended Mode Register */
1081         unsigned int mrs = 0;           /* Mode Register Set */
1082         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1083         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1084         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1085         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1086                                            0x7=OCD default state */
1087         unsigned int rtt;
1088         unsigned int al;                /* Posted CAS# additive latency (AL) */
1089         unsigned int ods = 0;           /* Output Drive Strength:
1090                                                 0 = Full strength (18ohm)
1091                                                 1 = Reduced strength (4ohm) */
1092         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1093                                                        1=Disable (Test/Debug) */
1094
1095         /* Mode Register (MR) */
1096         unsigned int mr;        /* Mode Register Definition */
1097         unsigned int pd;        /* Power-Down Mode */
1098         unsigned int wr;        /* Write Recovery */
1099         unsigned int dll_res;   /* DLL Reset */
1100         unsigned int mode;      /* Normal=0 or Test=1 */
1101         unsigned int caslat = 0;/* CAS# latency */
1102         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1103         unsigned int bt;
1104         unsigned int bl;        /* BL: Burst Length */
1105
1106 #if defined(CONFIG_FSL_DDR2)
1107         const unsigned int mclk_ps = get_memory_clk_period_ps();
1108 #endif
1109         dqs_en = !popts->dqs_config;
1110         rtt = fsl_ddr_get_rtt();
1111
1112         al = additive_latency;
1113
1114         esdmode = (0
1115                 | ((mrs & 0x3) << 14)
1116                 | ((outputs & 0x1) << 12)
1117                 | ((rdqs_en & 0x1) << 11)
1118                 | ((dqs_en & 0x1) << 10)
1119                 | ((ocd & 0x7) << 7)
1120                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1121                 | ((al & 0x7) << 3)
1122                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1123                 | ((ods & 0x1) << 1)
1124                 | ((dll_en & 0x1) << 0)
1125                 );
1126
1127         mr = 0;          /* FIXME: CHECKME */
1128
1129         /*
1130          * 0 = Fast Exit (Normal)
1131          * 1 = Slow Exit (Low Power)
1132          */
1133         pd = 0;
1134
1135 #if defined(CONFIG_FSL_DDR1)
1136         wr = 0;       /* Historical */
1137 #elif defined(CONFIG_FSL_DDR2)
1138         wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1;
1139 #endif
1140         dll_res = 0;
1141         mode = 0;
1142
1143 #if defined(CONFIG_FSL_DDR1)
1144         if (1 <= cas_latency && cas_latency <= 4) {
1145                 unsigned char mode_caslat_table[4] = {
1146                         0x5,    /* 1.5 clocks */
1147                         0x2,    /* 2.0 clocks */
1148                         0x6,    /* 2.5 clocks */
1149                         0x3     /* 3.0 clocks */
1150                 };
1151                 caslat = mode_caslat_table[cas_latency - 1];
1152         } else {
1153                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1154         }
1155 #elif defined(CONFIG_FSL_DDR2)
1156         caslat = cas_latency;
1157 #endif
1158         bt = 0;
1159
1160         switch (popts->burst_length) {
1161         case DDR_BL4:
1162                 bl = 2;
1163                 break;
1164         case DDR_BL8:
1165                 bl = 3;
1166                 break;
1167         default:
1168                 printf("Error: invalid burst length of %u specified. "
1169                         " Defaulting to 4 beats.\n",
1170                         popts->burst_length);
1171                 bl = 2;
1172                 break;
1173         }
1174
1175         sdmode = (0
1176                   | ((mr & 0x3) << 14)
1177                   | ((pd & 0x1) << 12)
1178                   | ((wr & 0x7) << 9)
1179                   | ((dll_res & 0x1) << 8)
1180                   | ((mode & 0x1) << 7)
1181                   | ((caslat & 0x7) << 4)
1182                   | ((bt & 0x1) << 3)
1183                   | ((bl & 0x7) << 0)
1184                   );
1185
1186         ddr->ddr_sdram_mode = (0
1187                                | ((esdmode & 0xFFFF) << 16)
1188                                | ((sdmode & 0xFFFF) << 0)
1189                                );
1190         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1191 }
1192 #endif
1193
1194 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1195 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1196 {
1197         unsigned int init_value;        /* Initialization value */
1198
1199 #ifdef CONFIG_MEM_INIT_VALUE
1200         init_value = CONFIG_MEM_INIT_VALUE;
1201 #else
1202         init_value = 0xDEADBEEF;
1203 #endif
1204         ddr->ddr_data_init = init_value;
1205 }
1206
1207 /*
1208  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1209  * The old controller on the 8540/60 doesn't have this register.
1210  * Hope it's OK to set it (to 0) anyway.
1211  */
1212 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1213                                          const memctl_options_t *popts)
1214 {
1215         unsigned int clk_adjust;        /* Clock adjust */
1216
1217         clk_adjust = popts->clk_adjust;
1218         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1219         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1220 }
1221
1222 /* DDR Initialization Address (DDR_INIT_ADDR) */
1223 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1224 {
1225         unsigned int init_addr = 0;     /* Initialization address */
1226
1227         ddr->ddr_init_addr = init_addr;
1228 }
1229
1230 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1231 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1232 {
1233         unsigned int uia = 0;   /* Use initialization address */
1234         unsigned int init_ext_addr = 0; /* Initialization address */
1235
1236         ddr->ddr_init_ext_addr = (0
1237                                   | ((uia & 0x1) << 31)
1238                                   | (init_ext_addr & 0xF)
1239                                   );
1240 }
1241
1242 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1243 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1244                                 const memctl_options_t *popts)
1245 {
1246         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1247         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1248         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1249         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1250         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1251
1252 #if defined(CONFIG_FSL_DDR3)
1253         if (popts->burst_length == DDR_BL8) {
1254                 /* We set BL/2 for fixed BL8 */
1255                 rrt = 0;        /* BL/2 clocks */
1256                 wwt = 0;        /* BL/2 clocks */
1257         } else {
1258                 /* We need to set BL/2 + 2 to BC4 and OTF */
1259                 rrt = 2;        /* BL/2 + 2 clocks */
1260                 wwt = 2;        /* BL/2 + 2 clocks */
1261         }
1262         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1263 #endif
1264         ddr->timing_cfg_4 = (0
1265                              | ((rwt & 0xf) << 28)
1266                              | ((wrt & 0xf) << 24)
1267                              | ((rrt & 0xf) << 20)
1268                              | ((wwt & 0xf) << 16)
1269                              | (dll_lock & 0x3)
1270                              );
1271         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1272 }
1273
1274 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1275 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1276 {
1277         unsigned int rodt_on = 0;       /* Read to ODT on */
1278         unsigned int rodt_off = 0;      /* Read to ODT off */
1279         unsigned int wodt_on = 0;       /* Write to ODT on */
1280         unsigned int wodt_off = 0;      /* Write to ODT off */
1281
1282 #if defined(CONFIG_FSL_DDR3)
1283         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1284         rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1285         rodt_off = 4;   /*  4 clocks */
1286         wodt_on = 1;    /*  1 clocks */
1287         wodt_off = 4;   /*  4 clocks */
1288 #endif
1289
1290         ddr->timing_cfg_5 = (0
1291                              | ((rodt_on & 0x1f) << 24)
1292                              | ((rodt_off & 0x7) << 20)
1293                              | ((wodt_on & 0x1f) << 12)
1294                              | ((wodt_off & 0x7) << 8)
1295                              );
1296         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1297 }
1298
1299 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1300 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1301 {
1302         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1303         /* Normal Operation Full Calibration Time (tZQoper) */
1304         unsigned int zqoper = 0;
1305         /* Normal Operation Short Calibration Time (tZQCS) */
1306         unsigned int zqcs = 0;
1307
1308         if (zq_en) {
1309                 zqinit = 9;     /* 512 clocks */
1310                 zqoper = 8;     /* 256 clocks */
1311                 zqcs = 6;       /* 64 clocks */
1312         }
1313
1314         ddr->ddr_zq_cntl = (0
1315                             | ((zq_en & 0x1) << 31)
1316                             | ((zqinit & 0xF) << 24)
1317                             | ((zqoper & 0xF) << 16)
1318                             | ((zqcs & 0xF) << 8)
1319                             );
1320         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1321 }
1322
1323 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1324 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1325                                 const memctl_options_t *popts)
1326 {
1327         /*
1328          * First DQS pulse rising edge after margining mode
1329          * is programmed (tWL_MRD)
1330          */
1331         unsigned int wrlvl_mrd = 0;
1332         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1333         unsigned int wrlvl_odten = 0;
1334         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1335         unsigned int wrlvl_dqsen = 0;
1336         /* WRLVL_SMPL: Write leveling sample time */
1337         unsigned int wrlvl_smpl = 0;
1338         /* WRLVL_WLR: Write leveling repeition time */
1339         unsigned int wrlvl_wlr = 0;
1340         /* WRLVL_START: Write leveling start time */
1341         unsigned int wrlvl_start = 0;
1342
1343         /* suggest enable write leveling for DDR3 due to fly-by topology */
1344         if (wrlvl_en) {
1345                 /* tWL_MRD min = 40 nCK, we set it 64 */
1346                 wrlvl_mrd = 0x6;
1347                 /* tWL_ODTEN 128 */
1348                 wrlvl_odten = 0x7;
1349                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1350                 wrlvl_dqsen = 0x5;
1351                 /*
1352                  * Write leveling sample time at least need 6 clocks
1353                  * higher than tWLO to allow enough time for progagation
1354                  * delay and sampling the prime data bits.
1355                  */
1356                 wrlvl_smpl = 0xf;
1357                 /*
1358                  * Write leveling repetition time
1359                  * at least tWLO + 6 clocks clocks
1360                  * we set it 64
1361                  */
1362                 wrlvl_wlr = 0x6;
1363                 /*
1364                  * Write leveling start time
1365                  * The value use for the DQS_ADJUST for the first sample
1366                  * when write leveling is enabled. It probably needs to be
1367                  * overriden per platform.
1368                  */
1369                 wrlvl_start = 0x8;
1370                 /*
1371                  * Override the write leveling sample and start time
1372                  * according to specific board
1373                  */
1374                 if (popts->wrlvl_override) {
1375                         wrlvl_smpl = popts->wrlvl_sample;
1376                         wrlvl_start = popts->wrlvl_start;
1377                 }
1378         }
1379
1380         ddr->ddr_wrlvl_cntl = (0
1381                                | ((wrlvl_en & 0x1) << 31)
1382                                | ((wrlvl_mrd & 0x7) << 24)
1383                                | ((wrlvl_odten & 0x7) << 20)
1384                                | ((wrlvl_dqsen & 0x7) << 16)
1385                                | ((wrlvl_smpl & 0xf) << 12)
1386                                | ((wrlvl_wlr & 0x7) << 8)
1387                                | ((wrlvl_start & 0x1F) << 0)
1388                                );
1389         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1390         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
1391         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
1392         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
1393         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
1394
1395 }
1396
1397 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1398 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1399 {
1400         /* Self Refresh Idle Threshold */
1401         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1402 }
1403
1404 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1405 {
1406         if (popts->addr_hash) {
1407                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
1408                 puts("Address hashing enabled.\n");
1409         }
1410 }
1411
1412 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1413 {
1414         ddr->ddr_cdr1 = popts->ddr_cdr1;
1415         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1416 }
1417
1418 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1419 {
1420         ddr->ddr_cdr2 = popts->ddr_cdr2;
1421         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
1422 }
1423
1424 unsigned int
1425 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1426 {
1427         unsigned int res = 0;
1428
1429         /*
1430          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1431          * not set at the same time.
1432          */
1433         if (ddr->ddr_sdram_cfg & 0x10000000
1434             && ddr->ddr_sdram_cfg & 0x00008000) {
1435                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1436                                 " should not be set at the same time.\n");
1437                 res++;
1438         }
1439
1440         return res;
1441 }
1442
1443 unsigned int
1444 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1445                                fsl_ddr_cfg_regs_t *ddr,
1446                                const common_timing_params_t *common_dimm,
1447                                const dimm_params_t *dimm_params,
1448                                unsigned int dbw_cap_adj,
1449                                unsigned int size_only)
1450 {
1451         unsigned int i;
1452         unsigned int cas_latency;
1453         unsigned int additive_latency;
1454         unsigned int sr_it;
1455         unsigned int zq_en;
1456         unsigned int wrlvl_en;
1457         unsigned int ip_rev = 0;
1458         unsigned int unq_mrs_en = 0;
1459         int cs_en = 1;
1460
1461         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1462
1463         if (common_dimm == NULL) {
1464                 printf("Error: subset DIMM params struct null pointer\n");
1465                 return 1;
1466         }
1467
1468         /*
1469          * Process overrides first.
1470          *
1471          * FIXME: somehow add dereated caslat to this
1472          */
1473         cas_latency = (popts->cas_latency_override)
1474                 ? popts->cas_latency_override_value
1475                 : common_dimm->lowest_common_SPD_caslat;
1476
1477         additive_latency = (popts->additive_latency_override)
1478                 ? popts->additive_latency_override_value
1479                 : common_dimm->additive_latency;
1480
1481         sr_it = (popts->auto_self_refresh_en)
1482                 ? popts->sr_it
1483                 : 0;
1484         /* ZQ calibration */
1485         zq_en = (popts->zq_en) ? 1 : 0;
1486         /* write leveling */
1487         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1488
1489         /* Chip Select Memory Bounds (CSn_BNDS) */
1490         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1491                 unsigned long long ea, sa;
1492                 unsigned int cs_per_dimm
1493                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1494                 unsigned int dimm_number
1495                         = i / cs_per_dimm;
1496                 unsigned long long rank_density
1497                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
1498
1499                 if (dimm_params[dimm_number].n_ranks == 0) {
1500                         debug("Skipping setup of CS%u "
1501                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1502                         continue;
1503                 }
1504                 if (popts->memctl_interleaving) {
1505                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1506                         case FSL_DDR_CS0_CS1_CS2_CS3:
1507                                 break;
1508                         case FSL_DDR_CS0_CS1:
1509                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1510                                 if (i > 1)
1511                                         cs_en = 0;
1512                                 break;
1513                         case FSL_DDR_CS2_CS3:
1514                         default:
1515                                 if (i > 0)
1516                                         cs_en = 0;
1517                                 break;
1518                         }
1519                         sa = common_dimm->base_address;
1520                         ea = sa + common_dimm->total_mem - 1;
1521                 } else if (!popts->memctl_interleaving) {
1522                         /*
1523                          * If memory interleaving between controllers is NOT
1524                          * enabled, the starting address for each memory
1525                          * controller is distinct.  However, because rank
1526                          * interleaving is enabled, the starting and ending
1527                          * addresses of the total memory on that memory
1528                          * controller needs to be programmed into its
1529                          * respective CS0_BNDS.
1530                          */
1531                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1532                         case FSL_DDR_CS0_CS1_CS2_CS3:
1533                                 sa = common_dimm->base_address;
1534                                 ea = sa + common_dimm->total_mem - 1;
1535                                 break;
1536                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1537                                 if ((i >= 2) && (dimm_number == 0)) {
1538                                         sa = dimm_params[dimm_number].base_address +
1539                                               2 * rank_density;
1540                                         ea = sa + 2 * rank_density - 1;
1541                                 } else {
1542                                         sa = dimm_params[dimm_number].base_address;
1543                                         ea = sa + 2 * rank_density - 1;
1544                                 }
1545                                 break;
1546                         case FSL_DDR_CS0_CS1:
1547                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1548                                         sa = dimm_params[dimm_number].base_address;
1549                                         ea = sa + rank_density - 1;
1550                                         if (i != 1)
1551                                                 sa += (i % cs_per_dimm) * rank_density;
1552                                         ea += (i % cs_per_dimm) * rank_density;
1553                                 } else {
1554                                         sa = 0;
1555                                         ea = 0;
1556                                 }
1557                                 if (i == 0)
1558                                         ea += rank_density;
1559                                 break;
1560                         case FSL_DDR_CS2_CS3:
1561                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1562                                         sa = dimm_params[dimm_number].base_address;
1563                                         ea = sa + rank_density - 1;
1564                                         if (i != 3)
1565                                                 sa += (i % cs_per_dimm) * rank_density;
1566                                         ea += (i % cs_per_dimm) * rank_density;
1567                                 } else {
1568                                         sa = 0;
1569                                         ea = 0;
1570                                 }
1571                                 if (i == 2)
1572                                         ea += (rank_density >> dbw_cap_adj);
1573                                 break;
1574                         default:  /* No bank(chip-select) interleaving */
1575                                 sa = dimm_params[dimm_number].base_address;
1576                                 ea = sa + rank_density - 1;
1577                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1578                                         sa += (i % cs_per_dimm) * rank_density;
1579                                         ea += (i % cs_per_dimm) * rank_density;
1580                                 } else {
1581                                         sa = 0;
1582                                         ea = 0;
1583                                 }
1584                                 break;
1585                         }
1586                 }
1587
1588                 sa >>= 24;
1589                 ea >>= 24;
1590
1591                 if (cs_en) {
1592                         ddr->cs[i].bnds = (0
1593                                 | ((sa & 0xFFF) << 16)/* starting address MSB */
1594                                 | ((ea & 0xFFF) << 0)   /* ending address MSB */
1595                                 );
1596                 } else {
1597                         /* setting bnds to 0xffffffff for inactive CS */
1598                         ddr->cs[i].bnds = 0xffffffff;
1599                 }
1600
1601                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1602                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1603                 set_csn_config_2(i, ddr);
1604         }
1605
1606         /*
1607          * In the case we only need to compute the ddr sdram size, we only need
1608          * to set csn registers, so return from here.
1609          */
1610         if (size_only)
1611                 return 0;
1612
1613         set_ddr_eor(ddr, popts);
1614
1615 #if !defined(CONFIG_FSL_DDR1)
1616         set_timing_cfg_0(ddr, popts, dimm_params);
1617 #endif
1618
1619         set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
1620         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1621         set_timing_cfg_2(ddr, popts, common_dimm,
1622                                 cas_latency, additive_latency);
1623
1624         set_ddr_cdr1(ddr, popts);
1625         set_ddr_cdr2(ddr, popts);
1626         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1627         ip_rev = fsl_ddr_get_version();
1628         if (ip_rev > 0x40400)
1629                 unq_mrs_en = 1;
1630
1631         set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1632         set_ddr_sdram_mode(ddr, popts, common_dimm,
1633                                 cas_latency, additive_latency, unq_mrs_en);
1634         set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
1635         set_ddr_sdram_interval(ddr, popts, common_dimm);
1636         set_ddr_data_init(ddr);
1637         set_ddr_sdram_clk_cntl(ddr, popts);
1638         set_ddr_init_addr(ddr);
1639         set_ddr_init_ext_addr(ddr);
1640         set_timing_cfg_4(ddr, popts);
1641         set_timing_cfg_5(ddr, cas_latency);
1642
1643         set_ddr_zq_cntl(ddr, zq_en);
1644         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1645
1646         set_ddr_sr_cntr(ddr, sr_it);
1647
1648         set_ddr_sdram_rcw(ddr, popts, common_dimm);
1649
1650 #ifdef CONFIG_SYS_FSL_DDR_EMU
1651         /* disble DDR training for emulator */
1652         ddr->debug[2] = 0x00000400;
1653         ddr->debug[4] = 0xff800000;
1654 #endif
1655         return check_fsl_memctl_config_regs(ddr);
1656 }