arch/powerpc/cpu/mpc8xxx/ddr/main.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  11  * Based on code from spd_sdram.c
  12  * Author: James Yang [at freescale.com]
  13  */
  14
  15 #include <common.h>
  16 #include <i2c.h>
  17 #include <asm/fsl_ddr_sdram.h>
  18
  19 #include "ddr.h"
  20
  21 extern void fsl_ddr_set_lawbar(
  22                 const common_timing_params_t *memctl_common_params,
  23                 unsigned int memctl_interleaved,
  24                 unsigned int ctrl_num);
  25
  26 /* processor specific function */
  27 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  28                                    unsigned int ctrl_num);
  29
  30 #if defined(SPD_EEPROM_ADDRESS) || \
  31     defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
  32     defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
  33 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  34 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  35         [0][0] = SPD_EEPROM_ADDRESS,
  36 };
  37 #endif
  38 #if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  39 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  40         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  41         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  42 };
  43 #endif
  44 #if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  45 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  46         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  47         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  48         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  49         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  50 };
  51 #endif
  52
  53 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  54 {
  55         int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
  56                                 sizeof(generic_spd_eeprom_t));
  57
  58         if (ret) {
  59                 printf("DDR: failed to read SPD from address %u\n", i2c_address);
  60                 memset(spd, 0, sizeof(generic_spd_eeprom_t));
  61         }
  62 }
  63
  64 __attribute__((weak, alias("__get_spd")))
  65 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
  66
  67 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  68                       unsigned int ctrl_num)
  69 {
  70         unsigned int i;
  71         unsigned int i2c_address = 0;
  72
  73         if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
  74                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  75                 return;
  76         }
  77
  78         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  79                 i2c_address = spd_i2c_addr[ctrl_num][i];
  80                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
  81         }
  82 }
  83 #else
  84 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  85                       unsigned int ctrl_num)
  86 {
  87 }
  88 #endif /* SPD_EEPROM_ADDRESSx */
  89
  90 /*
  91  * ASSUMPTIONS:
  92  *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
  93  *    - Same memory data bus width on all controllers
  94  *
  95  * NOTES:
  96  *
  97  * The memory controller and associated documentation use confusing
  98  * terminology when referring to the orgranization of DRAM.
  99  *
 100  * Here is a terminology translation table:
 101  *
 102  * memory controller/documention  |industry   |this code  |signals
 103  * -------------------------------|-----------|-----------|-----------------
 104  * physical bank/bank             |rank       |rank       |chip select (CS)
 105  * logical bank/sub-bank          |bank       |bank       |bank address (BA)
 106  * page/row                       |row        |page       |row address
 107  * ???                            |column     |column     |column address
 108  *
 109  * The naming confusion is further exacerbated by the descriptions of the
 110  * memory controller interleaving feature, where accesses are interleaved
 111  * _BETWEEN_ two seperate memory controllers.  This is configured only in
 112  * CS0_CONFIG[INTLV_CTL] of each memory controller.
 113  *
 114  * memory controller documentation | number of chip selects
 115  *                                 | per memory controller supported
 116  * --------------------------------|-----------------------------------------
 117  * cache line interleaving         | 1 (CS0 only)
 118  * page interleaving               | 1 (CS0 only)
 119  * bank interleaving               | 1 (CS0 only)
 120  * superbank interleraving         | depends on bank (chip select)
 121  *                                 |   interleraving [rank interleaving]
 122  *                                 |   mode used on every memory controller
 123  *
 124  * Even further confusing is the existence of the interleaving feature
 125  * _WITHIN_ each memory controller.  The feature is referred to in
 126  * documentation as chip select interleaving or bank interleaving,
 127  * although it is configured in the DDR_SDRAM_CFG field.
 128  *
 129  * Name of field                | documentation name    | this code
 130  * -----------------------------|-----------------------|------------------
 131  * DDR_SDRAM_CFG[BA_INTLV_CTL]  | Bank (chip select)    | rank interleaving
 132  *                              |  interleaving
 133  */
 134
 135 #ifdef DEBUG
 136 const char *step_string_tbl[] = {
 137         "STEP_GET_SPD",
 138         "STEP_COMPUTE_DIMM_PARMS",
 139         "STEP_COMPUTE_COMMON_PARMS",
 140         "STEP_GATHER_OPTS",
 141         "STEP_ASSIGN_ADDRESSES",
 142         "STEP_COMPUTE_REGS",
 143         "STEP_PROGRAM_REGS",
 144         "STEP_ALL"
 145 };
 146
 147 const char * step_to_string(unsigned int step) {
 148
 149         unsigned int s = __ilog2(step);
 150
 151         if ((1 << s) != step)
 152                 return step_string_tbl[7];
 153
 154         return step_string_tbl[s];
 155 }
 156 #endif
 157
 158 int step_assign_addresses(fsl_ddr_info_t *pinfo,
 159                           unsigned int dbw_cap_adj[],
 160                           unsigned int *all_memctl_interleaving,
 161                           unsigned int *all_ctlr_rank_interleaving)
 162 {
 163         int i, j;
 164
 165         /*
 166          * If a reduced data width is requested, but the SPD
 167          * specifies a physically wider device, adjust the
 168          * computed dimm capacities accordingly before
 169          * assigning addresses.
 170          */
 171         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 172                 unsigned int found = 0;
 173
 174                 switch (pinfo->memctl_opts[i].data_bus_width) {
 175                 case 2:
 176                         /* 16-bit */
 177                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 178                                 unsigned int dw;
 179                                 if (!pinfo->dimm_params[i][j].n_ranks)
 180                                         continue;
 181                                 dw = pinfo->dimm_params[i][j].primary_sdram_width;
 182                                 if ((dw == 72 || dw == 64)) {
 183                                         dbw_cap_adj[i] = 2;
 184                                         break;
 185                                 } else if ((dw == 40 || dw == 32)) {
 186                                         dbw_cap_adj[i] = 1;
 187                                         break;
 188                                 }
 189                         }
 190                         break;
 191
 192                 case 1:
 193                         /* 32-bit */
 194                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 195                                 unsigned int dw;
 196                                 dw = pinfo->dimm_params[i][j].data_width;
 197                                 if (pinfo->dimm_params[i][j].n_ranks
 198                                     && (dw == 72 || dw == 64)) {
 199                                         /*
 200                                          * FIXME: can't really do it
 201                                          * like this because this just
 202                                          * further reduces the memory
 203                                          */
 204                                         found = 1;
 205                                         break;
 206                                 }
 207                         }
 208                         if (found) {
 209                                 dbw_cap_adj[i] = 1;
 210                         }
 211                         break;
 212
 213                 case 0:
 214                         /* 64-bit */
 215                         break;
 216
 217                 default:
 218                         printf("unexpected data bus width "
 219                                 "specified controller %u\n", i);
 220                         return 1;
 221                 }
 222         }
 223
 224         j = 0;
 225         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 226                 if (pinfo->memctl_opts[i].memctl_interleaving)
 227                         j++;
 228         /*
 229          * Not support less than all memory controllers interleaving
 230          * if more than two controllers
 231          */
 232         if (j == CONFIG_NUM_DDR_CONTROLLERS)
 233                 *all_memctl_interleaving = 1;
 234
 235         /* Check that all controllers are rank interleaving. */
 236         j = 0;
 237         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 238                 if (pinfo->memctl_opts[i].ba_intlv_ctl)
 239                         j++;
 240         /*
 241          * All memory controllers must be populated to qualify for
 242          * all controller rank interleaving
 243          */
 244          if (j == CONFIG_NUM_DDR_CONTROLLERS)
 245                 *all_ctlr_rank_interleaving = 1;
 246
 247         if (*all_memctl_interleaving) {
 248                 unsigned long long addr, total_mem_per_ctlr = 0;
 249                 /*
 250                  * If interleaving between memory controllers,
 251                  * make each controller start at a base address
 252                  * of 0.
 253                  *
 254                  * Also, if bank interleaving (chip select
 255                  * interleaving) is enabled on each memory
 256                  * controller, CS0 needs to be programmed to
 257                  * cover the entire memory range on that memory
 258                  * controller
 259                  *
 260                  * Bank interleaving also implies that each
 261                  * addressed chip select is identical in size.
 262                  */
 263
 264                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 265                         addr = 0;
 266                         pinfo->common_timing_params[i].base_address = 0ull;
 267                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 268                                 unsigned long long cap
 269                                         = pinfo->dimm_params[i][j].capacity;
 270
 271                                 pinfo->dimm_params[i][j].base_address = addr;
 272                                 addr += cap >> dbw_cap_adj[i];
 273                                 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
 274                         }
 275                 }
 276                 pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
 277         } else {
 278                 /*
 279                  * Simple linear assignment if memory
 280                  * controllers are not interleaved.
 281                  */
 282                 unsigned long long cur_memsize = 0;
 283                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 284                         u64 total_mem_per_ctlr = 0;
 285                         pinfo->common_timing_params[i].base_address =
 286                                                 cur_memsize;
 287                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 288                                 /* Compute DIMM base addresses. */
 289                                 unsigned long long cap =
 290                                         pinfo->dimm_params[i][j].capacity;
 291                                 pinfo->dimm_params[i][j].base_address =
 292                                         cur_memsize;
 293                                 cur_memsize += cap >> dbw_cap_adj[i];
 294                                 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
 295                         }
 296                         pinfo->common_timing_params[i].total_mem =
 297                                                         total_mem_per_ctlr;
 298                 }
 299         }
 300
 301         return 0;
 302 }
 303
 304 unsigned long long
 305 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 306                                        unsigned int size_only)
 307 {
 308         unsigned int i, j;
 309         unsigned int all_controllers_memctl_interleaving = 0;
 310         unsigned int all_controllers_rank_interleaving = 0;
 311         unsigned long long total_mem = 0;
 312
 313         fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 314         common_timing_params_t *timing_params = pinfo->common_timing_params;
 315
 316         /* data bus width capacity adjust shift amount */
 317         unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
 318
 319         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 320                 dbw_capacity_adjust[i] = 0;
 321         }
 322
 323         debug("starting at step %u (%s)\n",
 324               start_step, step_to_string(start_step));
 325
 326         switch (start_step) {
 327         case STEP_GET_SPD:
 328 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 329                 /* STEP 1:  Gather all DIMM SPD data */
 330                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 331                         fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
 332                 }
 333
 334         case STEP_COMPUTE_DIMM_PARMS:
 335                 /* STEP 2:  Compute DIMM parameters from SPD data */
 336
 337                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 338                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 339                                 unsigned int retval;
 340                                 generic_spd_eeprom_t *spd =
 341                                         &(pinfo->spd_installed_dimms[i][j]);
 342                                 dimm_params_t *pdimm =
 343                                         &(pinfo->dimm_params[i][j]);
 344
 345                                 retval = compute_dimm_parameters(spd, pdimm, i);
 346                                 if (retval == 2) {
 347                                         printf("Error: compute_dimm_parameters"
 348                                         " non-zero returned FATAL value "
 349                                         "for memctl=%u dimm=%u\n", i, j);
 350                                         return 0;
 351                                 }
 352                                 if (retval) {
 353                                         debug("Warning: compute_dimm_parameters"
 354                                         " non-zero return value for memctl=%u "
 355                                         "dimm=%u\n", i, j);
 356                                 }
 357                         }
 358                 }
 359
 360 #else
 361         case STEP_COMPUTE_DIMM_PARMS:
 362                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 363                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 364                                 dimm_params_t *pdimm =
 365                                         &(pinfo->dimm_params[i][j]);
 366                                 fsl_ddr_get_dimm_params(pdimm, i, j);
 367                         }
 368                 }
 369                 debug("Filling dimm parameters from board specific file\n");
 370 #endif
 371         case STEP_COMPUTE_COMMON_PARMS:
 372                 /*
 373                  * STEP 3: Compute a common set of timing parameters
 374                  * suitable for all of the DIMMs on each memory controller
 375                  */
 376                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 377                         debug("Computing lowest common DIMM"
 378                                 " parameters for memctl=%u\n", i);
 379                         compute_lowest_common_dimm_parameters(
 380                                 pinfo->dimm_params[i],
 381                                 &timing_params[i],
 382                                 CONFIG_DIMM_SLOTS_PER_CTLR);
 383                 }
 384
 385         case STEP_GATHER_OPTS:
 386                 /* STEP 4:  Gather configuration requirements from user */
 387                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 388                         debug("Reloading memory controller "
 389                                 "configuration options for memctl=%u\n", i);
 390                         /*
 391                          * This "reloads" the memory controller options
 392                          * to defaults.  If the user "edits" an option,
 393                          * next_step points to the step after this,
 394                          * which is currently STEP_ASSIGN_ADDRESSES.
 395                          */
 396                         populate_memctl_options(
 397                                         timing_params[i].all_DIMMs_registered,
 398                                         &pinfo->memctl_opts[i],
 399                                         pinfo->dimm_params[i], i);
 400                 }
 401                 check_interleaving_options(pinfo);
 402         case STEP_ASSIGN_ADDRESSES:
 403                 /* STEP 5:  Assign addresses to chip selects */
 404                 step_assign_addresses(pinfo,
 405                                 dbw_capacity_adjust,
 406                                 &all_controllers_memctl_interleaving,
 407                                 &all_controllers_rank_interleaving);
 408
 409         case STEP_COMPUTE_REGS:
 410                 /* STEP 6:  compute controller register values */
 411                 debug("FSL Memory ctrl cg register computation\n");
 412                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 413                         if (timing_params[i].ndimms_present == 0) {
 414                                 memset(&ddr_reg[i], 0,
 415                                         sizeof(fsl_ddr_cfg_regs_t));
 416                                 continue;
 417                         }
 418
 419                         compute_fsl_memctl_config_regs(
 420                                         &pinfo->memctl_opts[i],
 421                                         &ddr_reg[i], &timing_params[i],
 422                                         pinfo->dimm_params[i],
 423                                         dbw_capacity_adjust[i],
 424                                         size_only);
 425                 }
 426
 427         default:
 428                 break;
 429         }
 430
 431         /* Compute the total amount of memory. */
 432
 433         /*
 434          * If bank interleaving but NOT memory controller interleaving
 435          * CS_BNDS describe the quantity of memory on each memory
 436          * controller, so the total is the sum across.
 437          */
 438         if (!all_controllers_memctl_interleaving
 439             && all_controllers_rank_interleaving) {
 440                 total_mem = 0;
 441                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 442                         total_mem += timing_params[i].total_mem;
 443                 }
 444
 445         } else {
 446                 /*
 447                  * Compute the amount of memory available just by
 448                  * looking for the highest valid CSn_BNDS value.
 449                  * This allows us to also experiment with using
 450                  * only CS0 when using dual-rank DIMMs.
 451                  */
 452                 unsigned int max_end = 0;
 453
 454                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 455                         for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
 456                                 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
 457                                 if (reg->cs[j].config & 0x80000000) {
 458                                         unsigned int end;
 459                                         end = reg->cs[j].bnds & 0xFFF;
 460                                         if (end > max_end) {
 461                                                 max_end = end;
 462                                         }
 463                                 }
 464                         }
 465                 }
 466
 467                 total_mem = 1 + (((unsigned long long)max_end << 24ULL)
 468                                     | 0xFFFFFFULL);
 469         }
 470
 471         return total_mem;
 472 }
 473
 474 /*
 475  * fsl_ddr_sdram() -- this is the main function to be called by
 476  *      initdram() in the board file.
 477  *
 478  * It returns amount of memory configured in bytes.
 479  */
 480 phys_size_t fsl_ddr_sdram(void)
 481 {
 482         unsigned int i;
 483         unsigned int memctl_interleaved;
 484         unsigned long long total_memory;
 485         fsl_ddr_info_t info;
 486
 487         /* Reset info structure. */
 488         memset(&info, 0, sizeof(fsl_ddr_info_t));
 489
 490         /* Compute it once normally. */
 491         total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
 492
 493         /* Check for memory controller interleaving. */
 494         memctl_interleaved = 0;
 495         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 496                 memctl_interleaved +=
 497                         info.memctl_opts[i].memctl_interleaving;
 498         }
 499
 500         if (memctl_interleaved) {
 501                 if (memctl_interleaved == CONFIG_NUM_DDR_CONTROLLERS) {
 502                         debug("memctl interleaving\n");
 503                         /*
 504                          * Change the meaning of memctl_interleaved
 505                          * to be "boolean".
 506                          */
 507                         memctl_interleaved = 1;
 508                 } else {
 509                         printf("Warning: memctl interleaving not "
 510                                 "properly configured on all controllers\n");
 511                         memctl_interleaved = 0;
 512                         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 513                                 info.memctl_opts[i].memctl_interleaving = 0;
 514                         debug("Recomputing with memctl_interleaving off.\n");
 515                         total_memory = fsl_ddr_compute(&info,
 516                                                        STEP_ASSIGN_ADDRESSES,
 517                                                        0);
 518                 }
 519         }
 520
 521         /* Program configuration registers. */
 522         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 523                 debug("Programming controller %u\n", i);
 524                 if (info.common_timing_params[i].ndimms_present == 0) {
 525                         debug("No dimms present on controller %u; "
 526                                         "skipping programming\n", i);
 527                         continue;
 528                 }
 529
 530                 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
 531         }
 532
 533         if (memctl_interleaved) {
 534                 const unsigned int ctrl_num = 0;
 535
 536                 /* Only set LAWBAR1 if memory controller interleaving is on. */
 537                 fsl_ddr_set_lawbar(&info.common_timing_params[0],
 538                                          memctl_interleaved, ctrl_num);
 539         } else {
 540                 /*
 541                  * Memory controller interleaving is NOT on;
 542                  * set each lawbar individually.
 543                  */
 544                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 545                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 546                                                  0, i);
 547                 }
 548         }
 549
 550         debug("total_memory = %llu\n", total_memory);
 551
 552 #if !defined(CONFIG_PHYS_64BIT)
 553         /* Check for 4G or more.  Bad. */
 554         if (total_memory >= (1ull << 32)) {
 555                 printf("Detected %lld MB of memory\n", total_memory >> 20);
 556                 printf("       This U-Boot only supports < 4G of DDR\n");
 557                 printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
 558                 printf("       "); /* re-align to match init_func_ram print */
 559                 total_memory = CONFIG_MAX_MEM_MAPPED;
 560         }
 561 #endif
 562
 563         return total_memory;
 564 }
 565
 566 /*
 567  * fsl_ddr_sdram_size() - This function only returns the size of the total
 568  * memory without setting ddr control registers.
 569  */
 570 phys_size_t
 571 fsl_ddr_sdram_size(void)
 572 {
 573         fsl_ddr_info_t  info;
 574         unsigned long long total_memory = 0;
 575
 576         memset(&info, 0 , sizeof(fsl_ddr_info_t));
 577
 578         /* Compute it once normally. */
 579         total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
 580
 581         return total_memory;
 582 }