arch/powerpc/cpu/mpc8xxx/ddr/main.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  11  * Based on code from spd_sdram.c
  12  * Author: James Yang [at freescale.com]
  13  */
  14
  15 #include <common.h>
  16 #include <i2c.h>
  17 #include <asm/fsl_ddr_sdram.h>
  18
  19 #include "ddr.h"
  20
  21 extern void fsl_ddr_set_lawbar(
  22                 const common_timing_params_t *memctl_common_params,
  23                 unsigned int memctl_interleaved,
  24                 unsigned int ctrl_num);
  25
  26 /* processor specific function */
  27 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  28                                    unsigned int ctrl_num);
  29
  30 #if defined(SPD_EEPROM_ADDRESS) || \
  31     defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
  32     defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
  33 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  34 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  35         [0][0] = SPD_EEPROM_ADDRESS,
  36 };
  37 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  38 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  39         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  40         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  41 };
  42 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  43 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  44         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  45         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  46 };
  47 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  48 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  49         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  50         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  51         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  52         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  53 };
  54 #endif
  55
  56 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  57 {
  58         int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
  59                                 sizeof(generic_spd_eeprom_t));
  60
  61         if (ret) {
  62                 printf("DDR: failed to read SPD from address %u\n", i2c_address);
  63                 memset(spd, 0, sizeof(generic_spd_eeprom_t));
  64         }
  65 }
  66
  67 __attribute__((weak, alias("__get_spd")))
  68 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
  69
  70 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  71                       unsigned int ctrl_num)
  72 {
  73         unsigned int i;
  74         unsigned int i2c_address = 0;
  75
  76         if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
  77                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  78                 return;
  79         }
  80
  81         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  82                 i2c_address = spd_i2c_addr[ctrl_num][i];
  83                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
  84         }
  85 }
  86 #else
  87 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  88                       unsigned int ctrl_num)
  89 {
  90 }
  91 #endif /* SPD_EEPROM_ADDRESSx */
  92
  93 /*
  94  * ASSUMPTIONS:
  95  *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
  96  *    - Same memory data bus width on all controllers
  97  *
  98  * NOTES:
  99  *
 100  * The memory controller and associated documentation use confusing
 101  * terminology when referring to the orgranization of DRAM.
 102  *
 103  * Here is a terminology translation table:
 104  *
 105  * memory controller/documention  |industry   |this code  |signals
 106  * -------------------------------|-----------|-----------|-----------------
 107  * physical bank/bank             |rank       |rank       |chip select (CS)
 108  * logical bank/sub-bank          |bank       |bank       |bank address (BA)
 109  * page/row                       |row        |page       |row address
 110  * ???                            |column     |column     |column address
 111  *
 112  * The naming confusion is further exacerbated by the descriptions of the
 113  * memory controller interleaving feature, where accesses are interleaved
 114  * _BETWEEN_ two seperate memory controllers.  This is configured only in
 115  * CS0_CONFIG[INTLV_CTL] of each memory controller.
 116  *
 117  * memory controller documentation | number of chip selects
 118  *                                 | per memory controller supported
 119  * --------------------------------|-----------------------------------------
 120  * cache line interleaving         | 1 (CS0 only)
 121  * page interleaving               | 1 (CS0 only)
 122  * bank interleaving               | 1 (CS0 only)
 123  * superbank interleraving         | depends on bank (chip select)
 124  *                                 |   interleraving [rank interleaving]
 125  *                                 |   mode used on every memory controller
 126  *
 127  * Even further confusing is the existence of the interleaving feature
 128  * _WITHIN_ each memory controller.  The feature is referred to in
 129  * documentation as chip select interleaving or bank interleaving,
 130  * although it is configured in the DDR_SDRAM_CFG field.
 131  *
 132  * Name of field                | documentation name    | this code
 133  * -----------------------------|-----------------------|------------------
 134  * DDR_SDRAM_CFG[BA_INTLV_CTL]  | Bank (chip select)    | rank interleaving
 135  *                              |  interleaving
 136  */
 137
 138 #ifdef DEBUG
 139 const char *step_string_tbl[] = {
 140         "STEP_GET_SPD",
 141         "STEP_COMPUTE_DIMM_PARMS",
 142         "STEP_COMPUTE_COMMON_PARMS",
 143         "STEP_GATHER_OPTS",
 144         "STEP_ASSIGN_ADDRESSES",
 145         "STEP_COMPUTE_REGS",
 146         "STEP_PROGRAM_REGS",
 147         "STEP_ALL"
 148 };
 149
 150 const char * step_to_string(unsigned int step) {
 151
 152         unsigned int s = __ilog2(step);
 153
 154         if ((1 << s) != step)
 155                 return step_string_tbl[7];
 156
 157         return step_string_tbl[s];
 158 }
 159 #endif
 160
 161 int step_assign_addresses(fsl_ddr_info_t *pinfo,
 162                           unsigned int dbw_cap_adj[],
 163                           unsigned int *all_memctl_interleaving,
 164                           unsigned int *all_ctlr_rank_interleaving)
 165 {
 166         int i, j;
 167
 168         /*
 169          * If a reduced data width is requested, but the SPD
 170          * specifies a physically wider device, adjust the
 171          * computed dimm capacities accordingly before
 172          * assigning addresses.
 173          */
 174         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 175                 unsigned int found = 0;
 176
 177                 switch (pinfo->memctl_opts[i].data_bus_width) {
 178                 case 2:
 179                         /* 16-bit */
 180                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 181                                 unsigned int dw;
 182                                 if (!pinfo->dimm_params[i][j].n_ranks)
 183                                         continue;
 184                                 dw = pinfo->dimm_params[i][j].primary_sdram_width;
 185                                 if ((dw == 72 || dw == 64)) {
 186                                         dbw_cap_adj[i] = 2;
 187                                         break;
 188                                 } else if ((dw == 40 || dw == 32)) {
 189                                         dbw_cap_adj[i] = 1;
 190                                         break;
 191                                 }
 192                         }
 193                         break;
 194
 195                 case 1:
 196                         /* 32-bit */
 197                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 198                                 unsigned int dw;
 199                                 dw = pinfo->dimm_params[i][j].data_width;
 200                                 if (pinfo->dimm_params[i][j].n_ranks
 201                                     && (dw == 72 || dw == 64)) {
 202                                         /*
 203                                          * FIXME: can't really do it
 204                                          * like this because this just
 205                                          * further reduces the memory
 206                                          */
 207                                         found = 1;
 208                                         break;
 209                                 }
 210                         }
 211                         if (found) {
 212                                 dbw_cap_adj[i] = 1;
 213                         }
 214                         break;
 215
 216                 case 0:
 217                         /* 64-bit */
 218                         break;
 219
 220                 default:
 221                         printf("unexpected data bus width "
 222                                 "specified controller %u\n", i);
 223                         return 1;
 224                 }
 225         }
 226
 227         j = 0;
 228         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 229                 if (pinfo->memctl_opts[i].memctl_interleaving)
 230                         j++;
 231         /*
 232          * Not support less than all memory controllers interleaving
 233          * if more than two controllers
 234          */
 235         if (j == CONFIG_NUM_DDR_CONTROLLERS)
 236                 *all_memctl_interleaving = 1;
 237
 238         /* Check that all controllers are rank interleaving. */
 239         j = 0;
 240         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 241                 if (pinfo->memctl_opts[i].ba_intlv_ctl)
 242                         j++;
 243         /*
 244          * All memory controllers must be populated to qualify for
 245          * all controller rank interleaving
 246          */
 247          if (j == CONFIG_NUM_DDR_CONTROLLERS)
 248                 *all_ctlr_rank_interleaving = 1;
 249
 250         if (*all_memctl_interleaving) {
 251                 unsigned long long addr, total_mem_per_ctlr = 0;
 252                 /*
 253                  * If interleaving between memory controllers,
 254                  * make each controller start at a base address
 255                  * of 0.
 256                  *
 257                  * Also, if bank interleaving (chip select
 258                  * interleaving) is enabled on each memory
 259                  * controller, CS0 needs to be programmed to
 260                  * cover the entire memory range on that memory
 261                  * controller
 262                  *
 263                  * Bank interleaving also implies that each
 264                  * addressed chip select is identical in size.
 265                  */
 266
 267                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 268                         addr = 0;
 269                         pinfo->common_timing_params[i].base_address = 0ull;
 270                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 271                                 unsigned long long cap
 272                                         = pinfo->dimm_params[i][j].capacity;
 273
 274                                 pinfo->dimm_params[i][j].base_address = addr;
 275                                 addr += cap >> dbw_cap_adj[i];
 276                                 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
 277                         }
 278                 }
 279                 pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
 280         } else {
 281                 /*
 282                  * Simple linear assignment if memory
 283                  * controllers are not interleaved.
 284                  */
 285                 unsigned long long cur_memsize = 0;
 286                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 287                         u64 total_mem_per_ctlr = 0;
 288                         pinfo->common_timing_params[i].base_address =
 289                                                 cur_memsize;
 290                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 291                                 /* Compute DIMM base addresses. */
 292                                 unsigned long long cap =
 293                                         pinfo->dimm_params[i][j].capacity;
 294                                 pinfo->dimm_params[i][j].base_address =
 295                                         cur_memsize;
 296                                 cur_memsize += cap >> dbw_cap_adj[i];
 297                                 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
 298                         }
 299                         pinfo->common_timing_params[i].total_mem =
 300                                                         total_mem_per_ctlr;
 301                 }
 302         }
 303
 304         return 0;
 305 }
 306
 307 unsigned long long
 308 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 309                                        unsigned int size_only)
 310 {
 311         unsigned int i, j;
 312         unsigned int all_controllers_memctl_interleaving = 0;
 313         unsigned int all_controllers_rank_interleaving = 0;
 314         unsigned long long total_mem = 0;
 315
 316         fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 317         common_timing_params_t *timing_params = pinfo->common_timing_params;
 318
 319         /* data bus width capacity adjust shift amount */
 320         unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
 321
 322         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 323                 dbw_capacity_adjust[i] = 0;
 324         }
 325
 326         debug("starting at step %u (%s)\n",
 327               start_step, step_to_string(start_step));
 328
 329         switch (start_step) {
 330         case STEP_GET_SPD:
 331 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 332                 /* STEP 1:  Gather all DIMM SPD data */
 333                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 334                         fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
 335                 }
 336
 337         case STEP_COMPUTE_DIMM_PARMS:
 338                 /* STEP 2:  Compute DIMM parameters from SPD data */
 339
 340                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 341                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 342                                 unsigned int retval;
 343                                 generic_spd_eeprom_t *spd =
 344                                         &(pinfo->spd_installed_dimms[i][j]);
 345                                 dimm_params_t *pdimm =
 346                                         &(pinfo->dimm_params[i][j]);
 347
 348                                 retval = compute_dimm_parameters(spd, pdimm, i);
 349 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 350                                 if (retval != 0) {
 351                                         printf("SPD error! Trying fallback to "
 352                                         "raw timing calculation\n");
 353                                         fsl_ddr_get_dimm_params(pdimm, i, j);
 354                                 }
 355 #else
 356                                 if (retval == 2) {
 357                                         printf("Error: compute_dimm_parameters"
 358                                         " non-zero returned FATAL value "
 359                                         "for memctl=%u dimm=%u\n", i, j);
 360                                         return 0;
 361                                 }
 362 #endif
 363                                 if (retval) {
 364                                         debug("Warning: compute_dimm_parameters"
 365                                         " non-zero return value for memctl=%u "
 366                                         "dimm=%u\n", i, j);
 367                                 }
 368                         }
 369                 }
 370
 371 #else
 372         case STEP_COMPUTE_DIMM_PARMS:
 373                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 374                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 375                                 dimm_params_t *pdimm =
 376                                         &(pinfo->dimm_params[i][j]);
 377                                 fsl_ddr_get_dimm_params(pdimm, i, j);
 378                         }
 379                 }
 380                 debug("Filling dimm parameters from board specific file\n");
 381 #endif
 382         case STEP_COMPUTE_COMMON_PARMS:
 383                 /*
 384                  * STEP 3: Compute a common set of timing parameters
 385                  * suitable for all of the DIMMs on each memory controller
 386                  */
 387                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 388                         debug("Computing lowest common DIMM"
 389                                 " parameters for memctl=%u\n", i);
 390                         compute_lowest_common_dimm_parameters(
 391                                 pinfo->dimm_params[i],
 392                                 &timing_params[i],
 393                                 CONFIG_DIMM_SLOTS_PER_CTLR);
 394                 }
 395
 396         case STEP_GATHER_OPTS:
 397                 /* STEP 4:  Gather configuration requirements from user */
 398                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 399                         debug("Reloading memory controller "
 400                                 "configuration options for memctl=%u\n", i);
 401                         /*
 402                          * This "reloads" the memory controller options
 403                          * to defaults.  If the user "edits" an option,
 404                          * next_step points to the step after this,
 405                          * which is currently STEP_ASSIGN_ADDRESSES.
 406                          */
 407                         populate_memctl_options(
 408                                         timing_params[i].all_DIMMs_registered,
 409                                         &pinfo->memctl_opts[i],
 410                                         pinfo->dimm_params[i], i);
 411                 }
 412                 check_interleaving_options(pinfo);
 413         case STEP_ASSIGN_ADDRESSES:
 414                 /* STEP 5:  Assign addresses to chip selects */
 415                 step_assign_addresses(pinfo,
 416                                 dbw_capacity_adjust,
 417                                 &all_controllers_memctl_interleaving,
 418                                 &all_controllers_rank_interleaving);
 419
 420         case STEP_COMPUTE_REGS:
 421                 /* STEP 6:  compute controller register values */
 422                 debug("FSL Memory ctrl cg register computation\n");
 423                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 424                         if (timing_params[i].ndimms_present == 0) {
 425                                 memset(&ddr_reg[i], 0,
 426                                         sizeof(fsl_ddr_cfg_regs_t));
 427                                 continue;
 428                         }
 429
 430                         compute_fsl_memctl_config_regs(
 431                                         &pinfo->memctl_opts[i],
 432                                         &ddr_reg[i], &timing_params[i],
 433                                         pinfo->dimm_params[i],
 434                                         dbw_capacity_adjust[i],
 435                                         size_only);
 436                 }
 437
 438         default:
 439                 break;
 440         }
 441
 442         /* Compute the total amount of memory. */
 443
 444         /*
 445          * If bank interleaving but NOT memory controller interleaving
 446          * CS_BNDS describe the quantity of memory on each memory
 447          * controller, so the total is the sum across.
 448          */
 449         if (!all_controllers_memctl_interleaving
 450             && all_controllers_rank_interleaving) {
 451                 total_mem = 0;
 452                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 453                         total_mem += timing_params[i].total_mem;
 454                 }
 455
 456         } else {
 457                 /*
 458                  * Compute the amount of memory available just by
 459                  * looking for the highest valid CSn_BNDS value.
 460                  * This allows us to also experiment with using
 461                  * only CS0 when using dual-rank DIMMs.
 462                  */
 463                 unsigned int max_end = 0;
 464
 465                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 466                         for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
 467                                 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
 468                                 if (reg->cs[j].config & 0x80000000) {
 469                                         unsigned int end;
 470                                         end = reg->cs[j].bnds & 0xFFF;
 471                                         if (end > max_end) {
 472                                                 max_end = end;
 473                                         }
 474                                 }
 475                         }
 476                 }
 477
 478                 total_mem = 1 + (((unsigned long long)max_end << 24ULL)
 479                                     | 0xFFFFFFULL);
 480         }
 481
 482         return total_mem;
 483 }
 484
 485 /*
 486  * fsl_ddr_sdram() -- this is the main function to be called by
 487  *      initdram() in the board file.
 488  *
 489  * It returns amount of memory configured in bytes.
 490  */
 491 phys_size_t fsl_ddr_sdram(void)
 492 {
 493         unsigned int i;
 494         unsigned int memctl_interleaved;
 495         unsigned long long total_memory;
 496         fsl_ddr_info_t info;
 497
 498         /* Reset info structure. */
 499         memset(&info, 0, sizeof(fsl_ddr_info_t));
 500
 501         /* Compute it once normally. */
 502         total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
 503
 504         /* Check for memory controller interleaving. */
 505         memctl_interleaved = 0;
 506         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 507                 memctl_interleaved +=
 508                         info.memctl_opts[i].memctl_interleaving;
 509         }
 510
 511         if (memctl_interleaved) {
 512                 if (memctl_interleaved == CONFIG_NUM_DDR_CONTROLLERS) {
 513                         debug("memctl interleaving\n");
 514                         /*
 515                          * Change the meaning of memctl_interleaved
 516                          * to be "boolean".
 517                          */
 518                         memctl_interleaved = 1;
 519                 } else {
 520                         printf("Warning: memctl interleaving not "
 521                                 "properly configured on all controllers\n");
 522                         memctl_interleaved = 0;
 523                         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 524                                 info.memctl_opts[i].memctl_interleaving = 0;
 525                         debug("Recomputing with memctl_interleaving off.\n");
 526                         total_memory = fsl_ddr_compute(&info,
 527                                                        STEP_ASSIGN_ADDRESSES,
 528                                                        0);
 529                 }
 530         }
 531
 532         /* Program configuration registers. */
 533         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 534                 debug("Programming controller %u\n", i);
 535                 if (info.common_timing_params[i].ndimms_present == 0) {
 536                         debug("No dimms present on controller %u; "
 537                                         "skipping programming\n", i);
 538                         continue;
 539                 }
 540
 541                 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
 542         }
 543
 544         if (memctl_interleaved) {
 545                 const unsigned int ctrl_num = 0;
 546
 547                 /* Only set LAWBAR1 if memory controller interleaving is on. */
 548                 fsl_ddr_set_lawbar(&info.common_timing_params[0],
 549                                          memctl_interleaved, ctrl_num);
 550         } else {
 551                 /*
 552                  * Memory controller interleaving is NOT on;
 553                  * set each lawbar individually.
 554                  */
 555                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 556                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 557                                                  0, i);
 558                 }
 559         }
 560
 561         debug("total_memory = %llu\n", total_memory);
 562
 563 #if !defined(CONFIG_PHYS_64BIT)
 564         /* Check for 4G or more.  Bad. */
 565         if (total_memory >= (1ull << 32)) {
 566                 printf("Detected %lld MB of memory\n", total_memory >> 20);
 567                 printf("       This U-Boot only supports < 4G of DDR\n");
 568                 printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
 569                 printf("       "); /* re-align to match init_func_ram print */
 570                 total_memory = CONFIG_MAX_MEM_MAPPED;
 571         }
 572 #endif
 573
 574         return total_memory;
 575 }
 576
 577 /*
 578  * fsl_ddr_sdram_size() - This function only returns the size of the total
 579  * memory without setting ddr control registers.
 580  */
 581 phys_size_t
 582 fsl_ddr_sdram_size(void)
 583 {
 584         fsl_ddr_info_t  info;
 585         unsigned long long total_memory = 0;
 586
 587         memset(&info, 0 , sizeof(fsl_ddr_info_t));
 588
 589         /* Compute it once normally. */
 590         total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
 591
 592         return total_memory;
 593 }