2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
17 #include <asm/fsl_ddr_sdram.h>
21 extern void fsl_ddr_set_lawbar(
22 const common_timing_params_t *memctl_common_params,
23 unsigned int memctl_interleaved,
24 unsigned int ctrl_num);
26 /* processor specific function */
27 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
28 unsigned int ctrl_num);
30 #if defined(SPD_EEPROM_ADDRESS) || \
31 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
32 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
33 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
34 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
35 [0][0] = SPD_EEPROM_ADDRESS,
38 #if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
39 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
40 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
41 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
44 #if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
45 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
46 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
47 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
48 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
49 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
53 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
55 int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
56 sizeof(generic_spd_eeprom_t));
59 printf("DDR: failed to read SPD from address %u\n", i2c_address);
60 memset(spd, 0, sizeof(generic_spd_eeprom_t));
64 __attribute__((weak, alias("__get_spd")))
65 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
67 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
68 unsigned int ctrl_num)
71 unsigned int i2c_address = 0;
73 if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
74 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
78 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
79 i2c_address = spd_i2c_addr[ctrl_num][i];
80 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
84 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
85 unsigned int ctrl_num)
88 #endif /* SPD_EEPROM_ADDRESSx */
92 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
93 * - Same memory data bus width on all controllers
97 * The memory controller and associated documentation use confusing
98 * terminology when referring to the orgranization of DRAM.
100 * Here is a terminology translation table:
102 * memory controller/documention |industry |this code |signals
103 * -------------------------------|-----------|-----------|-----------------
104 * physical bank/bank |rank |rank |chip select (CS)
105 * logical bank/sub-bank |bank |bank |bank address (BA)
106 * page/row |row |page |row address
107 * ??? |column |column |column address
109 * The naming confusion is further exacerbated by the descriptions of the
110 * memory controller interleaving feature, where accesses are interleaved
111 * _BETWEEN_ two seperate memory controllers. This is configured only in
112 * CS0_CONFIG[INTLV_CTL] of each memory controller.
114 * memory controller documentation | number of chip selects
115 * | per memory controller supported
116 * --------------------------------|-----------------------------------------
117 * cache line interleaving | 1 (CS0 only)
118 * page interleaving | 1 (CS0 only)
119 * bank interleaving | 1 (CS0 only)
120 * superbank interleraving | depends on bank (chip select)
121 * | interleraving [rank interleaving]
122 * | mode used on every memory controller
124 * Even further confusing is the existence of the interleaving feature
125 * _WITHIN_ each memory controller. The feature is referred to in
126 * documentation as chip select interleaving or bank interleaving,
127 * although it is configured in the DDR_SDRAM_CFG field.
129 * Name of field | documentation name | this code
130 * -----------------------------|-----------------------|------------------
131 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
136 const char *step_string_tbl[] = {
138 "STEP_COMPUTE_DIMM_PARMS",
139 "STEP_COMPUTE_COMMON_PARMS",
141 "STEP_ASSIGN_ADDRESSES",
147 const char * step_to_string(unsigned int step) {
149 unsigned int s = __ilog2(step);
151 if ((1 << s) != step)
152 return step_string_tbl[7];
154 return step_string_tbl[s];
158 int step_assign_addresses(fsl_ddr_info_t *pinfo,
159 unsigned int dbw_cap_adj[],
160 unsigned int *all_memctl_interleaving,
161 unsigned int *all_ctlr_rank_interleaving)
166 * If a reduced data width is requested, but the SPD
167 * specifies a physically wider device, adjust the
168 * computed dimm capacities accordingly before
169 * assigning addresses.
171 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
172 unsigned int found = 0;
174 switch (pinfo->memctl_opts[i].data_bus_width) {
177 printf("can't handle 16-bit mode yet\n");
182 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
184 dw = pinfo->dimm_params[i][j].data_width;
185 if (pinfo->dimm_params[i][j].n_ranks
186 && (dw == 72 || dw == 64)) {
188 * FIXME: can't really do it
189 * like this because this just
190 * further reduces the memory
206 printf("unexpected data bus width "
207 "specified controller %u\n", i);
213 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
214 if (pinfo->memctl_opts[i].memctl_interleaving)
217 * Not support less than all memory controllers interleaving
218 * if more than two controllers
220 if (j == CONFIG_NUM_DDR_CONTROLLERS)
221 *all_memctl_interleaving = 1;
223 /* Check that all controllers are rank interleaving. */
225 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
226 if (pinfo->memctl_opts[i].ba_intlv_ctl)
229 * All memory controllers must be populated to qualify for
230 * all controller rank interleaving
232 if (j == CONFIG_NUM_DDR_CONTROLLERS)
233 *all_ctlr_rank_interleaving = 1;
235 if (*all_memctl_interleaving) {
236 unsigned long long addr, total_mem_per_ctlr = 0;
238 * If interleaving between memory controllers,
239 * make each controller start at a base address
242 * Also, if bank interleaving (chip select
243 * interleaving) is enabled on each memory
244 * controller, CS0 needs to be programmed to
245 * cover the entire memory range on that memory
248 * Bank interleaving also implies that each
249 * addressed chip select is identical in size.
252 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
254 pinfo->common_timing_params[i].base_address = 0ull;
255 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
256 unsigned long long cap
257 = pinfo->dimm_params[i][j].capacity;
259 pinfo->dimm_params[i][j].base_address = addr;
260 addr += cap >> dbw_cap_adj[i];
261 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
264 pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
267 * Simple linear assignment if memory
268 * controllers are not interleaved.
270 unsigned long long cur_memsize = 0;
271 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
272 u64 total_mem_per_ctlr = 0;
273 pinfo->common_timing_params[i].base_address =
275 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
276 /* Compute DIMM base addresses. */
277 unsigned long long cap =
278 pinfo->dimm_params[i][j].capacity;
279 pinfo->dimm_params[i][j].base_address =
281 cur_memsize += cap >> dbw_cap_adj[i];
282 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
284 pinfo->common_timing_params[i].total_mem =
293 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
294 unsigned int size_only)
297 unsigned int all_controllers_memctl_interleaving = 0;
298 unsigned int all_controllers_rank_interleaving = 0;
299 unsigned long long total_mem = 0;
301 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
302 common_timing_params_t *timing_params = pinfo->common_timing_params;
304 /* data bus width capacity adjust shift amount */
305 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
307 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
308 dbw_capacity_adjust[i] = 0;
311 debug("starting at step %u (%s)\n",
312 start_step, step_to_string(start_step));
314 switch (start_step) {
316 /* STEP 1: Gather all DIMM SPD data */
317 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
318 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
321 case STEP_COMPUTE_DIMM_PARMS:
322 /* STEP 2: Compute DIMM parameters from SPD data */
324 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
325 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
327 generic_spd_eeprom_t *spd =
328 &(pinfo->spd_installed_dimms[i][j]);
329 dimm_params_t *pdimm =
330 &(pinfo->dimm_params[i][j]);
332 retval = compute_dimm_parameters(spd, pdimm, i);
334 printf("Error: compute_dimm_parameters"
335 " non-zero returned FATAL value "
336 "for memctl=%u dimm=%u\n", i, j);
340 debug("Warning: compute_dimm_parameters"
341 " non-zero return value for memctl=%u "
347 case STEP_COMPUTE_COMMON_PARMS:
349 * STEP 3: Compute a common set of timing parameters
350 * suitable for all of the DIMMs on each memory controller
352 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
353 debug("Computing lowest common DIMM"
354 " parameters for memctl=%u\n", i);
355 compute_lowest_common_dimm_parameters(
356 pinfo->dimm_params[i],
358 CONFIG_DIMM_SLOTS_PER_CTLR);
361 case STEP_GATHER_OPTS:
362 /* STEP 4: Gather configuration requirements from user */
363 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
364 debug("Reloading memory controller "
365 "configuration options for memctl=%u\n", i);
367 * This "reloads" the memory controller options
368 * to defaults. If the user "edits" an option,
369 * next_step points to the step after this,
370 * which is currently STEP_ASSIGN_ADDRESSES.
372 populate_memctl_options(
373 timing_params[i].all_DIMMs_registered,
374 &pinfo->memctl_opts[i],
375 pinfo->dimm_params[i], i);
377 check_interleaving_options(pinfo);
378 case STEP_ASSIGN_ADDRESSES:
379 /* STEP 5: Assign addresses to chip selects */
380 step_assign_addresses(pinfo,
382 &all_controllers_memctl_interleaving,
383 &all_controllers_rank_interleaving);
385 case STEP_COMPUTE_REGS:
386 /* STEP 6: compute controller register values */
387 debug("FSL Memory ctrl cg register computation\n");
388 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
389 if (timing_params[i].ndimms_present == 0) {
390 memset(&ddr_reg[i], 0,
391 sizeof(fsl_ddr_cfg_regs_t));
395 compute_fsl_memctl_config_regs(
396 &pinfo->memctl_opts[i],
397 &ddr_reg[i], &timing_params[i],
398 pinfo->dimm_params[i],
399 dbw_capacity_adjust[i],
407 /* Compute the total amount of memory. */
410 * If bank interleaving but NOT memory controller interleaving
411 * CS_BNDS describe the quantity of memory on each memory
412 * controller, so the total is the sum across.
414 if (!all_controllers_memctl_interleaving
415 && all_controllers_rank_interleaving) {
417 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
418 total_mem += timing_params[i].total_mem;
423 * Compute the amount of memory available just by
424 * looking for the highest valid CSn_BNDS value.
425 * This allows us to also experiment with using
426 * only CS0 when using dual-rank DIMMs.
428 unsigned int max_end = 0;
430 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
431 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
432 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
433 if (reg->cs[j].config & 0x80000000) {
435 end = reg->cs[j].bnds & 0xFFF;
443 total_mem = 1 + (((unsigned long long)max_end << 24ULL)
451 * fsl_ddr_sdram() -- this is the main function to be called by
452 * initdram() in the board file.
454 * It returns amount of memory configured in bytes.
456 phys_size_t fsl_ddr_sdram(void)
459 unsigned int memctl_interleaved;
460 unsigned long long total_memory;
463 /* Reset info structure. */
464 memset(&info, 0, sizeof(fsl_ddr_info_t));
466 /* Compute it once normally. */
467 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
469 /* Check for memory controller interleaving. */
470 memctl_interleaved = 0;
471 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
472 memctl_interleaved +=
473 info.memctl_opts[i].memctl_interleaving;
476 if (memctl_interleaved) {
477 if (memctl_interleaved == CONFIG_NUM_DDR_CONTROLLERS) {
478 debug("memctl interleaving\n");
480 * Change the meaning of memctl_interleaved
483 memctl_interleaved = 1;
485 printf("Warning: memctl interleaving not "
486 "properly configured on all controllers\n");
487 memctl_interleaved = 0;
488 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
489 info.memctl_opts[i].memctl_interleaving = 0;
490 debug("Recomputing with memctl_interleaving off.\n");
491 total_memory = fsl_ddr_compute(&info,
492 STEP_ASSIGN_ADDRESSES,
497 /* Program configuration registers. */
498 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
499 debug("Programming controller %u\n", i);
500 if (info.common_timing_params[i].ndimms_present == 0) {
501 debug("No dimms present on controller %u; "
502 "skipping programming\n", i);
506 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
509 if (memctl_interleaved) {
510 const unsigned int ctrl_num = 0;
512 /* Only set LAWBAR1 if memory controller interleaving is on. */
513 fsl_ddr_set_lawbar(&info.common_timing_params[0],
514 memctl_interleaved, ctrl_num);
517 * Memory controller interleaving is NOT on;
518 * set each lawbar individually.
520 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
521 fsl_ddr_set_lawbar(&info.common_timing_params[i],
526 debug("total_memory = %llu\n", total_memory);
528 #if !defined(CONFIG_PHYS_64BIT)
529 /* Check for 4G or more. Bad. */
530 if (total_memory >= (1ull << 32)) {
531 printf("Detected %lld MB of memory\n", total_memory >> 20);
532 printf(" This U-Boot only supports < 4G of DDR\n");
533 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
534 printf(" "); /* re-align to match init_func_ram print */
535 total_memory = CONFIG_MAX_MEM_MAPPED;
543 * fsl_ddr_sdram_size() - This function only returns the size of the total
544 * memory without setting ddr control registers.
547 fsl_ddr_sdram_size(void)
550 unsigned long long total_memory = 0;
552 memset(&info, 0 , sizeof(fsl_ddr_info_t));
554 /* Compute it once normally. */
555 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);