arch/powerpc/cpu/mpc8xxx/ddr/main.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  11  * Based on code from spd_sdram.c
  12  * Author: James Yang [at freescale.com]
  13  */
  14
  15 #include <common.h>
  16 #include <i2c.h>
  17 #include <asm/fsl_ddr_sdram.h>
  18 #include <asm/fsl_law.h>
  19
  20 #include "ddr.h"
  21
  22 void fsl_ddr_set_lawbar(
  23                 const common_timing_params_t *memctl_common_params,
  24                 unsigned int memctl_interleaved,
  25                 unsigned int ctrl_num);
  26 void fsl_ddr_set_intl3r(const unsigned int granule_size);
  27
  28 /* processor specific function */
  29 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  30                                    unsigned int ctrl_num);
  31
  32 #if defined(SPD_EEPROM_ADDRESS) || \
  33     defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
  34     defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
  35 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  36 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  37         [0][0] = SPD_EEPROM_ADDRESS,
  38 };
  39 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  40 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  41         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  42         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  43 };
  44 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  45 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  46         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  47         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  48 };
  49 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  50 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  51         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  52         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  53         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  54         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  55 };
  56 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  57 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  58         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  59         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  60         [2][0] = SPD_EEPROM_ADDRESS3,   /* controller 3 */
  61 };
  62 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  63 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  64         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  65         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  66         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  67         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  68         [2][0] = SPD_EEPROM_ADDRESS5,   /* controller 3 */
  69         [2][1] = SPD_EEPROM_ADDRESS6,   /* controller 3 */
  70 };
  71
  72 #endif
  73
  74 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  75 {
  76         int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
  77                                 sizeof(generic_spd_eeprom_t));
  78
  79         if (ret) {
  80                 printf("DDR: failed to read SPD from address %u\n", i2c_address);
  81                 memset(spd, 0, sizeof(generic_spd_eeprom_t));
  82         }
  83 }
  84
  85 __attribute__((weak, alias("__get_spd")))
  86 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
  87
  88 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  89                       unsigned int ctrl_num)
  90 {
  91         unsigned int i;
  92         unsigned int i2c_address = 0;
  93
  94         if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
  95                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  96                 return;
  97         }
  98
  99         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
 100                 i2c_address = spd_i2c_addr[ctrl_num][i];
 101                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
 102         }
 103 }
 104 #else
 105 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 106                       unsigned int ctrl_num)
 107 {
 108 }
 109 #endif /* SPD_EEPROM_ADDRESSx */
 110
 111 /*
 112  * ASSUMPTIONS:
 113  *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
 114  *    - Same memory data bus width on all controllers
 115  *
 116  * NOTES:
 117  *
 118  * The memory controller and associated documentation use confusing
 119  * terminology when referring to the orgranization of DRAM.
 120  *
 121  * Here is a terminology translation table:
 122  *
 123  * memory controller/documention  |industry   |this code  |signals
 124  * -------------------------------|-----------|-----------|-----------------
 125  * physical bank/bank             |rank       |rank       |chip select (CS)
 126  * logical bank/sub-bank          |bank       |bank       |bank address (BA)
 127  * page/row                       |row        |page       |row address
 128  * ???                            |column     |column     |column address
 129  *
 130  * The naming confusion is further exacerbated by the descriptions of the
 131  * memory controller interleaving feature, where accesses are interleaved
 132  * _BETWEEN_ two seperate memory controllers.  This is configured only in
 133  * CS0_CONFIG[INTLV_CTL] of each memory controller.
 134  *
 135  * memory controller documentation | number of chip selects
 136  *                                 | per memory controller supported
 137  * --------------------------------|-----------------------------------------
 138  * cache line interleaving         | 1 (CS0 only)
 139  * page interleaving               | 1 (CS0 only)
 140  * bank interleaving               | 1 (CS0 only)
 141  * superbank interleraving         | depends on bank (chip select)
 142  *                                 |   interleraving [rank interleaving]
 143  *                                 |   mode used on every memory controller
 144  *
 145  * Even further confusing is the existence of the interleaving feature
 146  * _WITHIN_ each memory controller.  The feature is referred to in
 147  * documentation as chip select interleaving or bank interleaving,
 148  * although it is configured in the DDR_SDRAM_CFG field.
 149  *
 150  * Name of field                | documentation name    | this code
 151  * -----------------------------|-----------------------|------------------
 152  * DDR_SDRAM_CFG[BA_INTLV_CTL]  | Bank (chip select)    | rank interleaving
 153  *                              |  interleaving
 154  */
 155
 156 const char *step_string_tbl[] = {
 157         "STEP_GET_SPD",
 158         "STEP_COMPUTE_DIMM_PARMS",
 159         "STEP_COMPUTE_COMMON_PARMS",
 160         "STEP_GATHER_OPTS",
 161         "STEP_ASSIGN_ADDRESSES",
 162         "STEP_COMPUTE_REGS",
 163         "STEP_PROGRAM_REGS",
 164         "STEP_ALL"
 165 };
 166
 167 const char * step_to_string(unsigned int step) {
 168
 169         unsigned int s = __ilog2(step);
 170
 171         if ((1 << s) != step)
 172                 return step_string_tbl[7];
 173
 174         return step_string_tbl[s];
 175 }
 176
 177 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 178                           unsigned int dbw_cap_adj[])
 179 {
 180         int i, j;
 181         unsigned long long total_mem, current_mem_base, total_ctlr_mem;
 182         unsigned long long rank_density, ctlr_density = 0;
 183
 184         /*
 185          * If a reduced data width is requested, but the SPD
 186          * specifies a physically wider device, adjust the
 187          * computed dimm capacities accordingly before
 188          * assigning addresses.
 189          */
 190         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 191                 unsigned int found = 0;
 192
 193                 switch (pinfo->memctl_opts[i].data_bus_width) {
 194                 case 2:
 195                         /* 16-bit */
 196                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 197                                 unsigned int dw;
 198                                 if (!pinfo->dimm_params[i][j].n_ranks)
 199                                         continue;
 200                                 dw = pinfo->dimm_params[i][j].primary_sdram_width;
 201                                 if ((dw == 72 || dw == 64)) {
 202                                         dbw_cap_adj[i] = 2;
 203                                         break;
 204                                 } else if ((dw == 40 || dw == 32)) {
 205                                         dbw_cap_adj[i] = 1;
 206                                         break;
 207                                 }
 208                         }
 209                         break;
 210
 211                 case 1:
 212                         /* 32-bit */
 213                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 214                                 unsigned int dw;
 215                                 dw = pinfo->dimm_params[i][j].data_width;
 216                                 if (pinfo->dimm_params[i][j].n_ranks
 217                                     && (dw == 72 || dw == 64)) {
 218                                         /*
 219                                          * FIXME: can't really do it
 220                                          * like this because this just
 221                                          * further reduces the memory
 222                                          */
 223                                         found = 1;
 224                                         break;
 225                                 }
 226                         }
 227                         if (found) {
 228                                 dbw_cap_adj[i] = 1;
 229                         }
 230                         break;
 231
 232                 case 0:
 233                         /* 64-bit */
 234                         break;
 235
 236                 default:
 237                         printf("unexpected data bus width "
 238                                 "specified controller %u\n", i);
 239                         return 1;
 240                 }
 241                 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
 242         }
 243
 244         current_mem_base = 0ull;
 245         total_mem = 0;
 246         if (pinfo->memctl_opts[0].memctl_interleaving) {
 247                 rank_density = pinfo->dimm_params[0][0].rank_density >>
 248                                         dbw_cap_adj[0];
 249                 switch (pinfo->memctl_opts[0].ba_intlv_ctl &
 250                                         FSL_DDR_CS0_CS1_CS2_CS3) {
 251                 case FSL_DDR_CS0_CS1_CS2_CS3:
 252                         ctlr_density = 4 * rank_density;
 253                         break;
 254                 case FSL_DDR_CS0_CS1:
 255                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 256                         ctlr_density = 2 * rank_density;
 257                         break;
 258                 case FSL_DDR_CS2_CS3:
 259                 default:
 260                         ctlr_density = rank_density;
 261                         break;
 262                 }
 263                 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
 264                         rank_density, ctlr_density);
 265                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 266                         if (pinfo->memctl_opts[i].memctl_interleaving) {
 267                                 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
 268                                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 269                                 case FSL_DDR_PAGE_INTERLEAVING:
 270                                 case FSL_DDR_BANK_INTERLEAVING:
 271                                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 272                                         total_ctlr_mem = 2 * ctlr_density;
 273                                         break;
 274                                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 275                                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 276                                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 277                                         total_ctlr_mem = 3 * ctlr_density;
 278                                         break;
 279                                 case FSL_DDR_4WAY_1KB_INTERLEAVING:
 280                                 case FSL_DDR_4WAY_4KB_INTERLEAVING:
 281                                 case FSL_DDR_4WAY_8KB_INTERLEAVING:
 282                                         total_ctlr_mem = 4 * ctlr_density;
 283                                         break;
 284                                 default:
 285                                         panic("Unknown interleaving mode");
 286                                 }
 287                                 pinfo->common_timing_params[i].base_address =
 288                                                         current_mem_base;
 289                                 pinfo->common_timing_params[i].total_mem =
 290                                                         total_ctlr_mem;
 291                                 total_mem = current_mem_base + total_ctlr_mem;
 292                                 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
 293                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 294                         } else {
 295                                 /* when 3rd controller not interleaved */
 296                                 current_mem_base = total_mem;
 297                                 total_ctlr_mem = 0;
 298                                 pinfo->common_timing_params[i].base_address =
 299                                                         current_mem_base;
 300                                 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 301                                         unsigned long long cap =
 302                                                 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 303                                         pinfo->dimm_params[i][j].base_address =
 304                                                 current_mem_base;
 305                                         debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 306                                         current_mem_base += cap;
 307                                         total_ctlr_mem += cap;
 308                                 }
 309                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 310                                 pinfo->common_timing_params[i].total_mem =
 311                                                         total_ctlr_mem;
 312                                 total_mem += total_ctlr_mem;
 313                         }
 314                 }
 315         } else {
 316                 /*
 317                  * Simple linear assignment if memory
 318                  * controllers are not interleaved.
 319                  */
 320                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 321                         total_ctlr_mem = 0;
 322                         pinfo->common_timing_params[i].base_address =
 323                                                 current_mem_base;
 324                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 325                                 /* Compute DIMM base addresses. */
 326                                 unsigned long long cap =
 327                                         pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 328                                 pinfo->dimm_params[i][j].base_address =
 329                                         current_mem_base;
 330                                 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 331                                 current_mem_base += cap;
 332                                 total_ctlr_mem += cap;
 333                         }
 334                         debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 335                         pinfo->common_timing_params[i].total_mem =
 336                                                         total_ctlr_mem;
 337                         total_mem += total_ctlr_mem;
 338                 }
 339         }
 340         debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
 341
 342         return total_mem;
 343 }
 344
 345 unsigned long long
 346 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 347                                        unsigned int size_only)
 348 {
 349         unsigned int i, j;
 350         unsigned long long total_mem = 0;
 351
 352         fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 353         common_timing_params_t *timing_params = pinfo->common_timing_params;
 354
 355         /* data bus width capacity adjust shift amount */
 356         unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
 357
 358         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 359                 dbw_capacity_adjust[i] = 0;
 360         }
 361
 362         debug("starting at step %u (%s)\n",
 363               start_step, step_to_string(start_step));
 364
 365         switch (start_step) {
 366         case STEP_GET_SPD:
 367 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 368                 /* STEP 1:  Gather all DIMM SPD data */
 369                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 370                         fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
 371                 }
 372
 373         case STEP_COMPUTE_DIMM_PARMS:
 374                 /* STEP 2:  Compute DIMM parameters from SPD data */
 375
 376                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 377                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 378                                 unsigned int retval;
 379                                 generic_spd_eeprom_t *spd =
 380                                         &(pinfo->spd_installed_dimms[i][j]);
 381                                 dimm_params_t *pdimm =
 382                                         &(pinfo->dimm_params[i][j]);
 383
 384                                 retval = compute_dimm_parameters(spd, pdimm, i);
 385 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 386                                 if (retval != 0) {
 387                                         printf("SPD error on controller %d! "
 388                                         "Trying fallback to raw timing "
 389                                         "calculation\n", i);
 390                                         fsl_ddr_get_dimm_params(pdimm, i, j);
 391                                 }
 392 #else
 393                                 if (retval == 2) {
 394                                         printf("Error: compute_dimm_parameters"
 395                                         " non-zero returned FATAL value "
 396                                         "for memctl=%u dimm=%u\n", i, j);
 397                                         return 0;
 398                                 }
 399 #endif
 400                                 if (retval) {
 401                                         debug("Warning: compute_dimm_parameters"
 402                                         " non-zero return value for memctl=%u "
 403                                         "dimm=%u\n", i, j);
 404                                 }
 405                         }
 406                 }
 407
 408 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
 409         case STEP_COMPUTE_DIMM_PARMS:
 410                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 411                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 412                                 dimm_params_t *pdimm =
 413                                         &(pinfo->dimm_params[i][j]);
 414                                 fsl_ddr_get_dimm_params(pdimm, i, j);
 415                         }
 416                 }
 417                 debug("Filling dimm parameters from board specific file\n");
 418 #endif
 419         case STEP_COMPUTE_COMMON_PARMS:
 420                 /*
 421                  * STEP 3: Compute a common set of timing parameters
 422                  * suitable for all of the DIMMs on each memory controller
 423                  */
 424                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 425                         debug("Computing lowest common DIMM"
 426                                 " parameters for memctl=%u\n", i);
 427                         compute_lowest_common_dimm_parameters(
 428                                 pinfo->dimm_params[i],
 429                                 &timing_params[i],
 430                                 CONFIG_DIMM_SLOTS_PER_CTLR);
 431                 }
 432
 433         case STEP_GATHER_OPTS:
 434                 /* STEP 4:  Gather configuration requirements from user */
 435                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 436                         debug("Reloading memory controller "
 437                                 "configuration options for memctl=%u\n", i);
 438                         /*
 439                          * This "reloads" the memory controller options
 440                          * to defaults.  If the user "edits" an option,
 441                          * next_step points to the step after this,
 442                          * which is currently STEP_ASSIGN_ADDRESSES.
 443                          */
 444                         populate_memctl_options(
 445                                         timing_params[i].all_DIMMs_registered,
 446                                         &pinfo->memctl_opts[i],
 447                                         pinfo->dimm_params[i], i);
 448                 }
 449         case STEP_ASSIGN_ADDRESSES:
 450                 /* STEP 5:  Assign addresses to chip selects */
 451                 check_interleaving_options(pinfo);
 452                 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
 453
 454         case STEP_COMPUTE_REGS:
 455                 /* STEP 6:  compute controller register values */
 456                 debug("FSL Memory ctrl register computation\n");
 457                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 458                         if (timing_params[i].ndimms_present == 0) {
 459                                 memset(&ddr_reg[i], 0,
 460                                         sizeof(fsl_ddr_cfg_regs_t));
 461                                 continue;
 462                         }
 463
 464                         compute_fsl_memctl_config_regs(
 465                                         &pinfo->memctl_opts[i],
 466                                         &ddr_reg[i], &timing_params[i],
 467                                         pinfo->dimm_params[i],
 468                                         dbw_capacity_adjust[i],
 469                                         size_only);
 470                 }
 471
 472         default:
 473                 break;
 474         }
 475
 476         {
 477                 /*
 478                  * Compute the amount of memory available just by
 479                  * looking for the highest valid CSn_BNDS value.
 480                  * This allows us to also experiment with using
 481                  * only CS0 when using dual-rank DIMMs.
 482                  */
 483                 unsigned int max_end = 0;
 484
 485                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 486                         for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
 487                                 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
 488                                 if (reg->cs[j].config & 0x80000000) {
 489                                         unsigned int end;
 490                                         end = reg->cs[j].bnds & 0xFFF;
 491                                         if (end > max_end) {
 492                                                 max_end = end;
 493                                         }
 494                                 }
 495                         }
 496                 }
 497
 498                 total_mem = 1 + (((unsigned long long)max_end << 24ULL)
 499                                     | 0xFFFFFFULL);
 500         }
 501
 502         return total_mem;
 503 }
 504
 505 /*
 506  * fsl_ddr_sdram() -- this is the main function to be called by
 507  *      initdram() in the board file.
 508  *
 509  * It returns amount of memory configured in bytes.
 510  */
 511 phys_size_t fsl_ddr_sdram(void)
 512 {
 513         unsigned int i;
 514         unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
 515         unsigned long long total_memory;
 516         fsl_ddr_info_t info;
 517
 518         /* Reset info structure. */
 519         memset(&info, 0, sizeof(fsl_ddr_info_t));
 520
 521         /* Compute it once normally. */
 522 #ifdef CONFIG_FSL_DDR_INTERACTIVE
 523         if (getenv("ddr_interactive"))
 524                 total_memory = fsl_ddr_interactive(&info);
 525         else
 526 #endif
 527                 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
 528
 529         /* Program configuration registers. */
 530         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 531                 debug("Programming controller %u\n", i);
 532                 if (info.common_timing_params[i].ndimms_present == 0) {
 533                         debug("No dimms present on controller %u; "
 534                                         "skipping programming\n", i);
 535                         continue;
 536                 }
 537
 538                 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
 539         }
 540
 541         /* program LAWs */
 542         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 543                 if (info.memctl_opts[i].memctl_interleaving) {
 544                         switch (info.memctl_opts[i].memctl_interleaving_mode) {
 545                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 546                         case FSL_DDR_PAGE_INTERLEAVING:
 547                         case FSL_DDR_BANK_INTERLEAVING:
 548                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 549                                 if (i == 0) {
 550                                         law_memctl = LAW_TRGT_IF_DDR_INTRLV;
 551                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 552                                                 law_memctl, i);
 553                                 } else if (i == 2) {
 554                                         law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
 555                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 556                                                 law_memctl, i);
 557                                 }
 558                                 break;
 559                         case FSL_DDR_3WAY_1KB_INTERLEAVING:
 560                         case FSL_DDR_3WAY_4KB_INTERLEAVING:
 561                         case FSL_DDR_3WAY_8KB_INTERLEAVING:
 562                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
 563                                 if (i == 0) {
 564                                         fsl_ddr_set_intl3r(info.memctl_opts[i].memctl_interleaving_mode);
 565                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 566                                                 law_memctl, i);
 567                                 }
 568                                 break;
 569                         case FSL_DDR_4WAY_1KB_INTERLEAVING:
 570                         case FSL_DDR_4WAY_4KB_INTERLEAVING:
 571                         case FSL_DDR_4WAY_8KB_INTERLEAVING:
 572                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
 573                                 if (i == 0)
 574                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 575                                                 law_memctl, i);
 576                                 /* place holder for future 4-way interleaving */
 577                                 break;
 578                         default:
 579                                 break;
 580                         }
 581                 } else {
 582                         switch (i) {
 583                         case 0:
 584                                 law_memctl = LAW_TRGT_IF_DDR_1;
 585                                 break;
 586                         case 1:
 587                                 law_memctl = LAW_TRGT_IF_DDR_2;
 588                                 break;
 589                         case 2:
 590                                 law_memctl = LAW_TRGT_IF_DDR_3;
 591                                 break;
 592                         case 3:
 593                                 law_memctl = LAW_TRGT_IF_DDR_4;
 594                                 break;
 595                         default:
 596                                 break;
 597                         }
 598                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 599                                         law_memctl, i);
 600                 }
 601         }
 602
 603         debug("total_memory by %s = %llu\n", __func__, total_memory);
 604
 605 #if !defined(CONFIG_PHYS_64BIT)
 606         /* Check for 4G or more.  Bad. */
 607         if (total_memory >= (1ull << 32)) {
 608                 printf("Detected %lld MB of memory\n", total_memory >> 20);
 609                 printf("       This U-Boot only supports < 4G of DDR\n");
 610                 printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
 611                 printf("       "); /* re-align to match init_func_ram print */
 612                 total_memory = CONFIG_MAX_MEM_MAPPED;
 613         }
 614 #endif
 615
 616         return total_memory;
 617 }
 618
 619 /*
 620  * fsl_ddr_sdram_size() - This function only returns the size of the total
 621  * memory without setting ddr control registers.
 622  */
 623 phys_size_t
 624 fsl_ddr_sdram_size(void)
 625 {
 626         fsl_ddr_info_t  info;
 627         unsigned long long total_memory = 0;
 628
 629         memset(&info, 0 , sizeof(fsl_ddr_info_t));
 630
 631         /* Compute it once normally. */
 632         total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
 633
 634         return total_memory;
 635 }