board/MAI/AmigaOneG3SE/start.txt

   1
   2         /*------------------------------------------------------*/
   3         /*              TERON Articia / SDRAM Init              */
   4         /*------------------------------------------------------*/
   5
   6 *       XD_CTL  = 0x81000000                    (0x74)
   7
   8 *       HBUS_ACC_CTL_0 &= 0xFFFFFDFF            (0x5c)
   9                        /* host bus access ctl reg 2(5e) */
  10                        /* set - CPU read from memory data one clock after data is latched */
  11
  12 *       GLOBL_INFO_0 |= 0x00004000              (0x50)
  13                       /* global info register 2 (52), AGP/PCI bus 1 arbiter is addressed in Articia S */
  14
  15         PCI_1_SB_CONFIG_0 |= 0x00000400         (0x80d0)
  16                         /* PCI1 side band config reg 2 (d2), enable read acces while write buffer not empty */
  17
  18         MEM_RAS_CTL_0 |= 0x3f000000             (0xcc)
  19                       &= 0x3fffffff
  20                       /* RAS park control reg 0(cc), park access enable is set */
  21
  22         HOST_RDBUF_CTL |= 0x10000000            (0x70)
  23                        &= 0x10ffffff
  24                       /* host read buffer control reg, enable prefetch for CPU read from DRAM control */
  25
  26         HBUS_ACC_CTL_0 |= 0x0100001f            (0x5c)
  27                        &= 0xf1ffffff
  28                       /* host bus access control register, enable CPU address bus pipe control  */
  29                       /* two outstanding requests,  *** changed to 2 from 3                             */
  30                       /* enable line merge write control for CPU write to system memory, PCI 1  */
  31                       /* and PCI 0 bus memory; enable page merge write control for write to             */
  32                       /* PCI bus 0 & bus 1 memory                                                       */
  33
  34         SRAM_CTL |= 0x00004000                  (0xc8)
  35                  &= 0xffbff7ff
  36                       /* DRAM detail timing control register 1 (ca), bit 3 set to 0     */
  37                       /* DRAM start access latency control - wait for one clock */
  38                       /* ff9f changed to ffbf                                           */
  39
  40         DIM0_TIM_CTL_0 = 0x737d737d             (0xc9)
  41                       /* DRAM timing control for dimm0 & dimm1; set wait one clock      */
  42                       /* cycle for next data access                                     */
  43
  44         DIM2_TIM_CTL_0 = 0x737d737d             (0xca)
  45                       /* DRAM timing control for dimm2 & dimm3; set wait one clock      */
  46                       /* cycle for next data access                                     */
  47
  48         DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB    (0x90)
  49                       /* set dimm0 bank0 for 128 MB     */
  50
  51         DIM0_BNK1_CTL_0 = BNK1_RAM_SIZ_128MB    (0x94)
  52                       /* set dimm0 for  bank1           */
  53
  54         DIM0_TIM_CTL_0 = 0xf3bf0000             (0xc9)
  55                       /* dimm0 timing control register; RAS - CAS latency - 4 clock             */
  56                       /* CAS access latency - 3 wait; pre-charge latency - 3 wait               */
  57                       /* pre-charge command period control - 5 clock; wait one clock            */
  58                       /* cycle for next data access; read to write access latency control       */
  59                       /* - 2 clock cycles                                                       */
  60
  61         DRAM_GBL_CTL_0 |= 0x00000100            (0xc0)
  62                        &= 0xffff01ff
  63                       /* memory global control register - support buffer sdram on bank 0        */
  64
  65         DRAM_ECC_CTL_0 |= 0x00260000            (0xc4)
  66                        &= 0xff26ffff
  67                       /* enable ECC; enable read, modify, write control */
  68
  69         DRAM_REF_CTL_0 = DRAM_REF_DATA          (0xb8)
  70                       /* set DRAM refresh parameters *** changed to 00940100    */
  71
  72         nop
  73         nop
  74         nop
  75         nop
  76         nop
  77
  78         DRAM_ECC_CTL_0 |= 0x20243280            (0xc4)
  79                       /* turn off ecc           */
  80                       /* for SDRAM bank 0       */
  81
  82         DRAM_ECC_CTL_0 |= 0x20243290            (0xc4) ?
  83                       /* for SDRAM bank 1       */
  84
  85
  86 /* Additional Stuff...*/
  87
  88         GLOBL_CTRL |= 0x20000b00                (0x54)
  89
  90         PCI_0_SB_CONFIG |= 0x04100007           (0xd0)
  91                       /* PCI 0 Side band config reg*/
  92
  93         0x8000083c |= 0x00080000
  94                       /* Disable VGA decode on PCI Bus 1 */
  95
  96
  97 /*End Additional Stuff..*/
  98
  99         /*--------------------------------------------------------------*/
 100         /*              TERON serial port initialization code           */
 101         /*--------------------------------------------------------------*/
 102
 103         0x84380080 |= 0x00030000
 104                      /* enable super IO configuration VIA chip Register 85      */
 105                      /* Enable super I/O config mode */
 106
 107         0xfe0003f0 = 0xe2
 108         bl delay1
 109
 110         0xfe0003f1 = 0x0f
 111         bl delay1
 112                     /* enable com1 & com2, parallel port disabled */
 113
 114         0xfe0003f0 = 0xe7
 115         bl delay1
 116                     /* let's make com1 base as 0x3f8 */
 117
 118         0xfe0003f1 = 0xfe
 119         bl delay1
 120
 121         0xfe0003f0 = 0xe8
 122         bl delay1
 123                     /* let's make com2 base as 0x2f8 */
 124
 125         0xfe0003f1 = 0xbe
 126
 127         0x84380080 &= 0xfffdffff
 128                     /* closing super IO configuration VIA chip Register 85   */
 129
 130
 131 /* -------------------------------*/
 132
 133         0xfe0003fb = 0x83
 134         bl delay1
 135                    /*latch enable word length -8 bit */         /* set mslab bit        */
 136         0xfe0003f8 = 0x0c
 137         bl delay1
 138                    /* set baud rate lsb for 9600 baud   */
 139         0xfe0003f9 = 0x0
 140         bl delay1
 141                    /* set baud rate msb for 9600 baud   */
 142         0xfe0003fb  = 0x03
 143         bl delay1
 144                       /* reset mslab    */
 145
 146         /*--------------------------------------------------------------*/
 147         /*              END TERON Serial Port Initialization Code       */
 148         /*--------------------------------------------------------------*/
 149
 150
 151         /*--------------------------------------------------------------*/
 152         /*      END TERON Articia / SDRAM Initialization code           */
 153         /*--------------------------------------------------------------*/
 154
 155 Proposed from Documentation:
 156
 157 write dmem 0xfec00cf8 0x50000080
 158 write dmem 0xfee00cfc 0xc0305411
 159
 160       Writes to index 0x50-0x53.
 161       0x50: Global Information Register 0
 162             0xC0 = Little Endian CPU, Sequential order Burst
 163       0x51: Global Information Register 1
 164             Read only, 0x30 = Provides PowerPC and X86 support
 165       0x52: Global Information Register 2
 166             0x05 = 64/128 bit CPU bus support
 167       0x53: Global Information Register 3
 168             0x80 = PCI Bus 0 grant active time is 1 clock after REQ# deasserted
 169
 170 write dmem 0xfec00cf8 0x5c000080
 171 write dmem 0xfee00cfc 0xb300011F
 172
 173 write dmem 0xfec00cf8 0xc8000080
 174 write dmem 0xfee00cfc 0x0020f100
 175
 176 write dmem 0xfec00cf8 0x90000080
 177 write dmem 0xfee00cfc 0x007fe700
 178
 179 write dmem 0xfec00cf8 0x9400080
 180 write dmem 0xfee00cfc 0x007fe700
 181
 182 write dmem 0xfec00cf8 0xb0000080
 183 write dmem 0xfee00cfc 0x737d737d
 184
 185 write dmem 0xfec00cf8 0xb4000080
 186 write dmem 0xfee00cfc 0x737d737d
 187
 188 write dmem 0xfec00cf8 0xc0000080
 189 write dmem 0xfee00cfc 0x40005500
 190
 191 write dmem 0xfec00cf8 0xb8000080
 192 write dmem 0xfee00cfc 0x00940100
 193
 194 write dmem 0xfec00cf8 0xc4000080
 195 write dmem 0xfee00cfc 0x00003280
 196
 197 write dmem 0xfec00cf8 0xc4000080
 198 write dmem 0xfee00cfc 0x00003290