board/amcc/yellowstone/yellowstone.c

   1 /*
   2  *
   3  * See file CREDITS for list of people who contributed to this
   4  * project.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <common.h>
  23 #include <ppc4xx.h>
  24 #include <asm/processor.h>
  25 #include <spd_sdram.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
  30
  31 int board_early_init_f(void)
  32 {
  33         register uint reg;
  34
  35         /*--------------------------------------------------------------------
  36          * Setup the external bus controller/chip selects
  37          *-------------------------------------------------------------------*/
  38         mtdcr(ebccfga, xbcfg);
  39         reg = mfdcr(ebccfgd);
  40         mtdcr(ebccfgd, reg | 0x04000000);       /* Set ATC */
  41
  42         /*--------------------------------------------------------------------
  43          * Setup the GPIO pins
  44          *-------------------------------------------------------------------*/
  45         /*CPLD cs */
  46         /*setup Address lines for flash size 64Meg. */
  47         out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
  48         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
  49         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
  50
  51         /*setup emac */
  52         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  53         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  54         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  55         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  56         out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  57
  58         /*UART1 */
  59         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
  60         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
  61         out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
  62
  63         /* external interrupts IRQ0...3 */
  64         out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
  65         out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
  66         out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
  67
  68 #if 0 /* test-only */
  69         /*setup USB 2.0 */
  70         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
  71         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
  72         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
  73         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
  74         out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
  75 #endif
  76
  77         /*--------------------------------------------------------------------
  78          * Setup the interrupt controller polarities, triggers, etc.
  79          *-------------------------------------------------------------------*/
  80         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  81         mtdcr(uic0er, 0x00000000);      /* disable all */
  82         mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
  83         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
  84         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
  85         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
  86         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  87
  88         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  89         mtdcr(uic1er, 0x00000000);      /* disable all */
  90         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
  91         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
  92         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
  93         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
  94         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  95
  96         /*--------------------------------------------------------------------
  97          * Setup other serial configuration
  98          *-------------------------------------------------------------------*/
  99         mfsdr(sdr_pci0, reg);
 100         mtsdr(sdr_pci0, 0x80000000 | reg);      /* PCI arbiter enabled */
 101         mtsdr(sdr_pfc0, 0x00003e00);    /* Pin function */
 102         mtsdr(sdr_pfc1, 0x00048000);    /* Pin function: UART0 has 4 pins */
 103
 104         /*clear tmrclk divisor */
 105         *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
 106
 107         /*enable ethernet */
 108         *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
 109
 110 #if 0 /* test-only */
 111         /*enable usb 1.1 fs device and remove usb 2.0 reset */
 112         *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
 113 #endif
 114
 115         /*get rid of flash write protect */
 116         *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
 117
 118         return 0;
 119 }
 120
 121 int misc_init_r (void)
 122 {
 123         uint pbcr;
 124         int size_val = 0;
 125
 126         /* Re-do sizing to get full correct info */
 127         mtdcr(ebccfga, pb0cr);
 128         pbcr = mfdcr(ebccfgd);
 129         switch (gd->bd->bi_flashsize) {
 130         case 1 << 20:
 131                 size_val = 0;
 132                 break;
 133         case 2 << 20:
 134                 size_val = 1;
 135                 break;
 136         case 4 << 20:
 137                 size_val = 2;
 138                 break;
 139         case 8 << 20:
 140                 size_val = 3;
 141                 break;
 142         case 16 << 20:
 143                 size_val = 4;
 144                 break;
 145         case 32 << 20:
 146                 size_val = 5;
 147                 break;
 148         case 64 << 20:
 149                 size_val = 6;
 150                 break;
 151         case 128 << 20:
 152                 size_val = 7;
 153                 break;
 154         }
 155         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 156         mtdcr(ebccfga, pb0cr);
 157         mtdcr(ebccfgd, pbcr);
 158
 159         /* adjust flash start and offset */
 160         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 161         gd->bd->bi_flashoffset = 0;
 162
 163         /* Monitor protection ON by default */
 164         (void)flash_protect(FLAG_PROTECT_SET,
 165                             -CFG_MONITOR_LEN,
 166                             0xffffffff,
 167                             &flash_info[0]);
 168
 169         return 0;
 170 }
 171
 172 int checkboard(void)
 173 {
 174         char *s = getenv("serial#");
 175         u8 rev;
 176         u8 val;
 177
 178         printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
 179
 180         rev = *(u8 *)(CFG_CPLD + 0);
 181         val = *(u8 *)(CFG_CPLD + 5) & 0x01;
 182         printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 183
 184         if (s != NULL) {
 185                 puts(", serial# ");
 186                 puts(s);
 187         }
 188         putc('\n');
 189
 190         return (0);
 191 }
 192
 193 /*************************************************************************
 194  *  sdram_init -- doesn't use serial presence detect.
 195  *
 196  *  Assumes:    256 MB, ECC, non-registered
 197  *              PLB @ 133 MHz
 198  *
 199  ************************************************************************/
 200 #define NUM_TRIES 64
 201 #define NUM_READS 10
 202
 203 void sdram_tr1_set(int ram_address, int* tr1_value)
 204 {
 205         int i;
 206         int j, k;
 207         volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
 208         int first_good = -1, last_bad = 0x1ff;
 209
 210         unsigned long test[NUM_TRIES] = {
 211                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 212                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 213                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 214                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 215                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 216                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 217                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 218                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 219                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 220                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 221                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 222                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 223                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 224                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 225                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 226                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
 227
 228         /* go through all possible SDRAM0_TR1[RDCT] values */
 229         for (i=0; i<=0x1ff; i++) {
 230                 /* set the current value for TR1 */
 231                 mtsdram(mem_tr1, (0x80800800 | i));
 232
 233                 /* write values */
 234                 for (j=0; j<NUM_TRIES; j++) {
 235                         ram_pointer[j] = test[j];
 236
 237                         /* clear any cache at ram location */
 238                         __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 239                 }
 240
 241                 /* read values back */
 242                 for (j=0; j<NUM_TRIES; j++) {
 243                         for (k=0; k<NUM_READS; k++) {
 244                                 /* clear any cache at ram location */
 245                                 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 246
 247                                 if (ram_pointer[j] != test[j])
 248                                         break;
 249                         }
 250
 251                         /* read error */
 252                         if (k != NUM_READS) {
 253                                 break;
 254                         }
 255                 }
 256
 257                 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
 258                 if (j == NUM_TRIES) {
 259                         if (first_good == -1)
 260                                 first_good = i;         /* found beginning of window */
 261                 } else { /* bad read */
 262                         /* if we have not had a good read then don't care */
 263                         if(first_good != -1) {
 264                                 /* first failure after a good read */
 265                                 last_bad = i-1;
 266                                 break;
 267                         }
 268                 }
 269         }
 270
 271         /* return the current value for TR1 */
 272         *tr1_value = (first_good + last_bad) / 2;
 273 }
 274
 275 void sdram_init(void)
 276 {
 277         register uint reg;
 278         int tr1_bank1, tr1_bank2;
 279
 280         /*--------------------------------------------------------------------
 281          * Setup some default
 282          *------------------------------------------------------------------*/
 283         mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default)             */
 284         mtsdram(mem_slio, 0x00000000);  /* rdre=0 wrre=0 rarw=0         */
 285         mtsdram(mem_devopt, 0x00000000);        /* dll=0 ds=0 (normal)          */
 286         mtsdram(mem_clktr, 0x40000000); /* ?? */
 287         mtsdram(mem_wddctr, 0x40000000);        /* ?? */
 288
 289         /*clear this first, if the DDR is enabled by a debugger
 290           then you can not make changes. */
 291         mtsdram(mem_cfg0, 0x00000000);  /* Disable EEC */
 292
 293         /*--------------------------------------------------------------------
 294          * Setup for board-specific specific mem
 295          *------------------------------------------------------------------*/
 296         /*
 297          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 298          */
 299         mtsdram(mem_b0cr, 0x000a4001);  /* SDBA=0x000 128MB, Mode 3, enabled */
 300         mtsdram(mem_b1cr, 0x080a4001);  /* SDBA=0x080 128MB, Mode 3, enabled */
 301
 302         mtsdram(mem_tr0, 0x410a4012);   /* ?? */
 303         mtsdram(mem_rtr, 0x04080000);   /* ?? */
 304         mtsdram(mem_cfg1, 0x00000000);  /* Self-refresh exit, disable PM    */
 305         mtsdram(mem_cfg0, 0x30000000);  /* Disable EEC */
 306         udelay(400);            /* Delay 200 usecs (min)            */
 307
 308         /*--------------------------------------------------------------------
 309          * Enable the controller, then wait for DCEN to complete
 310          *------------------------------------------------------------------*/
 311         mtsdram(mem_cfg0, 0x80000000);  /* Enable */
 312
 313         for (;;) {
 314                 mfsdram(mem_mcsts, reg);
 315                 if (reg & 0x80000000)
 316                         break;
 317         }
 318
 319         sdram_tr1_set(0x00000000, &tr1_bank1);
 320         sdram_tr1_set(0x08000000, &tr1_bank2);
 321         mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
 322 }
 323
 324 /*************************************************************************
 325  *  long int initdram
 326  *
 327  ************************************************************************/
 328 long int initdram(int board)
 329 {
 330         sdram_init();
 331         return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);     /* return bytes */
 332 }
 333
 334 #if defined(CFG_DRAM_TEST)
 335 int testdram(void)
 336 {
 337         unsigned long *mem = (unsigned long *)0;
 338         const unsigned long kend = (1024 / sizeof(unsigned long));
 339         unsigned long k, n;
 340
 341         mtmsr(0);
 342
 343         for (k = 0; k < CFG_KBYTES_SDRAM;
 344              ++k, mem += (1024 / sizeof(unsigned long))) {
 345                 if ((k & 1023) == 0) {
 346                         printf("%3d MB\r", k / 1024);
 347                 }
 348
 349                 memset(mem, 0xaaaaaaaa, 1024);
 350                 for (n = 0; n < kend; ++n) {
 351                         if (mem[n] != 0xaaaaaaaa) {
 352                                 printf("SDRAM test fails at: %08x\n",
 353                                        (uint) & mem[n]);
 354                                 return 1;
 355                         }
 356                 }
 357
 358                 memset(mem, 0x55555555, 1024);
 359                 for (n = 0; n < kend; ++n) {
 360                         if (mem[n] != 0x55555555) {
 361                                 printf("SDRAM test fails at: %08x\n",
 362                                        (uint) & mem[n]);
 363                                 return 1;
 364                         }
 365                 }
 366         }
 367         printf("SDRAM test passes\n");
 368         return 0;
 369 }
 370 #endif
 371
 372 /*************************************************************************
 373  *  pci_pre_init
 374  *
 375  *  This routine is called just prior to registering the hose and gives
 376  *  the board the opportunity to check things. Returning a value of zero
 377  *  indicates that things are bad & PCI initialization should be aborted.
 378  *
 379  *      Different boards may wish to customize the pci controller structure
 380  *      (add regions, override default access routines, etc) or perform
 381  *      certain pre-initialization actions.
 382  *
 383  ************************************************************************/
 384 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 385 int pci_pre_init(struct pci_controller *hose)
 386 {
 387         unsigned long addr;
 388
 389         /*-------------------------------------------------------------------------+
 390           | Set priority for all PLB3 devices to 0.
 391           | Set PLB3 arbiter to fair mode.
 392           +-------------------------------------------------------------------------*/
 393         mfsdr(sdr_amp1, addr);
 394         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 395         addr = mfdcr(plb3_acr);
 396         mtdcr(plb3_acr, addr | 0x80000000);
 397
 398         /*-------------------------------------------------------------------------+
 399           | Set priority for all PLB4 devices to 0.
 400           +-------------------------------------------------------------------------*/
 401         mfsdr(sdr_amp0, addr);
 402         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 403         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 404         mtdcr(plb4_acr, addr);
 405
 406         /*-------------------------------------------------------------------------+
 407           | Set Nebula PLB4 arbiter to fair mode.
 408           +-------------------------------------------------------------------------*/
 409         /* Segment0 */
 410         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 411         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 412         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 413         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 414         mtdcr(plb0_acr, addr);
 415
 416         /* Segment1 */
 417         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 418         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 419         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 420         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 421         mtdcr(plb1_acr, addr);
 422
 423         return 1;
 424 }
 425 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 426
 427 /*************************************************************************
 428  *  pci_target_init
 429  *
 430  *      The bootstrap configuration provides default settings for the pci
 431  *      inbound map (PIM). But the bootstrap config choices are limited and
 432  *      may not be sufficient for a given board.
 433  *
 434  ************************************************************************/
 435 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 436 void pci_target_init(struct pci_controller *hose)
 437 {
 438         /*--------------------------------------------------------------------------+
 439          * Set up Direct MMIO registers
 440          *--------------------------------------------------------------------------*/
 441         /*--------------------------------------------------------------------------+
 442           | PowerPC440 EP PCI Master configuration.
 443           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 444           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 445           |   Use byte reversed out routines to handle endianess.
 446           | Make this region non-prefetchable.
 447           +--------------------------------------------------------------------------*/
 448         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 449         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 450         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 451         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 452         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 453
 454         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 455         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 456         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 457         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 458         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 459
 460         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 461         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 462         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 463         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 464
 465         /*--------------------------------------------------------------------------+
 466          * Set up Configuration registers
 467          *--------------------------------------------------------------------------*/
 468
 469         /* Program the board's subsystem id/vendor id */
 470         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 471                               CFG_PCI_SUBSYS_VENDORID);
 472         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 473
 474         /* Configure command register as bus master */
 475         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 476
 477         /* 240nS PCI clock */
 478         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 479
 480         /* No error reporting */
 481         pci_write_config_word(0, PCI_ERREN, 0);
 482
 483         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 484
 485 }
 486 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 487
 488 /*************************************************************************
 489  *  pci_master_init
 490  *
 491  ************************************************************************/
 492 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 493 void pci_master_init(struct pci_controller *hose)
 494 {
 495         unsigned short temp_short;
 496
 497         /*--------------------------------------------------------------------------+
 498           | Write the PowerPC440 EP PCI Configuration regs.
 499           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 500           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 501           +--------------------------------------------------------------------------*/
 502         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 503         pci_write_config_word(0, PCI_COMMAND,
 504                               temp_short | PCI_COMMAND_MASTER |
 505                               PCI_COMMAND_MEMORY);
 506 }
 507 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 508
 509 /*************************************************************************
 510  *  is_pci_host
 511  *
 512  *      This routine is called to determine if a pci scan should be
 513  *      performed. With various hardware environments (especially cPCI and
 514  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 515  *      bit in the strap register, or generic host/adapter assumptions.
 516  *
 517  *      Rather than hard-code a bad assumption in the general 440 code, the
 518  *      440 pci code requires the board to decide at runtime.
 519  *
 520  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 521  *
 522  *
 523  ************************************************************************/
 524 #if defined(CONFIG_PCI)
 525 int is_pci_host(struct pci_controller *hose)
 526 {
 527         /* Bamboo is always configured as host. */
 528         return (1);
 529 }
 530 #endif                          /* defined(CONFIG_PCI) */
 531
 532 /*************************************************************************
 533  *  hw_watchdog_reset
 534  *
 535  *      This routine is called to reset (keep alive) the watchdog timer
 536  *
 537  ************************************************************************/
 538 #if defined(CONFIG_HW_WATCHDOG)
 539 void hw_watchdog_reset(void)
 540 {
 541
 542 }
 543 #endif
 544
 545 void board_reset(void)
 546 {
 547         /* give reset to BCSR */
 548         *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09;
 549 }