board/amcc/yucca/yucca.h

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __YUCCA_H_
  25 #define __YUCCA_H_
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 /*----------------------------------------------------------------------------+
  32 | Defines
  33 +----------------------------------------------------------------------------*/
  34
  35 #define TMR_FREQ_EXT            25000000
  36 #define BOARD_UART_CLOCK        11059200
  37
  38 #define BOARD_OPTION_SELECTED           1
  39 #define BOARD_OPTION_NOT_SELECTED       0
  40
  41 #define ENGINEERING_CLOCK_CHECKING "clk_chk"
  42 #define ENGINEERING_EXTERNAL_CLOCK "ext_clk"
  43
  44 #define ENGINEERING_CLOCK_CHECKING_DATA 1
  45 #define ENGINEERING_EXTERNAL_CLOCK_DATA 2
  46
  47 /* ethernet definition */
  48 #define MAX_ENETMODE_PARM       3
  49 #define ENETMODE_NEG            0
  50 #define ENETMODE_SPEED          1
  51 #define ENETMODE_DUPLEX         2
  52
  53 #define ENETMODE_AUTONEG        0
  54 #define ENETMODE_NO_AUTONEG     1
  55 #define ENETMODE_10             2
  56 #define ENETMODE_100            3
  57 #define ENETMODE_1000           4
  58 #define ENETMODE_HALF           5
  59 #define ENETMODE_FULL           6
  60
  61 #define NUM_TLB_ENTRIES          64
  62
  63 /*----------------------------------------------------------------------------+
  64 | TLB specific defines.
  65 +----------------------------------------------------------------------------*/
  66 #define TLB_256MB_ALIGN_MASK    0xF0000000
  67 #define TLB_16MB_ALIGN_MASK     0xFF000000
  68 #define TLB_1MB_ALIGN_MASK      0xFFF00000
  69 #define TLB_256KB_ALIGN_MASK    0xFFFC0000
  70 #define TLB_64KB_ALIGN_MASK     0xFFFF0000
  71 #define TLB_16KB_ALIGN_MASK     0xFFFFC000
  72 #define TLB_4KB_ALIGN_MASK      0xFFFFF000
  73 #define TLB_1KB_ALIGN_MASK      0xFFFFFC00
  74 #define TLB_256MB_SIZE          0x10000000
  75 #define TLB_16MB_SIZE           0x01000000
  76 #define TLB_1MB_SIZE            0x00100000
  77 #define TLB_256KB_SIZE          0x00040000
  78 #define TLB_64KB_SIZE           0x00010000
  79 #define TLB_16KB_SIZE           0x00004000
  80 #define TLB_4KB_SIZE            0x00001000
  81 #define TLB_1KB_SIZE            0x00000400
  82
  83 #define TLB_WORD0_EPN_MASK      0xFFFFFC00
  84 #define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
  85 #define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
  86 #define TLB_WORD0_V_MASK        0x00000200
  87 #define TLB_WORD0_V_ENABLE      0x00000200
  88 #define TLB_WORD0_V_DISABLE     0x00000000
  89 #define TLB_WORD0_TS_MASK       0x00000100
  90 #define TLB_WORD0_TS_1          0x00000100
  91 #define TLB_WORD0_TS_0          0x00000000
  92 #define TLB_WORD0_SIZE_MASK     0x000000F0
  93 #define TLB_WORD0_SIZE_1KB      0x00000000
  94 #define TLB_WORD0_SIZE_4KB      0x00000010
  95 #define TLB_WORD0_SIZE_16KB     0x00000020
  96 #define TLB_WORD0_SIZE_64KB     0x00000030
  97 #define TLB_WORD0_SIZE_256KB    0x00000040
  98 #define TLB_WORD0_SIZE_1MB      0x00000050
  99 #define TLB_WORD0_SIZE_16MB     0x00000070
 100 #define TLB_WORD0_SIZE_256MB    0x00000090
 101 #define TLB_WORD0_TPAR_MASK     0x0000000F
 102 #define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
 103 #define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
 104
 105 #define TLB_WORD1_RPN_MASK      0xFFFFFC00
 106 #define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
 107 #define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
 108 #define TLB_WORD1_PAR1_MASK     0x00000300
 109 #define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
 110 #define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
 111 #define TLB_WORD1_PAR1_0        0x00000000
 112 #define TLB_WORD1_PAR1_1        0x00000100
 113 #define TLB_WORD1_PAR1_2        0x00000200
 114 #define TLB_WORD1_PAR1_3        0x00000300
 115 #define TLB_WORD1_ERPN_MASK     0x0000000F
 116 #define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
 117 #define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
 118
 119 #define TLB_WORD2_PAR2_MASK     0xC0000000
 120 #define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
 121 #define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
 122 #define TLB_WORD2_PAR2_0        0x00000000
 123 #define TLB_WORD2_PAR2_1        0x40000000
 124 #define TLB_WORD2_PAR2_2        0x80000000
 125 #define TLB_WORD2_PAR2_3        0xC0000000
 126 #define TLB_WORD2_U0_MASK       0x00008000
 127 #define TLB_WORD2_U0_ENABLE     0x00008000
 128 #define TLB_WORD2_U0_DISABLE    0x00000000
 129 #define TLB_WORD2_U1_MASK       0x00004000
 130 #define TLB_WORD2_U1_ENABLE     0x00004000
 131 #define TLB_WORD2_U1_DISABLE    0x00000000
 132 #define TLB_WORD2_U2_MASK       0x00002000
 133 #define TLB_WORD2_U2_ENABLE     0x00002000
 134 #define TLB_WORD2_U2_DISABLE    0x00000000
 135 #define TLB_WORD2_U3_MASK       0x00001000
 136 #define TLB_WORD2_U3_ENABLE     0x00001000
 137 #define TLB_WORD2_U3_DISABLE    0x00000000
 138 #define TLB_WORD2_W_MASK        0x00000800
 139 #define TLB_WORD2_W_ENABLE      0x00000800
 140 #define TLB_WORD2_W_DISABLE     0x00000000
 141 #define TLB_WORD2_I_MASK        0x00000400
 142 #define TLB_WORD2_I_ENABLE      0x00000400
 143 #define TLB_WORD2_I_DISABLE     0x00000000
 144 #define TLB_WORD2_M_MASK        0x00000200
 145 #define TLB_WORD2_M_ENABLE      0x00000200
 146 #define TLB_WORD2_M_DISABLE     0x00000000
 147 #define TLB_WORD2_G_MASK        0x00000100
 148 #define TLB_WORD2_G_ENABLE      0x00000100
 149 #define TLB_WORD2_G_DISABLE     0x00000000
 150 #define TLB_WORD2_E_MASK        0x00000080
 151 #define TLB_WORD2_E_ENABLE      0x00000080
 152 #define TLB_WORD2_E_DISABLE     0x00000000
 153 #define TLB_WORD2_UX_MASK       0x00000020
 154 #define TLB_WORD2_UX_ENABLE     0x00000020
 155 #define TLB_WORD2_UX_DISABLE    0x00000000
 156 #define TLB_WORD2_UW_MASK       0x00000010
 157 #define TLB_WORD2_UW_ENABLE     0x00000010
 158 #define TLB_WORD2_UW_DISABLE    0x00000000
 159 #define TLB_WORD2_UR_MASK       0x00000008
 160 #define TLB_WORD2_UR_ENABLE     0x00000008
 161 #define TLB_WORD2_UR_DISABLE    0x00000000
 162 #define TLB_WORD2_SX_MASK       0x00000004
 163 #define TLB_WORD2_SX_ENABLE     0x00000004
 164 #define TLB_WORD2_SX_DISABLE    0x00000000
 165 #define TLB_WORD2_SW_MASK       0x00000002
 166 #define TLB_WORD2_SW_ENABLE     0x00000002
 167 #define TLB_WORD2_SW_DISABLE    0x00000000
 168 #define TLB_WORD2_SR_MASK       0x00000001
 169 #define TLB_WORD2_SR_ENABLE     0x00000001
 170 #define TLB_WORD2_SR_DISABLE    0x00000000
 171
 172 /*----------------------------------------------------------------------------+
 173 | Board specific defines.
 174 +----------------------------------------------------------------------------*/
 175 #define NONCACHE_MEMORY_SIZE     (64*1024)
 176 #define NONCACHE_AREA0_ENDOFFSET (64*1024)
 177 #define NONCACHE_AREA1_ENDOFFSET (32*1024)
 178
 179 #define FLASH_SECTORSIZE        0x00010000
 180
 181 /* SDRAM MICRON */
 182 #define SDRAM_MICRON            0x2C
 183
 184 #define SDRAM_TRUE              1
 185 #define SDRAM_FALSE             0
 186 #define SDRAM_DDR1              1
 187 #define SDRAM_DDR2              2
 188 #define SDRAM_NONE              0
 189 #define MAXDIMMS                2               /* Changes le 12/01/05 pour 1.6 */
 190 #define MAXRANKS                4               /* Changes le 12/01/05 pour 1.6 */
 191 #define MAXBANKSPERDIMM         2
 192 #define MAXRANKSPERDIMM         2
 193 #define MAXBXCF                 4               /* Changes le 12/01/05 pour 1.6 */
 194 #define MAXSDRAMMEMORY          0xFFFFFFFF      /* 4GB */
 195 #define ERROR_STR_LENGTH        256
 196 #define MAX_SPD_BYTES           256             /* Max number of bytes on the DIMM's SPD EEPROM */
 197
 198 /*----------------------------------------------------------------------------+
 199 | SDR Configuration registers
 200 +----------------------------------------------------------------------------*/
 201 /* Serial Device Strap Reg 0 */
 202 #define sdr_pstrp0      0x0040
 203
 204 #define SDR0_SDSTP1_EBC_ROM_BS_MASK     0x00000080 /* EBC Boot bus width Mask */
 205 #define SDR0_SDSTP1_EBC_ROM_BS_16BIT    0x00000080 /* EBC 16 Bits */
 206 #define SDR0_SDSTP1_EBC_ROM_BS_8BIT     0x00000000 /* EBC  8 Bits */
 207
 208 #define SDR0_SDSTP1_BOOT_SEL_MASK       0x00080000 /* Boot device Selection Mask */
 209 #define SDR0_SDSTP1_BOOT_SEL_EBC        0x00000000 /* EBC */
 210 #define SDR0_SDSTP1_BOOT_SEL_PCI        0x00080000 /* PCI */
 211
 212 #define SDR0_SDSTP1_EBC_SIZE_MASK       0x00000060 /* Boot rom size Mask */
 213 #define SDR0_SDSTP1_BOOT_SIZE_16MB      0x00000060 /* 16 MB */
 214 #define SDR0_SDSTP1_BOOT_SIZE_8MB       0x00000040 /*  8 MB */
 215 #define SDR0_SDSTP1_BOOT_SIZE_4MB       0x00000020 /*  4 MB */
 216 #define SDR0_SDSTP1_BOOT_SIZE_2MB       0x00000000 /*  2 MB */
 217
 218 /* Serial Device Enabled - Addr = 0xA8 */
 219 #define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
 220 /* Serial Device Enabled - Addr = 0xA4 */
 221 #define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
 222
 223 /* Pin Straps Reg */
 224 #define SDR0_PSTRP0                     0x0040
 225 #define SDR0_PSTRP0_BOOTSTRAP_MASK      0xE0000000  /* Strap Bits */
 226
 227 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000  /* Default strap settings 0 */
 228 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000  /* Default strap settings 1 */
 229 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000  /* Default strap settings 2 */
 230 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000  /* Default strap settings 3 */
 231 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000  /* Default strap settings 4 */
 232 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000  /* Default strap settings 5 */
 233 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000  /* Default strap settings 6 */
 234 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000  /* Default strap settings 7 */
 235
 236 /* fpgareg - defines are in include/config/YUCCA.h */
 237
 238 #define SDR0_CUST0_ENET3_MASK           0x00000080
 239 #define SDR0_CUST0_ENET3_COPPER         0x00000000
 240 #define SDR0_CUST0_ENET3_FIBER          0x00000080
 241 #define SDR0_CUST0_RGMII3_MASK          0x00000070
 242 #define SDR0_CUST0_RGMII3_ENCODE(n)     ((((unsigned long)(n))&0x7)<<4)
 243 #define SDR0_CUST0_RGMII3_DECODE(n)     ((((unsigned long)(n))>>4)&0x07)
 244 #define SDR0_CUST0_RGMII3_DISAB         0x00000000
 245 #define SDR0_CUST0_RGMII3_RTBI          0x00000040
 246 #define SDR0_CUST0_RGMII3_RGMII         0x00000050
 247 #define SDR0_CUST0_RGMII3_TBI           0x00000060
 248 #define SDR0_CUST0_RGMII3_GMII          0x00000070
 249 #define SDR0_CUST0_ENET2_MASK           0x00000008
 250 #define SDR0_CUST0_ENET2_COPPER         0x00000000
 251 #define SDR0_CUST0_ENET2_FIBER          0x00000008
 252 #define SDR0_CUST0_RGMII2_MASK          0x00000007
 253 #define SDR0_CUST0_RGMII2_ENCODE(n)     ((((unsigned long)(n))&0x7)<<0)
 254 #define SDR0_CUST0_RGMII2_DECODE(n)     ((((unsigned long)(n))>>0)&0x07)
 255 #define SDR0_CUST0_RGMII2_DISAB         0x00000000
 256 #define SDR0_CUST0_RGMII2_RTBI          0x00000004
 257 #define SDR0_CUST0_RGMII2_RGMII         0x00000005
 258 #define SDR0_CUST0_RGMII2_TBI           0x00000006
 259 #define SDR0_CUST0_RGMII2_GMII          0x00000007
 260
 261 #define ONE_MILLION                     1000000
 262 #define ONE_BILLION                     1000000000
 263
 264 /*----------------------------------------------------------------------------+
 265 |                               X
 266 |                              XX
 267 | XX  XXX   XXXXX   XX XXX    XXXXX
 268 | XX  XX        X    XXX XX    XX
 269 | XX  XX   XXXXXX    XX        XX
 270 | XX  XX   X   XX    XX        XX XX
 271 |  XXX XX  XXXXX X  XXXX        XXX
 272 +----------------------------------------------------------------------------*/
 273 /*----------------------------------------------------------------------------+
 274 | Declare Configuration values
 275 +----------------------------------------------------------------------------*/
 276
 277 typedef enum config_selection {
 278         CONFIG_NOT_SELECTED,
 279         CONFIG_SELECTED
 280 } config_selection_t;
 281
 282 typedef enum config_list {
 283         UART2_IN_SERVICE_MODE,
 284         CPU_TRACE_MODE,
 285         UART1_CTS_RTS,
 286         CONFIG_NB
 287 } config_list_t;
 288
 289 #define MAX_CONFIG_SELECT_NB                    3
 290
 291 #define BOARD_INFO_UART2_IN_SERVICE_MODE        1
 292 #define BOARD_INFO_CPU_TRACE_MODE               2
 293 #define BOARD_INFO_UART1_CTS_RTS_MODE           4
 294
 295 void force_bup_config_selection(config_selection_t *confgi_select_P);
 296 void update_config_selection_table(config_selection_t *config_select_P);
 297 void display_config_selection(config_selection_t *config_select_P);
 298
 299 /*----------------------------------------------------------------------------+
 300 |                     XX
 301 |
 302 |   XXXX    XX XXX   XXX     XXXX
 303 |  XX        XX  XX   XX    XX  XX
 304 |  XX  XXX   XX  XX   XX    XX  XX
 305 |  XX  XX    XXXXX    XX    XX  XX
 306 |   XXXX     XX      XXXX    XXXX
 307 |           XXXX
 308 |
 309 |
 310 |
 311 | +------------------------------------------------------------------+
 312 | |  GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O |
 313 | +----------------------+------------------+-----+------------+-----+
 314 | |                      |                  |     |            |     |
 315 | | GPIO0_0              | PCIX0REQ2_N      | I/O |  TRCCLK    |     |
 316 | | GPIO0_1              | PCIX0REQ3_N      | I/O |  TRCBS0    |     |
 317 | | GPIO0_2              | PCIX0GNT2_N      | I/O |  TRCBS1    |     |
 318 | | GPIO0_3              | PCIX0GNT3_N      | I/O |  TRCBS2    |     |
 319 | | GPIO0_4              | PCIX1REQ2_N      | I/O |  TRCES0    |     |
 320 | | GPIO0_5              | PCIX1REQ3_N      | I/O |  TRCES1    |     |
 321 | | GPIO0_6              | PCIX1GNT2_N      | I/O |  TRCES2    | NA  |
 322 | | GPIO0_7              | PCIX1GNT3_N      | I/O |  TRCES3    | NA  |
 323 | | GPIO0_8              | PERREADY         |  I  |  TRCES4    | NA  |
 324 | | GPIO0_9              | PERCS1_N         |  O  |  TRCTS0    | NA  |
 325 | | GPIO0_10             | PERCS2_N         |  O  |  TRCTS1    | NA  |
 326 | | GPIO0_11             | IRQ0             |  I  |  TRCTS2    | NA  |
 327 | | GPIO0_12             | IRQ1             |  I  |  TRCTS3    | NA  |
 328 | | GPIO0_13             | IRQ2             |  I  |  TRCTS4    | NA  |
 329 | | GPIO0_14             | IRQ3             |  I  |  TRCTS5    | NA  |
 330 | | GPIO0_15             | IRQ4             |  I  |  TRCTS6    | NA  |
 331 | | GPIO0_16             | IRQ5             |  I  |  UART2RX   |  I  |
 332 | | GPIO0_17             | PERBE0_N         |  O  |  UART2TX   |  O  |
 333 | | GPIO0_18             | PCI0GNT0_N       | I/O |  NA        | NA  |
 334 | | GPIO0_19             | PCI0GNT1_N       | I/O |  NA        | NA  |
 335 | | GPIO0_20             | PCI0REQ0_N       | I/O |  NA        | NA  |
 336 | | GPIO0_21             | PCI0REQ1_N       | I/O |  NA        | NA  |
 337 | | GPIO0_22             | PCI1GNT0_N       | I/O |  NA        | NA  |
 338 | | GPIO0_23             | PCI1GNT1_N       | I/O |  NA        | NA  |
 339 | | GPIO0_24             | PCI1REQ0_N       | I/O |  NA        | NA  |
 340 | | GPIO0_25             | PCI1REQ1_N       | I/O |  NA        | NA  |
 341 | | GPIO0_26             | PCI2GNT0_N       | I/O |  NA        | NA  |
 342 | | GPIO0_27             | PCI2GNT1_N       | I/O |  NA        | NA  |
 343 | | GPIO0_28             | PCI2REQ0_N       | I/O |  NA        | NA  |
 344 | | GPIO0_29             | PCI2REQ1_N       | I/O |  NA        | NA  |
 345 | | GPIO0_30             | UART1RX          |  I  |  NA        | NA  |
 346 | | GPIO0_31             | UART1TX          |  O  |  NA        | NA  |
 347 | |                      |                  |     |            |     |
 348 | +----------------------+------------------+-----+------------+-----+
 349 |
 350 +----------------------------------------------------------------------------*/
 351
 352 unsigned long auto_calc_speed(void);
 353 /*----------------------------------------------------------------------------+
 354 | Prototypes
 355 +----------------------------------------------------------------------------*/
 356 void print_evb440spe_info(void);
 357
 358 int onboard_pci_arbiter_selected(int core_pci);
 359
 360 #ifdef __cplusplus
 361 }
 362 #endif
 363 #endif /* __YUCCA_H_ */