2 * Copyright 2004 Freescale Semiconductor.
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
31 #include "../common/cadmus.h"
32 #include "../common/eeprom.h"
34 #if defined(CONFIG_DDR_ECC)
35 extern void ddr_enable_ecc(unsigned int dram_size);
38 extern long int spd_sdram(void);
40 void local_bus_init(void);
41 void sdram_init(void);
43 int board_early_init_f (void)
50 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
51 volatile ccsr_gur_t *gur = &immap->im_gur;
53 /* PCI slot in USER bits CSR[6:7] by convention. */
54 uint pci_slot = get_pci_slot ();
56 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
57 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
58 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
59 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
61 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
63 uint cpu_board_rev = get_cpu_board_revision ();
65 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
66 get_board_version (), pci_slot);
68 printf ("CPU Board Revision %d.%d (0x%04x)\n",
69 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
70 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
72 printf (" PCI1: %d bit, %s MHz, %s\n",
74 (pci1_speed == 33000000) ? "33" :
75 (pci1_speed == 66000000) ? "66" : "unknown",
76 pci1_clk_sel ? "sync" : "async");
79 printf (" PCI2: 32 bit, 66 MHz, %s\n",
80 pci2_clk_sel ? "sync" : "async");
82 printf (" PCI2: disabled\n");
86 * Initialize local bus.
94 initdram(int board_type)
97 volatile immap_t *immap = (immap_t *)CFG_IMMR;
99 puts("Initializing\n");
101 #if defined(CONFIG_DDR_DLL)
104 * Work around to stabilize DDR DLL MSYNC_IN.
105 * Errata DDR9 seems to have been fixed.
106 * This is now the workaround for Errata DDR11:
107 * Override DLL = 1, Course Adj = 1, Tap Select = 0
110 volatile ccsr_gur_t *gur= &immap->im_gur;
112 gur->ddrdllcr = 0x81000000;
113 asm("sync;isync;msync");
117 dram_size = spd_sdram();
119 #if defined(CONFIG_DDR_ECC)
121 * Initialize and enable DDR ECC.
123 ddr_enable_ecc(dram_size);
126 * SDRAM Initialization
135 * Initialize Local Bus
140 volatile immap_t *immap = (immap_t *)CFG_IMMR;
141 volatile ccsr_gur_t *gur = &immap->im_gur;
142 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
151 * Fix Local Bus clock glitch when DLL is enabled.
153 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
154 * If localbus freq is > 133Mhz, DLL can be safely enabled.
155 * Between 66 and 133, the DLL is enabled with an override workaround.
158 get_sys_info(&sysinfo);
159 clkdiv = lbc->lcrr & 0x0f;
160 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
163 lbc->lcrr |= 0x80000000; /* DLL Bypass */
165 } else if (lbc_hz >= 133) {
166 lbc->lcrr &= (~0x80000000); /* DLL Enabled */
169 lbc->lcrr &= (~0x8000000); /* DLL Enabled */
173 * Sample LBC DLL ctrl reg, upshift it to set the
176 temp_lbcdll = gur->lbcdllcr;
177 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
178 asm("sync;isync;msync");
183 * Initialize SDRAM memory on the Local Bus.
188 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
191 volatile immap_t *immap = (immap_t *)CFG_IMMR;
192 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
193 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
199 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
202 * Setup SDRAM Base and Option Registers
204 lbc->or2 = CFG_OR2_PRELIM;
207 lbc->br2 = CFG_BR2_PRELIM;
210 lbc->lbcr = CFG_LBC_LBCR;
214 lbc->lsrt = CFG_LBC_LSRT;
215 lbc->mrtpr = CFG_LBC_MRTPR;
219 * Determine which address lines to use baed on CPU board rev.
221 cpu_board_rev = get_cpu_board_revision();
222 lsdmr_common = CFG_LBC_LSDMR_COMMON;
223 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
224 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
225 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
226 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
229 * Assume something unable to identify itself is
230 * really old, and likely has lines 16/17 mapped.
232 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
236 * Issue PRECHARGE ALL command.
238 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
241 ppcDcbf((unsigned long) sdram_addr);
245 * Issue 8 AUTO REFRESH commands.
247 for (idx = 0; idx < 8; idx++) {
248 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
251 ppcDcbf((unsigned long) sdram_addr);
256 * Issue 8 MODE-set command.
258 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
261 ppcDcbf((unsigned long) sdram_addr);
265 * Issue NORMAL OP command.
267 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
270 ppcDcbf((unsigned long) sdram_addr);
271 udelay(200); /* Overkill. Must wait > 200 bus cycles */
273 #endif /* enable SDRAM init */
276 #if defined(CFG_DRAM_TEST)
280 uint *pstart = (uint *) CFG_MEMTEST_START;
281 uint *pend = (uint *) CFG_MEMTEST_END;
284 printf("Testing DRAM from 0x%08x to 0x%08x\n",
288 printf("DRAM test phase 1:\n");
289 for (p = pstart; p < pend; p++)
292 for (p = pstart; p < pend; p++) {
293 if (*p != 0xaaaaaaaa) {
294 printf ("DRAM test fails at: %08x\n", (uint) p);
299 printf("DRAM test phase 2:\n");
300 for (p = pstart; p < pend; p++)
303 for (p = pstart; p < pend; p++) {
304 if (*p != 0x55555555) {
305 printf ("DRAM test fails at: %08x\n", (uint) p);
310 printf("DRAM test passed.\n");
315 #if defined(CONFIG_PCI)
318 * Initialize PCI Devices, report devices found.
321 #ifndef CONFIG_PCI_PNP
322 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
323 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
324 PCI_IDSEL_NUMBER, PCI_ANY_ID,
325 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
327 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
333 static struct pci_controller hose = {
334 #ifndef CONFIG_PCI_PNP
335 config_table: pci_mpc85xxcds_config_table,
339 #endif /* CONFIG_PCI */
345 extern void pci_mpc85xx_init(struct pci_controller *hose);
347 pci_mpc85xx_init(&hose);