board/compulab/cm_fx6/cm_fx6.c

   1 /*
   2  * Board functions for Compulab CM-FX6 board
   3  *
   4  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   5  *
   6  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <fsl_esdhc.h>
  13 #include <miiphy.h>
  14 #include <netdev.h>
  15 #include <fdt_support.h>
  16 #include <sata.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/iomux.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/sata.h>
  22 #include <asm/io.h>
  23 #include <asm/gpio.h>
  24 #include "common.h"
  25 #include "../common/eeprom.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef CONFIG_DWC_AHSATA
  30 static int cm_fx6_issd_gpios[] = {
  31         /* The order of the GPIOs in the array is important! */
  32         CM_FX6_SATA_PHY_SLP,
  33         CM_FX6_SATA_NRSTDLY,
  34         CM_FX6_SATA_PWREN,
  35         CM_FX6_SATA_NSTANDBY1,
  36         CM_FX6_SATA_NSTANDBY2,
  37         CM_FX6_SATA_LDO_EN,
  38 };
  39
  40 static void cm_fx6_sata_power(int on)
  41 {
  42         int i;
  43
  44         if (!on) { /* tell the iSSD that the power will be removed */
  45                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
  46                 mdelay(10);
  47         }
  48
  49         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
  50                 gpio_direction_output(cm_fx6_issd_gpios[i], on);
  51                 udelay(100);
  52         }
  53
  54         if (!on) /* for compatibility lower the power loss interrupt */
  55                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
  56 }
  57
  58 static iomux_v3_cfg_t const sata_pads[] = {
  59         /* SATA PWR */
  60         IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  61         IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  62         IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  63         IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  64         /* SATA CTRL */
  65         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  66         IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  67         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  68         IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  69         IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  70 };
  71
  72 static void cm_fx6_setup_issd(void)
  73 {
  74         SETUP_IOMUX_PADS(sata_pads);
  75         /* Make sure this gpio has logical 0 value */
  76         gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
  77         udelay(100);
  78
  79         cm_fx6_sata_power(0);
  80         mdelay(250);
  81         cm_fx6_sata_power(1);
  82 }
  83
  84 #define CM_FX6_SATA_INIT_RETRIES        10
  85 int sata_initialize(void)
  86 {
  87         int err, i;
  88
  89         cm_fx6_setup_issd();
  90         for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
  91                 err = setup_sata();
  92                 if (err) {
  93                         printf("SATA setup failed: %d\n", err);
  94                         return err;
  95                 }
  96
  97                 udelay(100);
  98
  99                 err = __sata_initialize();
 100                 if (!err)
 101                         break;
 102
 103                 /* There is no device on the SATA port */
 104                 if (sata_port_status(0, 0) == 0)
 105                         break;
 106
 107                 /* There's a device, but link not established. Retry */
 108         }
 109
 110         return err;
 111 }
 112 #endif
 113
 114 #ifdef CONFIG_SYS_I2C_MXC
 115 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 116                         PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
 117                         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 118
 119 I2C_PADS(i2c0_pads,
 120          PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 121          PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 122          IMX_GPIO_NR(3, 21),
 123          PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 124          PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 125          IMX_GPIO_NR(3, 28));
 126
 127 I2C_PADS(i2c1_pads,
 128          PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 129          PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 130          IMX_GPIO_NR(4, 12),
 131          PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 132          PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 133          IMX_GPIO_NR(4, 13));
 134
 135 I2C_PADS(i2c2_pads,
 136          PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 137          PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 138          IMX_GPIO_NR(1, 3),
 139          PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 140          PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 141          IMX_GPIO_NR(1, 6));
 142
 143
 144 static void cm_fx6_setup_i2c(void)
 145 {
 146         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c0_pads));
 147         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c1_pads));
 148         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c2_pads));
 149 }
 150 #else
 151 static void cm_fx6_setup_i2c(void) { }
 152 #endif
 153
 154 #ifdef CONFIG_USB_EHCI_MX6
 155 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
 156                         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
 157                         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 158
 159 static int cm_fx6_usb_hub_reset(void)
 160 {
 161         int err;
 162
 163         err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
 164         if (err) {
 165                 printf("USB hub rst gpio request failed: %d\n", err);
 166                 return -1;
 167         }
 168
 169         SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
 170         gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
 171         udelay(10);
 172         gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
 173         mdelay(1);
 174
 175         return 0;
 176 }
 177
 178 static int cm_fx6_init_usb_otg(void)
 179 {
 180         int ret;
 181         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 182
 183         ret = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
 184         if (ret) {
 185                 printf("USB OTG pwr gpio request failed: %d\n", ret);
 186                 return ret;
 187         }
 188
 189         SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
 190         SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
 191                                                 MUX_PAD_CTRL(WEAK_PULLDOWN));
 192         clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
 193         /* disable ext. charger detect, or it'll affect signal quality at dp. */
 194         return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
 195 }
 196
 197 #define MX6_USBNC_BASEADDR      0x2184800
 198 #define USBNC_USB_H1_PWR_POL    (1 << 9)
 199 int board_ehci_hcd_init(int port)
 200 {
 201         u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
 202
 203         switch (port) {
 204         case 0:
 205                 return cm_fx6_init_usb_otg();
 206         case 1:
 207                 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR |
 208                                 MUX_PAD_CTRL(NO_PAD_CTRL));
 209
 210                 /* Set PWR polarity to match power switch's enable polarity */
 211                 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
 212                 return cm_fx6_usb_hub_reset();
 213         default:
 214                 break;
 215         }
 216
 217         return 0;
 218 }
 219
 220 int board_ehci_power(int port, int on)
 221 {
 222         if (port == 0)
 223                 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
 224
 225         return 0;
 226 }
 227 #endif
 228
 229 #ifdef CONFIG_FEC_MXC
 230 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 231                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 232
 233 static int mx6_rgmii_rework(struct phy_device *phydev)
 234 {
 235         unsigned short val;
 236
 237         /* Ar8031 phy SmartEEE feature cause link status generates glitch,
 238          * which cause ethernet link down/up issue, so disable SmartEEE
 239          */
 240         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
 241         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 242         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 243         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 244         val &= ~(0x1 << 8);
 245         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 246
 247         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 248         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 249         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 250         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 251
 252         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 253         val &= 0xffe3;
 254         val |= 0x18;
 255         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 256
 257         /* introduce tx clock delay */
 258         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 259         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 260         val |= 0x0100;
 261         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 262
 263         return 0;
 264 }
 265
 266 int board_phy_config(struct phy_device *phydev)
 267 {
 268         mx6_rgmii_rework(phydev);
 269
 270         if (phydev->drv->config)
 271                 return phydev->drv->config(phydev);
 272
 273         return 0;
 274 }
 275
 276 static iomux_v3_cfg_t const enet_pads[] = {
 277         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 278         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 279         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 280         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 281         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 282         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 283         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 284         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 285         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 286         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 287         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 288         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 289         IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 290         IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 291         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
 292         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
 293                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 294         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 295                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 296         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 297                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 298 };
 299
 300 static int handle_mac_address(void)
 301 {
 302         unsigned char enetaddr[6];
 303         int rc;
 304
 305         rc = eth_getenv_enetaddr("ethaddr", enetaddr);
 306         if (rc)
 307                 return 0;
 308
 309         rc = cl_eeprom_read_mac_addr(enetaddr);
 310         if (rc)
 311                 return rc;
 312
 313         if (!is_valid_ether_addr(enetaddr))
 314                 return -1;
 315
 316         return eth_setenv_enetaddr("ethaddr", enetaddr);
 317 }
 318
 319 int board_eth_init(bd_t *bis)
 320 {
 321         int res = handle_mac_address();
 322         if (res)
 323                 puts("No MAC address found\n");
 324
 325         SETUP_IOMUX_PADS(enet_pads);
 326         /* phy reset */
 327         gpio_direction_output(CM_FX6_ENET_NRST, 0);
 328         udelay(500);
 329         gpio_set_value(CM_FX6_ENET_NRST, 1);
 330         enable_enet_clk(1);
 331         return cpu_eth_init(bis);
 332 }
 333 #endif
 334
 335 #ifdef CONFIG_NAND_MXS
 336 static iomux_v3_cfg_t const nand_pads[] = {
 337         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 338         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 339         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 340         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 341         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 342         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 343         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 344         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 345         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 346         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 347         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 348         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 349         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 350         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 351 };
 352
 353 static void cm_fx6_setup_gpmi_nand(void)
 354 {
 355         SETUP_IOMUX_PADS(nand_pads);
 356         /* Enable clock roots */
 357         enable_usdhc_clk(1, 3);
 358         enable_usdhc_clk(1, 4);
 359
 360         setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
 361                           MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
 362                           MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
 363 }
 364 #else
 365 static void cm_fx6_setup_gpmi_nand(void) {}
 366 #endif
 367
 368 #ifdef CONFIG_FSL_ESDHC
 369 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 370         {USDHC1_BASE_ADDR},
 371         {USDHC2_BASE_ADDR},
 372         {USDHC3_BASE_ADDR},
 373 };
 374
 375 static enum mxc_clock usdhc_clk[3] = {
 376         MXC_ESDHC_CLK,
 377         MXC_ESDHC2_CLK,
 378         MXC_ESDHC3_CLK,
 379 };
 380
 381 int board_mmc_init(bd_t *bis)
 382 {
 383         int i;
 384
 385         cm_fx6_set_usdhc_iomux();
 386         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 387                 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
 388                 usdhc_cfg[i].max_bus_width = 4;
 389                 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 390                 enable_usdhc_clk(1, i);
 391         }
 392
 393         return 0;
 394 }
 395 #endif
 396
 397 #ifdef CONFIG_OF_BOARD_SETUP
 398 void ft_board_setup(void *blob, bd_t *bd)
 399 {
 400         uint8_t enetaddr[6];
 401
 402         /* MAC addr */
 403         if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
 404                 fdt_find_and_setprop(blob, "/fec", "local-mac-address",
 405                                      enetaddr, 6, 1);
 406         }
 407 }
 408 #endif
 409
 410 int board_init(void)
 411 {
 412         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 413         cm_fx6_setup_gpmi_nand();
 414         cm_fx6_setup_i2c();
 415
 416         return 0;
 417 }
 418
 419 int checkboard(void)
 420 {
 421         puts("Board: CM-FX6\n");
 422         return 0;
 423 }
 424
 425 void dram_init_banksize(void)
 426 {
 427         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 428         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 429
 430         switch (gd->ram_size) {
 431         case 0x10000000: /* DDR_16BIT_256MB */
 432                 gd->bd->bi_dram[0].size = 0x10000000;
 433                 gd->bd->bi_dram[1].size = 0;
 434                 break;
 435         case 0x20000000: /* DDR_32BIT_512MB */
 436                 gd->bd->bi_dram[0].size = 0x20000000;
 437                 gd->bd->bi_dram[1].size = 0;
 438                 break;
 439         case 0x40000000:
 440                 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
 441                         gd->bd->bi_dram[0].size = 0x20000000;
 442                         gd->bd->bi_dram[1].size = 0x20000000;
 443                 } else { /* DDR_64BIT_1GB */
 444                         gd->bd->bi_dram[0].size = 0x40000000;
 445                         gd->bd->bi_dram[1].size = 0;
 446                 }
 447                 break;
 448         case 0x80000000: /* DDR_64BIT_2GB */
 449                 gd->bd->bi_dram[0].size = 0x40000000;
 450                 gd->bd->bi_dram[1].size = 0x40000000;
 451                 break;
 452         case 0xEFF00000: /* DDR_64BIT_4GB */
 453                 gd->bd->bi_dram[0].size = 0x70000000;
 454                 gd->bd->bi_dram[1].size = 0x7FF00000;
 455                 break;
 456         }
 457 }
 458
 459 int dram_init(void)
 460 {
 461         gd->ram_size = imx_ddr_size();
 462         switch (gd->ram_size) {
 463         case 0x10000000:
 464         case 0x20000000:
 465         case 0x40000000:
 466         case 0x80000000:
 467                 break;
 468         case 0xF0000000:
 469                 gd->ram_size -= 0x100000;
 470                 break;
 471         default:
 472                 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
 473                 return -1;
 474         }
 475
 476         return 0;
 477 }
 478
 479 u32 get_board_rev(void)
 480 {
 481         return cl_eeprom_get_board_rev();
 482 }
 483