4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/iomux-mx28.h>
30 #include <asm/arch/imx-regs.h>
31 #include <asm/arch/sys_proto.h>
33 #define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
34 #define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
35 #define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
36 #define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
37 #define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
38 #define MUX_CONFIG_GPMI (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
39 #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
40 #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
42 const iomux_cfg_t iomux_setup[] = {
44 MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
47 MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
48 MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
49 MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
50 MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
51 MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
52 MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
53 MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
54 MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
55 MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
56 MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
57 MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
58 MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
59 MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
60 MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
61 MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
62 MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
63 MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
64 MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
65 MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
66 MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
67 MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
68 MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
69 MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
70 MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
71 MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
72 MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
75 #ifdef CONFIG_DENX_M28_V10
76 MX28_PAD_AUART0_CTS__DUART_RX,
77 MX28_PAD_AUART0_RTS__DUART_TX,
79 MX28_PAD_PWM0__DUART_RX,
80 MX28_PAD_PWM1__DUART_TX,
82 MX28_PAD_AUART0_TX__DUART_RTS,
83 MX28_PAD_AUART0_RX__DUART_CTS,
86 MX28_PAD_AUART1_RX__AUART1_RX,
87 MX28_PAD_AUART1_TX__AUART1_TX,
88 MX28_PAD_AUART1_RTS__AUART1_RTS,
89 MX28_PAD_AUART1_CTS__AUART1_CTS,
92 MX28_PAD_GPMI_RDY2__CAN0_TX,
93 MX28_PAD_GPMI_RDY3__CAN0_RX,
96 MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC,
99 MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
100 MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
101 MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
102 MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
103 MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
104 MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
105 MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
106 MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
107 MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
108 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
109 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
110 MX28_PAD_SSP0_SCK__SSP0_SCK |
111 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
112 MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 |
113 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), /* Power */
114 MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP */
117 MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
118 MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
119 MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
120 MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
121 MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
122 MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
123 MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
124 MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
125 MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
126 MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
127 MX28_PAD_GPMI_RDN__GPMI_RDN |
128 (MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP),
129 MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
130 MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
131 MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
132 MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
135 MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
136 MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
137 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
138 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
139 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
140 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
141 MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
142 MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
143 MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
145 MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
146 MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
147 MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
148 MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
149 MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
150 MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
151 #if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
152 MX28_PAD_AUART2_RTS__GPIO_3_11, /* PHY reset */
156 MX28_PAD_I2C0_SCL__I2C0_SCL,
157 MX28_PAD_I2C0_SDA__I2C0_SDA,
160 MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
161 MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
162 MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
163 MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
164 MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
165 MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
166 MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
167 MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
168 MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
169 MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
170 MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
171 MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
172 MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
173 MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
174 MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
175 MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
176 MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
177 MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
178 MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
179 MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
180 MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
181 MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
182 MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
183 MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
184 MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
186 MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
187 MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
188 MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
189 MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
190 MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
191 MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
192 MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
193 MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
194 MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
195 MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
196 MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
197 MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
198 MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
199 MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
200 MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
201 MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
202 MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
203 MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
204 MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
205 MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
206 MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
207 MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
208 MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
209 MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
211 /* SPI2 (for flash) */
212 MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
213 MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
214 MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
215 MX28_PAD_SSP2_SS0__SSP2_D3 |
216 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
219 void board_init_ll(void)
221 mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
224 static uint32_t dram_vals[] = {
225 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
226 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
227 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
228 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000,
229 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
230 0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a,
231 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000,
232 0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
233 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202,
234 0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303,
235 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100,
236 0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
237 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
238 0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200,
239 0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27,
240 0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006,
241 0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201,
242 0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04,
243 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
244 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
245 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
246 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
247 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
248 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
249 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
250 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
251 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
252 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
253 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
254 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
255 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
256 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
257 0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004,
258 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
259 0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303,
260 0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200,
261 0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004,
262 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001
265 void mx28_ddr2_setup(void)
270 for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
271 writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));