board/esd/pmc440/pmc440.c

   1 /*
   2  * (Cg) Copyright 2007-2008
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
   4  * Based on board/amcc/sequoia/sequoia.c
   5  *
   6  * (C) Copyright 2006
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * (C) Copyright 2006
  10  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  11  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <libfdt.h>
  18 #include <fdt_support.h>
  19 #include <asm/ppc440.h>
  20 #include <asm/processor.h>
  21 #include <asm/io.h>
  22 #include <asm/bitops.h>
  23 #include <command.h>
  24 #include <i2c.h>
  25 #ifdef CONFIG_RESET_PHY_R
  26 #include <miiphy.h>
  27 #endif
  28 #include <serial.h>
  29 #include <asm/4xx_pci.h>
  30 #include <usb.h>
  31
  32 #include "fpga.h"
  33 #include "pmc440.h"
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  38 extern void __ft_board_setup(void *blob, bd_t *bd);
  39
  40 ulong flash_get_size(ulong base, int banknum);
  41 int pci_is_66mhz(void);
  42 int is_monarch(void);
  43 int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
  44                           uchar *buffer, unsigned cnt);
  45
  46 struct serial_device *default_serial_console(void)
  47 {
  48         uchar buf[4];
  49         ulong delay;
  50         int i;
  51         ulong val;
  52
  53         /*
  54          * Use default console on P4 when strapping jumper
  55          * is installed (bootstrap option != 'H').
  56          */
  57         mfsdr(SDR0_PINSTP, val);
  58         if (((val & 0xf0000000) >> 29) != 7)
  59                 return &eserial2_device;
  60
  61         ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
  62         if (!(scratchreg & 0x80)) {
  63                 /* mark scratchreg valid */
  64                 scratchreg = (scratchreg & 0xffffff00) | 0x80;
  65
  66                 i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
  67                                           0x10, buf, 4);
  68                 if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
  69                         scratchreg |= buf[2];
  70
  71                         /* bringup delay for console */
  72                         for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
  73                                 udelay(1000);
  74                         }
  75                 } else
  76                         scratchreg |= 0x01;
  77                 out_be32((void*)GPIO0_ISR3L, scratchreg);
  78         }
  79
  80         if (scratchreg & 0x01)
  81                 return &eserial2_device;
  82         else
  83                 return &eserial1_device;
  84 }
  85
  86 int board_early_init_f(void)
  87 {
  88         u32 sdr0_cust0;
  89         u32 sdr0_pfc1, sdr0_pfc2;
  90         u32 reg;
  91
  92         /* general EBC configuration (disable EBC timeouts) */
  93         mtdcr(EBC0_CFGADDR, EBC0_CFG);
  94         mtdcr(EBC0_CFGDATA, 0xf8400000);
  95
  96         /*
  97          * Setup the GPIO pins
  98          * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
  99          */
 100         out_be32((void *)GPIO0_OR,    0x40000102);
 101         out_be32((void *)GPIO0_TCR,   0x4c90011f);
 102         out_be32((void *)GPIO0_OSRL,  0x28051400);
 103         out_be32((void *)GPIO0_OSRH,  0x55005000);
 104         out_be32((void *)GPIO0_TSRL,  0x08051400);
 105         out_be32((void *)GPIO0_TSRH,  0x55005000);
 106         out_be32((void *)GPIO0_ISR1L, 0x54000000);
 107         out_be32((void *)GPIO0_ISR1H, 0x00000000);
 108         out_be32((void *)GPIO0_ISR2L, 0x44000000);
 109         out_be32((void *)GPIO0_ISR2H, 0x00000100);
 110         out_be32((void *)GPIO0_ISR3L, 0x00000000);
 111         out_be32((void *)GPIO0_ISR3H, 0x00000000);
 112
 113         out_be32((void *)GPIO1_OR,    0x80002408);
 114         out_be32((void *)GPIO1_TCR,   0xd6003c08);
 115         out_be32((void *)GPIO1_OSRL,  0x0a5a0000);
 116         out_be32((void *)GPIO1_OSRH,  0x00000000);
 117         out_be32((void *)GPIO1_TSRL,  0x00000000);
 118         out_be32((void *)GPIO1_TSRH,  0x00000000);
 119         out_be32((void *)GPIO1_ISR1L, 0x00005555);
 120         out_be32((void *)GPIO1_ISR1H, 0x40000000);
 121         out_be32((void *)GPIO1_ISR2L, 0x04010000);
 122         out_be32((void *)GPIO1_ISR2H, 0x00000000);
 123         out_be32((void *)GPIO1_ISR3L, 0x01400000);
 124         out_be32((void *)GPIO1_ISR3H, 0x00000000);
 125
 126         /* patch PLB:PCI divider for 66MHz PCI */
 127         mfcpr(CPR0_SPCID, reg);
 128         if (pci_is_66mhz() && (reg != 0x02000000)) {
 129                 mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
 130
 131                 mfcpr(CPR0_ICFG, reg);
 132                 reg |= CPR0_ICFG_RLI_MASK;
 133                 mtcpr(CPR0_ICFG, reg);
 134
 135                 mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
 136         }
 137
 138         /*
 139          * Setup the interrupt controller polarities, triggers, etc.
 140          */
 141         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 142         mtdcr(UIC0ER, 0x00000000);      /* disable all */
 143         mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
 144         mtdcr(UIC0PR, 0xfffff7ef);
 145         mtdcr(UIC0TR, 0x00000000);
 146         mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
 147         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 148
 149         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 150         mtdcr(UIC1ER, 0x00000000);      /* disable all */
 151         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
 152         mtdcr(UIC1PR, 0xffffc7f5);
 153         mtdcr(UIC1TR, 0x00000000);
 154         mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
 155         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 156
 157         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 158         mtdcr(UIC2ER, 0x00000000);      /* disable all */
 159         mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
 160         mtdcr(UIC2PR, 0x27ffffff);
 161         mtdcr(UIC2TR, 0x00000000);
 162         mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
 163         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 164
 165         /* select Ethernet pins */
 166         mfsdr(SDR0_PFC1, sdr0_pfc1);
 167         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
 168                 SDR0_PFC1_SELECT_CONFIG_4;
 169         mfsdr(SDR0_PFC2, sdr0_pfc2);
 170         sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
 171                 SDR0_PFC2_SELECT_CONFIG_4;
 172
 173         /* enable 2nd IIC */
 174         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
 175
 176         mtsdr(SDR0_PFC2, sdr0_pfc2);
 177         mtsdr(SDR0_PFC1, sdr0_pfc1);
 178
 179         /* setup NAND FLASH */
 180         mfsdr(SDR0_CUST0, sdr0_cust0);
 181         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
 182                 SDR0_CUST0_NDFC_ENABLE          |
 183                 SDR0_CUST0_NDFC_BW_8_BIT        |
 184                 SDR0_CUST0_NDFC_ARE_MASK        |
 185                 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 186         mtsdr(SDR0_CUST0, sdr0_cust0);
 187
 188         return 0;
 189 }
 190
 191 #if defined(CONFIG_MISC_INIT_F)
 192 int misc_init_f(void)
 193 {
 194         struct pci_controller hose;
 195         hose.first_busno = 0;
 196         hose.last_busno = 0;
 197         hose.region_count = 0;
 198
 199         if (getenv("pciearly") && (!is_monarch())) {
 200                 printf("PCI:   early target init\n");
 201                 pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
 202                 pci_target_init(&hose);
 203         }
 204         return 0;
 205 }
 206 #endif
 207
 208 /*
 209  * misc_init_r.
 210  */
 211 int misc_init_r(void)
 212 {
 213         uint pbcr;
 214         int size_val = 0;
 215         u32 reg;
 216         unsigned long usb2d0cr = 0;
 217         unsigned long usb2phy0cr, usb2h0cr = 0;
 218         unsigned long sdr0_pfc1;
 219         unsigned long sdr0_srst0, sdr0_srst1;
 220         char *act = getenv("usbact");
 221
 222         /*
 223          * FLASH stuff...
 224          */
 225
 226         /* Re-do sizing to get full correct info */
 227
 228         /* adjust flash start and offset */
 229         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 230         gd->bd->bi_flashoffset = 0;
 231
 232 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 233         mtdcr(EBC0_CFGADDR, PB2CR);
 234 #else
 235         mtdcr(EBC0_CFGADDR, PB0CR);
 236 #endif
 237         pbcr = mfdcr(EBC0_CFGDATA);
 238         size_val = ffs(gd->bd->bi_flashsize) - 21;
 239         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 240 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 241         mtdcr(EBC0_CFGADDR, PB2CR);
 242 #else
 243         mtdcr(EBC0_CFGADDR, PB0CR);
 244 #endif
 245         mtdcr(EBC0_CFGDATA, pbcr);
 246
 247         /*
 248          * Re-check to get correct base address
 249          */
 250         flash_get_size(gd->bd->bi_flashstart, 0);
 251
 252 #ifdef CONFIG_ENV_IS_IN_FLASH
 253         /* Monitor protection ON by default */
 254         (void)flash_protect(FLAG_PROTECT_SET,
 255                             -CONFIG_SYS_MONITOR_LEN,
 256                             0xffffffff,
 257                             &flash_info[0]);
 258
 259         /* Env protection ON by default */
 260         (void)flash_protect(FLAG_PROTECT_SET,
 261                             CONFIG_ENV_ADDR_REDUND,
 262                             CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
 263                             &flash_info[0]);
 264 #endif
 265
 266         /*
 267          * USB suff...
 268          */
 269         if ((act == NULL || strcmp(act, "host") == 0) &&
 270             !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
 271                 /* SDR Setting */
 272                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 273                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 274                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 275                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 276
 277                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 278                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 279                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 280                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
 281                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 282                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 283                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 284                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 285                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 286                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 287
 288                 /*
 289                  * An 8-bit/60MHz interface is the only possible alternative
 290                  * when connecting the Device to the PHY
 291                  */
 292                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 293                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
 294
 295                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 296                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 297
 298                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 299                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 300                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 301                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 302
 303                 /*
 304                  * Take USB out of reset:
 305                  * -Initial status = all cores are in reset
 306                  * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
 307                  * -wait 1 ms
 308                  * -deassert reset to PHY
 309                  * -wait 1 ms
 310                  * -deassert  reset to HOST
 311                  * -wait 4 ms
 312                  * -deassert all other resets
 313                  */
 314                 mfsdr(SDR0_SRST1, sdr0_srst1);
 315                 sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 |      \
 316                                 SDR0_SRST1_P4OPB0 |     \
 317                                 SDR0_SRST1_OPBA2 |      \
 318                                 SDR0_SRST1_PLB42OPB1 |  \
 319                                 SDR0_SRST1_OPB2PLB40);
 320                 mtsdr(SDR0_SRST1, sdr0_srst1);
 321                 udelay(1000);
 322
 323                 mfsdr(SDR0_SRST1, sdr0_srst1);
 324                 sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
 325                 mtsdr(SDR0_SRST1, sdr0_srst1);
 326                 udelay(1000);
 327
 328                 mfsdr(SDR0_SRST0, sdr0_srst0);
 329                 sdr0_srst0 &= ~SDR0_SRST0_USB2H;
 330                 mtsdr(SDR0_SRST0, sdr0_srst0);
 331                 udelay(4000);
 332
 333                 /* finally all the other resets */
 334                 mtsdr(SDR0_SRST1, 0x00000000);
 335                 mtsdr(SDR0_SRST0, 0x00000000);
 336
 337                 if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
 338                         /* enable power on USB socket */
 339                         out_be32((void*)GPIO1_OR,
 340                                  in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
 341                 }
 342
 343                 printf("USB:   Host\n");
 344
 345         } else if ((strcmp(act, "dev") == 0) ||
 346                    (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
 347                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 348
 349                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 350                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 351                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 352                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 353                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 354                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 355                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 356                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 357                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 358
 359                 udelay (1000);
 360                 mtsdr(SDR0_SRST1, 0x672c6000);
 361
 362                 udelay (1000);
 363                 mtsdr(SDR0_SRST0, 0x00000080);
 364
 365                 udelay (1000);
 366                 mtsdr(SDR0_SRST1, 0x60206000);
 367
 368                 *(unsigned int *)(0xe0000350) = 0x00000001;
 369
 370                 udelay (1000);
 371                 mtsdr(SDR0_SRST1, 0x60306000);
 372
 373                 /* SDR Setting */
 374                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 375                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 376                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 377                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 378
 379                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 380                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 381                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 382                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
 383                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 384                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
 385                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 386                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
 387                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 388                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
 389
 390                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 391                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
 392
 393                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 394
 395                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 396                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
 397
 398                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 399                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 400                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 401                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 402
 403                 /*clear resets*/
 404                 udelay(1000);
 405                 mtsdr(SDR0_SRST1, 0x00000000);
 406                 udelay(1000);
 407                 mtsdr(SDR0_SRST0, 0x00000000);
 408
 409                 printf("USB:   Device\n");
 410         }
 411
 412         /*
 413          * Clear PLB4A0_ACR[WRP]
 414          * This fix will make the MAL burst disabling patch for the Linux
 415          * EMAC driver obsolete.
 416          */
 417         reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
 418         mtdcr(PLB4A0_ACR, reg);
 419
 420 #ifdef CONFIG_FPGA
 421         pmc440_init_fpga();
 422 #endif
 423
 424         /* turn off POST LED */
 425         out_be32((void*)GPIO1_OR,  in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
 426         /* turn on RUN LED */
 427         out_be32((void*)GPIO0_OR,  in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
 428         return 0;
 429 }
 430
 431 int is_monarch(void)
 432 {
 433         if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
 434                 return 0;
 435
 436         return 1;
 437 }
 438
 439 int pci_is_66mhz(void)
 440 {
 441         if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
 442                 return 1;
 443         return 0;
 444 }
 445
 446 int board_revision(void)
 447 {
 448         return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
 449 }
 450
 451 int checkboard(void)
 452 {
 453         puts("Board: esd GmbH - PMC440");
 454
 455         gd->board_type = board_revision();
 456         printf(", Rev 1.%ld, ", gd->board_type);
 457
 458         if (!is_monarch()) {
 459                 puts("non-");
 460         }
 461
 462         printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
 463         return (0);
 464 }
 465
 466
 467 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
 468 /*
 469  * Assign interrupts to PCI devices. Some OSs rely on this.
 470  */
 471 void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 472 {
 473         unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
 474
 475         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
 476                                    int_line[PCI_DEV(dev) & 0x03]);
 477 }
 478 #endif
 479
 480 /*
 481  * pci_target_init
 482  *
 483  * The bootstrap configuration provides default settings for the pci
 484  * inbound map (PIM). But the bootstrap config choices are limited and
 485  * may not be sufficient for a given board.
 486  */
 487 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 488 void pci_target_init(struct pci_controller *hose)
 489 {
 490         char *ptmla_str, *ptmms_str;
 491
 492         /*
 493          * Set up Direct MMIO registers
 494          */
 495         /*
 496          * PowerPC440EPX PCI Master configuration.
 497          * Map one 1Gig range of PLB/processor addresses to PCI memory space.
 498          * PLB address 0x80000000-0xBFFFFFFF
 499          *     ==> PCI address 0x80000000-0xBFFFFFFF
 500          * Use byte reversed out routines to handle endianess.
 501          * Make this region non-prefetchable.
 502          */
 503         out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
 504                                                 /* - disabled b4 setting */
 505         out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
 506         out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
 507         out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 508         out32r(PCIL0_PMM0MA, 0xc0000001);       /* 1G + No prefetching, */
 509                                                 /* and enable region */
 510
 511         if (!is_monarch()) {
 512                 ptmla_str = getenv("ptm1la");
 513                 ptmms_str = getenv("ptm1ms");
 514                 if(NULL != ptmla_str && NULL != ptmms_str ) {
 515                         out32r(PCIL0_PTM1MS,
 516                                simple_strtoul(ptmms_str, NULL, 16));
 517                         out32r(PCIL0_PTM1LA,
 518                                simple_strtoul(ptmla_str, NULL, 16));
 519                 } else {
 520                         /* BAR1: default top 64MB of RAM */
 521                         out32r(PCIL0_PTM1MS, 0xfc000001);
 522                         out32r(PCIL0_PTM1LA, 0x0c000000);
 523                 }
 524         } else {
 525                 /* BAR1: default: complete 256MB RAM */
 526                 out32r(PCIL0_PTM1MS, 0xf0000001);
 527                 out32r(PCIL0_PTM1LA, 0x00000000);
 528         }
 529
 530         ptmla_str = getenv("ptm2la");           /* Local Addr. Reg */
 531         ptmms_str = getenv("ptm2ms");           /* Memory Size/Attribute */
 532         if(NULL != ptmla_str && NULL != ptmms_str ) {
 533                 out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
 534                 out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
 535         } else {
 536                 /* BAR2: default: 4MB FPGA */
 537                 out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
 538                 out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
 539         }
 540
 541         if (is_monarch()) {
 542                 /* BAR2: map FPGA registers behind system memory at 1GB */
 543                 pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008);
 544         }
 545
 546         /*
 547          * Set up Configuration registers
 548          */
 549
 550         /* Program the board's vendor id */
 551         pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
 552                                    CONFIG_SYS_PCI_SUBSYS_VENDORID);
 553
 554         /* disabled for PMC405 backward compatibility */
 555         /* Configure command register as bus master */
 556         /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
 557
 558
 559         /* 240nS PCI clock */
 560         pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
 561
 562         /* No error reporting */
 563         pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
 564
 565         if (!is_monarch()) {
 566                 /* Program the board's subsystem id/classcode */
 567                 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
 568                                            CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
 569                 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
 570                                            CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
 571
 572                 /* PCI configuration done: release ERREADY */
 573                 out_be32((void*)GPIO1_OR,
 574                          in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
 575                 out_be32((void*)GPIO1_TCR,
 576                          in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
 577         } else {
 578                 /* Program the board's subsystem id/classcode */
 579                 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
 580                                            CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
 581                 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
 582                                            CONFIG_SYS_PCI_CLASSCODE_MONARCH);
 583         }
 584
 585         /* enable host configuration */
 586         pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
 587 }
 588 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 589
 590 /*
 591  * Override weak default pci_master_init()
 592  */
 593 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 594 void pci_master_init(struct pci_controller *hose)
 595 {
 596         /*
 597          * Only configure the master in monach mode
 598          */
 599         if (is_monarch())
 600                 __pci_master_init(hose);
 601 }
 602 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 603
 604 static void wait_for_pci_ready(void)
 605 {
 606         if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
 607                 printf("PCI:   Waiting for EREADY (CTRL-C to skip) ... ");
 608                 while (1) {
 609                         if (ctrlc()) {
 610                                 puts("abort\n");
 611                                 break;
 612                         }
 613                         if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
 614                                 printf("done\n");
 615                                 break;
 616                         }
 617                 }
 618         }
 619 }
 620
 621 /*
 622  * Override weak is_pci_host()
 623  *
 624  * This routine is called to determine if a pci scan should be
 625  * performed. With various hardware environments (especially cPCI and
 626  * PPMC) it's insufficient to depend on the state of the arbiter enable
 627  * bit in the strap register, or generic host/adapter assumptions.
 628  *
 629  * Rather than hard-code a bad assumption in the general 440 code, the
 630  * 440 pci code requires the board to decide at runtime.
 631  *
 632  * Return 0 for adapter mode, non-zero for host (monarch) mode.
 633  */
 634 #if defined(CONFIG_PCI)
 635 int is_pci_host(struct pci_controller *hose)
 636 {
 637         char *s = getenv("pciscan");
 638         if (s == NULL)
 639                 if (is_monarch()) {
 640                         wait_for_pci_ready();
 641                         return 1;
 642                 } else
 643                         return 0;
 644         else if (!strcmp(s, "yes"))
 645                 return 1;
 646
 647         return 0;
 648 }
 649 #endif /* defined(CONFIG_PCI) */
 650
 651 #ifdef CONFIG_RESET_PHY_R
 652 void reset_phy(void)
 653 {
 654         char *s;
 655         unsigned short val_method, val_behavior;
 656
 657         /* special LED setup for NGCC/CANDES */
 658         if ((s = getenv("bd_type")) &&
 659             ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
 660                 val_method   = 0x0e0a;
 661                 val_behavior = 0x0cf2;
 662         } else {
 663                 /* PMC440 standard type */
 664                 val_method   = 0x0e10;
 665                 val_behavior = 0x0cf0;
 666         }
 667
 668         if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
 669                 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
 670                 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
 671                 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
 672                 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
 673         }
 674
 675         if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
 676                 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
 677                 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
 678                 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
 679                 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
 680         }
 681 }
 682 #endif
 683
 684 #if defined(CONFIG_SYS_EEPROM_WREN)
 685 /*
 686  *  Input: <dev_addr> I2C address of EEPROM device to enable.
 687  *         <state>    -1: deliver current state
 688  *                     0: disable write
 689  *                     1: enable write
 690  *  Returns:          -1: wrong device address
 691  *                     0: dis-/en- able done
 692  *                   0/1: current state if <state> was -1.
 693  */
 694 int eeprom_write_enable(unsigned dev_addr, int state)
 695 {
 696         if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
 697             (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
 698                 return -1;
 699         } else {
 700                 switch (state) {
 701                 case 1:
 702                         /* Enable write access, clear bit GPIO_SINT2. */
 703                         out_be32((void *)GPIO0_OR,
 704                               in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
 705                         state = 0;
 706                         break;
 707                 case 0:
 708                         /* Disable write access, set bit GPIO_SINT2. */
 709                         out_be32((void *)GPIO0_OR,
 710                                  in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
 711                         state = 0;
 712                         break;
 713                 default:
 714                         /* Read current status back. */
 715                         state = (0 == (in_be32((void *)GPIO0_OR)
 716                                        & GPIO0_EP_EEP));
 717                         break;
 718                 }
 719         }
 720         return state;
 721 }
 722 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 723
 724 #define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
 725 int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
 726                            uchar *buffer, unsigned cnt)
 727 {
 728         unsigned end = offset + cnt;
 729         unsigned blk_off;
 730         int rcode = 0;
 731
 732 #if defined(CONFIG_SYS_EEPROM_WREN)
 733         eeprom_write_enable(dev_addr, 1);
 734 #endif
 735         /*
 736          * Write data until done or would cross a write page boundary.
 737          * We must write the address again when changing pages
 738          * because the address counter only increments within a page.
 739          */
 740
 741         while (offset < end) {
 742                 unsigned alen, len;
 743                 unsigned maxlen;
 744                 uchar addr[2];
 745
 746                 blk_off = offset & 0xFF;        /* block offset */
 747
 748                 addr[0] = offset >> 8;          /* block number */
 749                 addr[1] = blk_off;              /* block offset */
 750                 alen    = 2;
 751                 addr[0] |= dev_addr;            /* insert device address */
 752
 753                 len = end - offset;
 754
 755 #define BOOT_EEPROM_PAGE_SIZE      (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
 756 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
 757
 758                 maxlen = BOOT_EEPROM_PAGE_SIZE -
 759                         BOOT_EEPROM_PAGE_OFFSET(blk_off);
 760                 if (maxlen > I2C_RXTX_LEN)
 761                         maxlen = I2C_RXTX_LEN;
 762
 763                 if (len > maxlen)
 764                         len = maxlen;
 765
 766                 if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
 767                         rcode = 1;
 768
 769                 buffer += len;
 770                 offset += len;
 771
 772 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
 773                 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 774 #endif
 775         }
 776 #if defined(CONFIG_SYS_EEPROM_WREN)
 777         eeprom_write_enable(dev_addr, 0);
 778 #endif
 779         return rcode;
 780 }
 781
 782 int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset,
 783                            uchar *buffer, unsigned cnt)
 784 {
 785         unsigned end = offset + cnt;
 786         unsigned blk_off;
 787         int rcode = 0;
 788
 789         /*
 790          * Read data until done or would cross a page boundary.
 791          * We must write the address again when changing pages
 792          * because the next page may be in a different device.
 793          */
 794         while (offset < end) {
 795                 unsigned alen, len;
 796                 unsigned maxlen;
 797                 uchar addr[2];
 798
 799                 blk_off = offset & 0xFF;        /* block offset */
 800
 801                 addr[0] = offset >> 8;          /* block number */
 802                 addr[1] = blk_off;              /* block offset */
 803                 alen    = 2;
 804
 805                 addr[0] |= dev_addr;            /* insert device address */
 806
 807                 len = end - offset;
 808
 809                 maxlen = 0x100 - blk_off;
 810                 if (maxlen > I2C_RXTX_LEN)
 811                         maxlen = I2C_RXTX_LEN;
 812                 if (len > maxlen)
 813                         len = maxlen;
 814
 815                 if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
 816                         rcode = 1;
 817                 buffer += len;
 818                 offset += len;
 819         }
 820
 821         return rcode;
 822 }
 823
 824 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
 825 int board_usb_init(int index, enum board_usb_init_type init)
 826 {
 827         char *act = getenv("usbact");
 828         int i;
 829
 830         if ((act == NULL || strcmp(act, "host") == 0) &&
 831             !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
 832                 /* enable power on USB socket */
 833                 out_be32((void*)GPIO1_OR,
 834                          in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
 835
 836         for (i=0; i<1000; i++)
 837                 udelay(1000);
 838
 839         return 0;
 840 }
 841
 842 int usb_board_stop(void)
 843 {
 844         /* disable power on USB socket */
 845         out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
 846         return 0;
 847 }
 848
 849 int board_usb_cleanup(int index, enum board_usb_init_type init)
 850 {
 851         return usb_board_stop();
 852 }
 853 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
 854
 855 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 856 void ft_board_setup(void *blob, bd_t *bd)
 857 {
 858         int rc;
 859
 860         __ft_board_setup(blob, bd);
 861
 862         /*
 863          * Disable PCI in non-monarch mode.
 864          */
 865         if (!is_monarch()) {
 866                 rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
 867                                           "disabled", sizeof("disabled"), 1);
 868                 if (rc) {
 869                         printf("Unable to update property status in PCI node, err=%s\n",
 870                                fdt_strerror(rc));
 871                 }
 872         }
 873 }
 874 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */