board/esg/ima3-mx53/ima3-mx53.c

   1 /*
   2  * (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
   3  *
   4  * (C) Copyright 2010 Freescale Semiconductor, Inc.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc.
  22  */
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm/arch/crm_regs.h>
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/iomux-mx53.h>
  30 #include <asm/errno.h>
  31 #include <netdev.h>
  32 #include <mmc.h>
  33 #include <fsl_esdhc.h>
  34 #include <asm/gpio.h>
  35
  36 /* NOR flash configuration */
  37 #define IMA3_MX53_CS0GCR1       (CSEN | DSZ(2))
  38 #define IMA3_MX53_CS0GCR2       0
  39 #define IMA3_MX53_CS0RCR1       (RCSN(2) | OEN(1) | RWSC(15))
  40 #define IMA3_MX53_CS0RCR2       0
  41 #define IMA3_MX53_CS0WCR1       (WBED1 | WCSN(2) | WEN(1) | WWSC(15))
  42 #define IMA3_MX53_CS0WCR2       0
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 static void weim_nor_settings(void)
  47 {
  48         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
  49
  50         writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1);
  51         writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2);
  52         writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1);
  53         writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2);
  54         writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1);
  55         writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2);
  56         writel(0x0, &weim_regs->wcr);
  57
  58         set_chipselect_size(CS0_128);
  59 }
  60
  61 int dram_init(void)
  62 {
  63         gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
  64                         PHYS_SDRAM_1_SIZE);
  65         return 0;
  66 }
  67
  68 #define UART_PAD_CTRL   (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  69                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  70
  71 static void setup_iomux_uart(void)
  72 {
  73         static const iomux_v3_cfg_t uart_pads[] = {
  74                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__UART4_RXD_MUX, UART_PAD_CTRL),
  75                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__UART4_TXD_MUX, UART_PAD_CTRL),
  76         };
  77
  78         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  79 }
  80
  81 static void setup_iomux_fec(void)
  82 {
  83         static const iomux_v3_cfg_t fec_pads[] = {
  84                 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  85                         PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  86                 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  87                 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
  88                                 PAD_CTL_HYS | PAD_CTL_PKE),
  89                 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
  90                                 PAD_CTL_HYS | PAD_CTL_PKE),
  91                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  92                                 PAD_CTL_HYS | PAD_CTL_PKE),
  93                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
  94                                 PAD_CTL_HYS | PAD_CTL_PKE),
  95                 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
  96                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
  97                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
  98                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
  99                 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
 100                 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
 101                                 PAD_CTL_HYS | PAD_CTL_PKE),
 102                 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 103                                 PAD_CTL_HYS | PAD_CTL_PKE),
 104                 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
 105                                 PAD_CTL_HYS | PAD_CTL_PKE),
 106                 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
 107                                 PAD_CTL_HYS | PAD_CTL_PKE),
 108                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
 109                                 PAD_CTL_HYS | PAD_CTL_PKE),
 110                 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
 111                                 PAD_CTL_HYS | PAD_CTL_PKE),
 112         };
 113
 114         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 115 }
 116
 117 #ifdef CONFIG_FSL_ESDHC
 118 struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR };
 119
 120 int board_mmc_getcd(struct mmc *mmc)
 121 {
 122         int ret;
 123
 124         ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
 125
 126         return ret;
 127 }
 128
 129 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 130                                  PAD_CTL_PUS_100K_UP)
 131 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 132                                  PAD_CTL_DSE_HIGH)
 133 #define SD_CD_PAD_CTRL          (PAD_CTL_DSE_HIGH | PAD_CTL_HYS | PAD_CTL_PKE)
 134
 135 int board_mmc_init(bd_t *bis)
 136 {
 137         static const iomux_v3_cfg_t sd1_pads[] = {
 138                 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 139                 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
 140                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 141                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 142                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 143                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 144                 NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, SD_CD_PAD_CTRL),
 145         };
 146
 147         imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 148         gpio_direction_input(IMX_GPIO_NR(1, 1));
 149
 150         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 151         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 152 }
 153 #endif
 154
 155 #define SPI_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
 156
 157 static void setup_iomux_spi(void)
 158 {
 159         static const iomux_v3_cfg_t spi_pads[] = {
 160                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL),
 161                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL),
 162                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL),
 163                 /* SSEL 0 */
 164                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__GPIO5_29, SPI_PAD_CTRL),
 165         };
 166
 167         imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
 168         gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
 169 }
 170
 171 int board_early_init_f(void)
 172 {
 173         /* configure I/O pads */
 174         setup_iomux_uart();
 175         setup_iomux_fec();
 176
 177         weim_nor_settings();
 178
 179         /* configure spi */
 180         setup_iomux_spi();
 181
 182         return 0;
 183 }
 184
 185 int board_init(void)
 186 {
 187         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 188
 189         mxc_set_sata_internal_clock();
 190
 191         return 0;
 192 }
 193
 194 #if defined(CONFIG_RESET_PHY_R)
 195 #include <miiphy.h>
 196
 197 void reset_phy(void)
 198 {
 199         unsigned short reg;
 200
 201         /* reset the phy */
 202         miiphy_reset("FEC", CONFIG_PHY_ADDR);
 203
 204         /* set hard link to 100Mbit, full-duplex */
 205         miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, &reg);
 206         reg &= ~BMCR_ANENABLE;
 207         reg |= (BMCR_SPEED100 | BMCR_FULLDPLX);
 208         miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg);
 209
 210         miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, &reg);
 211         reg |= (1 << 5);
 212         miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg);
 213 }
 214 #endif
 215
 216 int checkboard(void)
 217 {
 218         puts("Board: IMA3_MX53\n");
 219
 220         return 0;
 221 }