board/freescale/corenet_ds/pci.c

   1 /*
   2  * Copyright 2007-2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/fsl_pci.h>
  27 #include <libfdt.h>
  28 #include <fdt_support.h>
  29 #include <asm/fsl_serdes.h>
  30
  31 #ifdef CONFIG_PCIE1
  32 static struct pci_controller pcie1_hose;
  33 #endif
  34
  35 #ifdef CONFIG_PCIE2
  36 static struct pci_controller pcie2_hose;
  37 #endif
  38
  39 #ifdef CONFIG_PCIE3
  40 static struct pci_controller pcie3_hose;
  41 #endif
  42
  43 void pci_init_board(void)
  44 {
  45         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  46         struct fsl_pci_info pci_info[3];
  47         u32 devdisr;
  48         int first_free_busno = 0;
  49         int num = 0;
  50
  51         int pcie_ep, pcie_configured;
  52
  53         devdisr = in_be32(&gur->devdisr);
  54
  55         debug ("   pci_init_board: devdisr=%x\n", devdisr);
  56
  57 #ifdef CONFIG_PCIE1
  58         pcie_configured = is_serdes_configured(PCIE1);
  59
  60         if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE1)) {
  61                 set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M,
  62                                 LAW_TRGT_IF_PCIE_1);
  63                 set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
  64                                 LAW_TRGT_IF_PCIE_1);
  65                 SET_STD_PCIE_INFO(pci_info[num], 1);
  66                 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
  67                 printf("    PCIE1 connected to Slot 1 as %s (base addr %lx)\n",
  68                                 pcie_ep ? "End Point" : "Root Complex",
  69                                 pci_info[num].regs);
  70                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
  71                                 &pcie1_hose, first_free_busno);
  72         } else {
  73                 printf ("    PCIE1: disabled\n");
  74         }
  75 #else
  76         setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */
  77 #endif
  78
  79 #ifdef CONFIG_PCIE2
  80         pcie_configured = is_serdes_configured(PCIE2);
  81
  82         if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE2)) {
  83                 set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M,
  84                                 LAW_TRGT_IF_PCIE_2);
  85                 set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
  86                                 LAW_TRGT_IF_PCIE_2);
  87                 SET_STD_PCIE_INFO(pci_info[num], 2);
  88                 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
  89                 printf("    PCIE2 connected to Slot 3 as %s (base addr %lx)\n",
  90                                 pcie_ep ? "End Point" : "Root Complex",
  91                                 pci_info[num].regs);
  92                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
  93                                 &pcie2_hose, first_free_busno);
  94         } else {
  95                 printf ("    PCIE2: disabled\n");
  96         }
  97 #else
  98         setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */
  99 #endif
 100
 101 #ifdef CONFIG_PCIE3
 102         pcie_configured = is_serdes_configured(PCIE3);
 103
 104         if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE3)) {
 105                 set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
 106                                 LAW_TRGT_IF_PCIE_3);
 107                 set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
 108                                 LAW_TRGT_IF_PCIE_3);
 109                 SET_STD_PCIE_INFO(pci_info[num], 3);
 110                 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
 111                 printf("    PCIE3 connected to Slot 2 as %s (base addr %lx)\n",
 112                                 pcie_ep ? "End Point" : "Root Complex",
 113                                 pci_info[num].regs);
 114                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 115                                 &pcie3_hose, first_free_busno);
 116         } else {
 117                 printf ("    PCIE3: disabled\n");
 118         }
 119 #else
 120         setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
 121 #endif
 122 }
 123
 124 void pci_of_setup(void *blob, bd_t *bd)
 125 {
 126         FT_FSL_PCI_SETUP;
 127 }