board/freescale/corenet_ds/pci.c

   1 /*
   2  * Copyright 2007-2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/fsl_pci.h>
  27 #include <libfdt.h>
  28 #include <fdt_support.h>
  29 #include <asm/fsl_serdes.h>
  30
  31 #ifdef CONFIG_PCIE1
  32 static struct pci_controller pcie1_hose;
  33 #endif
  34
  35 #ifdef CONFIG_PCIE2
  36 static struct pci_controller pcie2_hose;
  37 #endif
  38
  39 #ifdef CONFIG_PCIE3
  40 static struct pci_controller pcie3_hose;
  41 #endif
  42
  43 #ifdef CONFIG_PCIE4
  44 static struct pci_controller pcie4_hose;
  45 #endif
  46
  47 void pci_init_board(void)
  48 {
  49         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  50         struct fsl_pci_info pci_info[4];
  51         u32 devdisr;
  52         int first_free_busno = 0;
  53         int num = 0;
  54
  55         int pcie_ep, pcie_configured;
  56
  57         devdisr = in_be32(&gur->devdisr);
  58
  59         debug ("   pci_init_board: devdisr=%x\n", devdisr);
  60
  61 #ifdef CONFIG_PCIE1
  62         pcie_configured = is_serdes_configured(PCIE1);
  63
  64         if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE1)) {
  65                 set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M,
  66                                 LAW_TRGT_IF_PCIE_1);
  67                 set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
  68                                 LAW_TRGT_IF_PCIE_1);
  69                 SET_STD_PCIE_INFO(pci_info[num], 1);
  70                 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
  71                 printf("PCIE1: connected to Slot 1 as %s (base addr %lx)\n",
  72                                 pcie_ep ? "End Point" : "Root Complex",
  73                                 pci_info[num].regs);
  74                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
  75                                 &pcie1_hose, first_free_busno);
  76         } else {
  77                 printf("PCIE1: disabled\n");
  78         }
  79 #else
  80         setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */
  81 #endif
  82
  83 #ifdef CONFIG_PCIE2
  84         pcie_configured = is_serdes_configured(PCIE2);
  85
  86         if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE2)) {
  87                 set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M,
  88                                 LAW_TRGT_IF_PCIE_2);
  89                 set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
  90                                 LAW_TRGT_IF_PCIE_2);
  91                 SET_STD_PCIE_INFO(pci_info[num], 2);
  92                 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
  93                 printf("PCIE2: connected to Slot 3 as %s (base addr %lx)\n",
  94                                 pcie_ep ? "End Point" : "Root Complex",
  95                                 pci_info[num].regs);
  96                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
  97                                 &pcie2_hose, first_free_busno);
  98         } else {
  99                 printf("PCIE2: disabled\n");
 100         }
 101 #else
 102         setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */
 103 #endif
 104
 105 #ifdef CONFIG_PCIE3
 106         pcie_configured = is_serdes_configured(PCIE3);
 107
 108         if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE3)) {
 109                 set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
 110                                 LAW_TRGT_IF_PCIE_3);
 111                 set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
 112                                 LAW_TRGT_IF_PCIE_3);
 113                 SET_STD_PCIE_INFO(pci_info[num], 3);
 114                 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
 115                 printf("PCIE3: connected to Slot 2 as %s (base addr %lx)\n",
 116                                 pcie_ep ? "End Point" : "Root Complex",
 117                                 pci_info[num].regs);
 118                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 119                                 &pcie3_hose, first_free_busno);
 120         } else {
 121                 printf("PCIE3: disabled\n");
 122         }
 123 #else
 124         setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
 125 #endif
 126
 127 #ifdef CONFIG_PCIE4
 128         pcie_configured = is_serdes_configured(PCIE4);
 129
 130         if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) {
 131                 set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M,
 132                                 LAW_TRGT_IF_PCIE_4);
 133                 set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K,
 134                                 LAW_TRGT_IF_PCIE_4);
 135                 SET_STD_PCIE_INFO(pci_info[num], 4);
 136                 pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs);
 137                 printf("PCIE4: connected to as %s (base addr %lx)\n",
 138                                 pcie_ep ? "End Point" : "Root Complex",
 139                                 pci_info[num].regs);
 140                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 141                                 &pcie4_hose, first_free_busno);
 142         } else {
 143                 printf("PCIE4: disabled\n");
 144         }
 145 #else
 146         setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */
 147 #endif
 148 }
 149
 150 void pci_of_setup(void *blob, bd_t *bd)
 151 {
 152         FT_FSL_PCI_SETUP;
 153 }