board/freescale/ls1021aqds/ls1021aqds.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/ns_access.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/ls102xa_stream_id.h>
  15 #include <hwconfig.h>
  16 #include <mmc.h>
  17 #include <fsl_esdhc.h>
  18 #include <fsl_ifc.h>
  19 #include <fsl_sec.h>
  20 #include <spl.h>
  21
  22 #include "../common/sleep.h"
  23 #include "../common/qixis.h"
  24 #include "ls1021aqds_qixis.h"
  25 #ifdef CONFIG_U_QE
  26 #include "../../../drivers/qe/qe.h"
  27 #endif
  28
  29 #define PIN_MUX_SEL_CAN         0x03
  30 #define PIN_MUX_SEL_IIC2        0xa0
  31 #define PIN_MUX_SEL_RGMII       0x00
  32 #define PIN_MUX_SEL_SAI         0x0c
  33 #define PIN_MUX_SEL_SDHC        0x00
  34
  35 #define SET_SDHC_MUX_SEL(reg, value)    ((reg & 0x0f) | value)
  36 #define SET_EC_MUX_SEL(reg, value)      ((reg & 0xf0) | value)
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 enum {
  40         MUX_TYPE_CAN,
  41         MUX_TYPE_IIC2,
  42         MUX_TYPE_RGMII,
  43         MUX_TYPE_SAI,
  44         MUX_TYPE_SDHC,
  45         MUX_TYPE_SD_PCI4,
  46         MUX_TYPE_SD_PC_SA_SG_SG,
  47         MUX_TYPE_SD_PC_SA_PC_SG,
  48         MUX_TYPE_SD_PC_SG_SG,
  49 };
  50
  51 enum {
  52         GE0_CLK125,
  53         GE2_CLK125,
  54         GE1_CLK125,
  55 };
  56
  57 int checkboard(void)
  58 {
  59 #ifndef CONFIG_QSPI_BOOT
  60         char buf[64];
  61 #endif
  62 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
  63         u8 sw;
  64 #endif
  65
  66         puts("Board: LS1021AQDS\n");
  67
  68 #ifdef CONFIG_SD_BOOT
  69         puts("SD\n");
  70 #elif CONFIG_QSPI_BOOT
  71         puts("QSPI\n");
  72 #else
  73         sw = QIXIS_READ(brdcfg[0]);
  74         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  75
  76         if (sw < 0x8)
  77                 printf("vBank: %d\n", sw);
  78         else if (sw == 0x8)
  79                 puts("PromJet\n");
  80         else if (sw == 0x9)
  81                 puts("NAND\n");
  82         else if (sw == 0x15)
  83                 printf("IFCCard\n");
  84         else
  85                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  86 #endif
  87
  88 #ifndef CONFIG_QSPI_BOOT
  89         printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
  90                QIXIS_READ(id), QIXIS_READ(arch));
  91
  92         printf("FPGA:  v%d (%s), build %d\n",
  93                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  94                (int)qixis_read_minor());
  95 #endif
  96
  97         return 0;
  98 }
  99
 100 unsigned long get_board_sys_clk(void)
 101 {
 102         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 103
 104         switch (sysclk_conf & 0x0f) {
 105         case QIXIS_SYSCLK_64:
 106                 return 64000000;
 107         case QIXIS_SYSCLK_83:
 108                 return 83333333;
 109         case QIXIS_SYSCLK_100:
 110                 return 100000000;
 111         case QIXIS_SYSCLK_125:
 112                 return 125000000;
 113         case QIXIS_SYSCLK_133:
 114                 return 133333333;
 115         case QIXIS_SYSCLK_150:
 116                 return 150000000;
 117         case QIXIS_SYSCLK_160:
 118                 return 160000000;
 119         case QIXIS_SYSCLK_166:
 120                 return 166666666;
 121         }
 122         return 66666666;
 123 }
 124
 125 unsigned long get_board_ddr_clk(void)
 126 {
 127         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 128
 129         switch ((ddrclk_conf & 0x30) >> 4) {
 130         case QIXIS_DDRCLK_100:
 131                 return 100000000;
 132         case QIXIS_DDRCLK_125:
 133                 return 125000000;
 134         case QIXIS_DDRCLK_133:
 135                 return 133333333;
 136         }
 137         return 66666666;
 138 }
 139
 140 unsigned int get_soc_major_rev(void)
 141 {
 142         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 143         unsigned int svr, major;
 144
 145         svr = in_be32(&gur->svr);
 146         major = SVR_MAJ(svr);
 147
 148         return major;
 149 }
 150
 151 int select_i2c_ch_pca9547(u8 ch)
 152 {
 153         int ret;
 154
 155         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 156         if (ret) {
 157                 puts("PCA: failed to select proper channel\n");
 158                 return ret;
 159         }
 160
 161         return 0;
 162 }
 163
 164 int dram_init(void)
 165 {
 166         /*
 167          * When resuming from deep sleep, the I2C channel may not be
 168          * in the default channel. So, switch to the default channel
 169          * before accessing DDR SPD.
 170          */
 171         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 172         gd->ram_size = initdram(0);
 173
 174         return 0;
 175 }
 176
 177 #ifdef CONFIG_FSL_ESDHC
 178 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 179         {CONFIG_SYS_FSL_ESDHC_ADDR},
 180 };
 181
 182 int board_mmc_init(bd_t *bis)
 183 {
 184         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 185
 186         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 187 }
 188 #endif
 189
 190 int board_early_init_f(void)
 191 {
 192         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 193         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 194         unsigned int major;
 195
 196 #ifdef CONFIG_TSEC_ENET
 197         out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 198 #endif
 199
 200 #ifdef CONFIG_FSL_IFC
 201         init_early_memctl_regs();
 202 #endif
 203
 204 #ifdef CONFIG_FSL_QSPI
 205         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 206 #endif
 207
 208 #ifdef CONFIG_FSL_DCU_FB
 209         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 210 #endif
 211
 212         /* Configure Little endian for SAI, ASRC and SPDIF */
 213         out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
 214
 215         /*
 216          * Enable snoop requests and DVM message requests for
 217          * Slave insterface S4 (A7 core cluster)
 218          */
 219         out_le32(&cci->slave[4].snoop_ctrl,
 220                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 221
 222         major = get_soc_major_rev();
 223         if (major == SOC_MAJOR_VER_1_0) {
 224                 /*
 225                  * Set CCI-400 Slave interface S1, S2 Shareable Override
 226                  * Register All transactions are treated as non-shareable
 227                  */
 228                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 229                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 230
 231                 /* Workaround for the issue that DDR could not respond to
 232                  * barrier transaction which is generated by executing DSB/ISB
 233                  * instruction. Set CCI-400 control override register to
 234                  * terminate the barrier transaction. After DDR is initialized,
 235                  * allow barrier transaction to DDR again */
 236                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 237         }
 238
 239 #if defined(CONFIG_DEEP_SLEEP)
 240         if (is_warm_boot())
 241                 fsl_dp_disable_console();
 242 #endif
 243
 244         return 0;
 245 }
 246
 247 #ifdef CONFIG_SPL_BUILD
 248 void board_init_f(ulong dummy)
 249 {
 250         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 251         unsigned int major;
 252
 253 #ifdef CONFIG_NAND_BOOT
 254         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 255         u32 porsr1, pinctl;
 256
 257         /*
 258          * There is LS1 SoC issue where NOR, FPGA are inaccessible during
 259          * NAND boot because IFC signals > IFC_AD7 are not enabled.
 260          * This workaround changes RCW source to make all signals enabled.
 261          */
 262         porsr1 = in_be32(&gur->porsr1);
 263         pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
 264                  DCFG_CCSR_PORSR1_RCW_SRC_I2C);
 265         out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 266                  pinctl);
 267 #endif
 268
 269         /* Clear the BSS */
 270         memset(__bss_start, 0, __bss_end - __bss_start);
 271
 272 #ifdef CONFIG_FSL_IFC
 273         init_early_memctl_regs();
 274 #endif
 275
 276         get_clocks();
 277
 278 #if defined(CONFIG_DEEP_SLEEP)
 279         if (is_warm_boot())
 280                 fsl_dp_disable_console();
 281 #endif
 282
 283         preloader_console_init();
 284
 285 #ifdef CONFIG_SPL_I2C_SUPPORT
 286         i2c_init_all();
 287 #endif
 288
 289         major = get_soc_major_rev();
 290         if (major == SOC_MAJOR_VER_1_0)
 291                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 292
 293         dram_init();
 294
 295         board_init_r(NULL, 0);
 296 }
 297 #endif
 298
 299 void config_etseccm_source(int etsec_gtx_125_mux)
 300 {
 301         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 302
 303         switch (etsec_gtx_125_mux) {
 304         case GE0_CLK125:
 305                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
 306                 debug("etseccm set to GE0_CLK125\n");
 307                 break;
 308
 309         case GE2_CLK125:
 310                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 311                 debug("etseccm set to GE2_CLK125\n");
 312                 break;
 313
 314         case GE1_CLK125:
 315                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
 316                 debug("etseccm set to GE1_CLK125\n");
 317                 break;
 318
 319         default:
 320                 printf("Error! trying to set etseccm to invalid value\n");
 321                 break;
 322         }
 323 }
 324
 325 int config_board_mux(int ctrl_type)
 326 {
 327         u8 reg12, reg14;
 328
 329         reg12 = QIXIS_READ(brdcfg[12]);
 330         reg14 = QIXIS_READ(brdcfg[14]);
 331
 332         switch (ctrl_type) {
 333         case MUX_TYPE_CAN:
 334                 config_etseccm_source(GE2_CLK125);
 335                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
 336                 break;
 337         case MUX_TYPE_IIC2:
 338                 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
 339                 break;
 340         case MUX_TYPE_RGMII:
 341                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
 342                 break;
 343         case MUX_TYPE_SAI:
 344                 config_etseccm_source(GE2_CLK125);
 345                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
 346                 break;
 347         case MUX_TYPE_SDHC:
 348                 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
 349                 break;
 350         case MUX_TYPE_SD_PCI4:
 351                 reg12 = 0x38;
 352                 break;
 353         case MUX_TYPE_SD_PC_SA_SG_SG:
 354                 reg12 = 0x01;
 355                 break;
 356         case MUX_TYPE_SD_PC_SA_PC_SG:
 357                 reg12 = 0x01;
 358                 break;
 359         case MUX_TYPE_SD_PC_SG_SG:
 360                 reg12 = 0x21;
 361                 break;
 362         default:
 363                 printf("Wrong mux interface type\n");
 364                 return -1;
 365         }
 366
 367         QIXIS_WRITE(brdcfg[12], reg12);
 368         QIXIS_WRITE(brdcfg[14], reg14);
 369
 370         return 0;
 371 }
 372
 373 int config_serdes_mux(void)
 374 {
 375         struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
 376         u32 cfg;
 377
 378         cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 379         cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 380
 381         switch (cfg) {
 382         case 0x0:
 383                 config_board_mux(MUX_TYPE_SD_PCI4);
 384                 break;
 385         case 0x30:
 386                 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
 387                 break;
 388         case 0x60:
 389                 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
 390                 break;
 391         case 0x70:
 392                 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
 393                 break;
 394         default:
 395                 printf("SRDS1 prtcl:0x%x\n", cfg);
 396                 break;
 397         }
 398
 399         return 0;
 400 }
 401
 402 int misc_init_r(void)
 403 {
 404         int conflict_flag;
 405
 406         /* some signals can not enable simultaneous*/
 407         conflict_flag = 0;
 408         if (hwconfig("sdhc"))
 409                 conflict_flag++;
 410         if (hwconfig("iic2"))
 411                 conflict_flag++;
 412         if (conflict_flag > 1) {
 413                 printf("WARNING: pin conflict !\n");
 414                 return 0;
 415         }
 416
 417         conflict_flag = 0;
 418         if (hwconfig("rgmii"))
 419                 conflict_flag++;
 420         if (hwconfig("can"))
 421                 conflict_flag++;
 422         if (hwconfig("sai"))
 423                 conflict_flag++;
 424         if (conflict_flag > 1) {
 425                 printf("WARNING: pin conflict !\n");
 426                 return 0;
 427         }
 428
 429         if (hwconfig("can"))
 430                 config_board_mux(MUX_TYPE_CAN);
 431         else if (hwconfig("rgmii"))
 432                 config_board_mux(MUX_TYPE_RGMII);
 433         else if (hwconfig("sai"))
 434                 config_board_mux(MUX_TYPE_SAI);
 435
 436         if (hwconfig("iic2"))
 437                 config_board_mux(MUX_TYPE_IIC2);
 438         else if (hwconfig("sdhc"))
 439                 config_board_mux(MUX_TYPE_SDHC);
 440
 441 #ifdef CONFIG_FSL_CAAM
 442         return sec_init();
 443 #endif
 444         return 0;
 445 }
 446
 447 #ifdef CONFIG_LS102XA_NS_ACCESS
 448 static struct csu_ns_dev ns_dev[] = {
 449         { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
 450         { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
 451         { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
 452         { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
 453         { CSU_CSLX_OCRAM, CSU_ALL_RW },
 454         { CSU_CSLX_GIC, CSU_ALL_RW },
 455         { CSU_CSLX_PCIE1, CSU_ALL_RW },
 456         { CSU_CSLX_OCRAM2, CSU_ALL_RW },
 457         { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
 458         { CSU_CSLX_PCIE2, CSU_ALL_RW },
 459         { CSU_CSLX_SATA, CSU_ALL_RW },
 460         { CSU_CSLX_USB3, CSU_ALL_RW },
 461         { CSU_CSLX_SERDES, CSU_ALL_RW },
 462         { CSU_CSLX_QDMA, CSU_ALL_RW },
 463         { CSU_CSLX_LPUART2, CSU_ALL_RW },
 464         { CSU_CSLX_LPUART1, CSU_ALL_RW },
 465         { CSU_CSLX_LPUART4, CSU_ALL_RW },
 466         { CSU_CSLX_LPUART3, CSU_ALL_RW },
 467         { CSU_CSLX_LPUART6, CSU_ALL_RW },
 468         { CSU_CSLX_LPUART5, CSU_ALL_RW },
 469         { CSU_CSLX_DSPI2, CSU_ALL_RW },
 470         { CSU_CSLX_DSPI1, CSU_ALL_RW },
 471         { CSU_CSLX_QSPI, CSU_ALL_RW },
 472         { CSU_CSLX_ESDHC, CSU_ALL_RW },
 473         { CSU_CSLX_2D_ACE, CSU_ALL_RW },
 474         { CSU_CSLX_IFC, CSU_ALL_RW },
 475         { CSU_CSLX_I2C1, CSU_ALL_RW },
 476         { CSU_CSLX_USB2, CSU_ALL_RW },
 477         { CSU_CSLX_I2C3, CSU_ALL_RW },
 478         { CSU_CSLX_I2C2, CSU_ALL_RW },
 479         { CSU_CSLX_DUART2, CSU_ALL_RW },
 480         { CSU_CSLX_DUART1, CSU_ALL_RW },
 481         { CSU_CSLX_WDT2, CSU_ALL_RW },
 482         { CSU_CSLX_WDT1, CSU_ALL_RW },
 483         { CSU_CSLX_EDMA, CSU_ALL_RW },
 484         { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
 485         { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
 486         { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
 487         { CSU_CSLX_DDR, CSU_ALL_RW },
 488         { CSU_CSLX_QUICC, CSU_ALL_RW },
 489         { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
 490         { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
 491         { CSU_CSLX_SFP, CSU_ALL_RW },
 492         { CSU_CSLX_TMU, CSU_ALL_RW },
 493         { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
 494         { CSU_CSLX_RESERVED0, CSU_ALL_RW },
 495         { CSU_CSLX_ETSEC1, CSU_ALL_RW },
 496         { CSU_CSLX_SEC5_5, CSU_ALL_RW },
 497         { CSU_CSLX_ETSEC3, CSU_ALL_RW },
 498         { CSU_CSLX_ETSEC2, CSU_ALL_RW },
 499         { CSU_CSLX_GPIO2, CSU_ALL_RW },
 500         { CSU_CSLX_GPIO1, CSU_ALL_RW },
 501         { CSU_CSLX_GPIO4, CSU_ALL_RW },
 502         { CSU_CSLX_GPIO3, CSU_ALL_RW },
 503         { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
 504         { CSU_CSLX_CSU, CSU_ALL_RW },
 505         { CSU_CSLX_ASRC, CSU_ALL_RW },
 506         { CSU_CSLX_SPDIF, CSU_ALL_RW },
 507         { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
 508         { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
 509         { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
 510         { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
 511         { CSU_CSLX_SAI2, CSU_ALL_RW },
 512         { CSU_CSLX_SAI1, CSU_ALL_RW },
 513         { CSU_CSLX_SAI4, CSU_ALL_RW },
 514         { CSU_CSLX_SAI3, CSU_ALL_RW },
 515         { CSU_CSLX_FTM2, CSU_ALL_RW },
 516         { CSU_CSLX_FTM1, CSU_ALL_RW },
 517         { CSU_CSLX_FTM4, CSU_ALL_RW },
 518         { CSU_CSLX_FTM3, CSU_ALL_RW },
 519         { CSU_CSLX_FTM6, CSU_ALL_RW },
 520         { CSU_CSLX_FTM5, CSU_ALL_RW },
 521         { CSU_CSLX_FTM8, CSU_ALL_RW },
 522         { CSU_CSLX_FTM7, CSU_ALL_RW },
 523         { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
 524         { CSU_CSLX_EPU, CSU_ALL_RW },
 525         { CSU_CSLX_GDI, CSU_ALL_RW },
 526         { CSU_CSLX_DDI, CSU_ALL_RW },
 527         { CSU_CSLX_RESERVED1, CSU_ALL_RW },
 528         { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
 529         { CSU_CSLX_RESERVED2, CSU_ALL_RW },
 530 };
 531 #endif
 532
 533 struct liodn_id_table sec_liodn_tbl[] = {
 534         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
 535         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
 536         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
 537         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
 538         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
 539         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
 540         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
 541         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
 542         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
 543         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
 544         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
 545         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
 546         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
 547         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
 548         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
 549         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
 550 };
 551
 552 struct smmu_stream_id dev_stream_id[] = {
 553         { 0x100, 0x01, "ETSEC MAC1" },
 554         { 0x104, 0x02, "ETSEC MAC2" },
 555         { 0x108, 0x03, "ETSEC MAC3" },
 556         { 0x10c, 0x04, "PEX1" },
 557         { 0x110, 0x05, "PEX2" },
 558         { 0x114, 0x06, "qDMA" },
 559         { 0x118, 0x07, "SATA" },
 560         { 0x11c, 0x08, "USB3" },
 561         { 0x120, 0x09, "QE" },
 562         { 0x124, 0x0a, "eSDHC" },
 563         { 0x128, 0x0b, "eMA" },
 564         { 0x14c, 0x0c, "2D-ACE" },
 565         { 0x150, 0x0d, "USB2" },
 566         { 0x18c, 0x0e, "DEBUG" },
 567 };
 568
 569 int board_init(void)
 570 {
 571         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 572         unsigned int major;
 573
 574         major = get_soc_major_rev();
 575         if (major == SOC_MAJOR_VER_1_0) {
 576                 /* Set CCI-400 control override register to
 577                  * enable barrier transaction */
 578                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 579         }
 580
 581         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 582
 583 #ifndef CONFIG_SYS_FSL_NO_SERDES
 584         fsl_serdes_init();
 585         config_serdes_mux();
 586 #endif
 587
 588         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 589                                       ARRAY_SIZE(sec_liodn_tbl));
 590         ls102xa_config_smmu_stream_id(dev_stream_id,
 591                                       ARRAY_SIZE(dev_stream_id));
 592
 593 #ifdef CONFIG_LS102XA_NS_ACCESS
 594         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 595 #endif
 596
 597 #ifdef CONFIG_U_QE
 598         u_qe_init();
 599 #endif
 600
 601         return 0;
 602 }
 603
 604 #if defined(CONFIG_DEEP_SLEEP)
 605 void board_sleep_prepare(void)
 606 {
 607         struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
 608         unsigned int major;
 609
 610         major = get_soc_major_rev();
 611         if (major == SOC_MAJOR_VER_1_0) {
 612                 /* Set CCI-400 control override register to
 613                  * enable barrier transaction */
 614                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 615         }
 616
 617
 618 #ifdef CONFIG_LS102XA_NS_ACCESS
 619         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 620 #endif
 621 }
 622 #endif
 623
 624 int ft_board_setup(void *blob, bd_t *bd)
 625 {
 626         ft_cpu_setup(blob, bd);
 627
 628 #ifdef CONFIG_PCI
 629         ft_pci_setup(blob, bd);
 630 #endif
 631
 632         return 0;
 633 }
 634
 635 u8 flash_read8(void *addr)
 636 {
 637         return __raw_readb(addr + 1);
 638 }
 639
 640 void flash_write16(u16 val, void *addr)
 641 {
 642         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 643
 644         __raw_writew(shftval, addr);
 645 }
 646
 647 u16 flash_read16(void *addr)
 648 {
 649         u16 val = __raw_readw(addr);
 650
 651         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 652 }