board/freescale/ls1021atwr/ls1021atwr.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/ns_access.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/ls102xa_stream_id.h>
  15 #include <hwconfig.h>
  16 #include <mmc.h>
  17 #include <fsl_esdhc.h>
  18 #include <fsl_ifc.h>
  19 #include <fsl_immap.h>
  20 #include <netdev.h>
  21 #include <fsl_mdio.h>
  22 #include <tsec.h>
  23 #include <fsl_sec.h>
  24 #include <spl.h>
  25 #include "../common/sleep.h"
  26 #ifdef CONFIG_U_QE
  27 #include "../../../drivers/qe/qe.h"
  28 #endif
  29
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #define VERSION_MASK            0x00FF
  34 #define BANK_MASK               0x0001
  35 #define CONFIG_RESET            0x1
  36 #define INIT_RESET              0x1
  37
  38 #define CPLD_SET_MUX_SERDES     0x20
  39 #define CPLD_SET_BOOT_BANK      0x40
  40
  41 #define BOOT_FROM_UPPER_BANK    0x0
  42 #define BOOT_FROM_LOWER_BANK    0x1
  43
  44 #define LANEB_SATA              (0x01)
  45 #define LANEB_SGMII1            (0x02)
  46 #define LANEC_SGMII1            (0x04)
  47 #define LANEC_PCIEX1            (0x08)
  48 #define LANED_PCIEX2            (0x10)
  49 #define LANED_SGMII2            (0x20)
  50
  51 #define MASK_LANE_B             0x1
  52 #define MASK_LANE_C             0x2
  53 #define MASK_LANE_D             0x4
  54 #define MASK_SGMII              0x8
  55
  56 #define KEEP_STATUS             0x0
  57 #define NEED_RESET              0x1
  58
  59 #define SOFT_MUX_ON_I2C3_IFC    0x2
  60 #define SOFT_MUX_ON_CAN3_USB2   0x8
  61 #define SOFT_MUX_ON_QE_LCD      0x10
  62
  63 #define PIN_I2C3_IFC_MUX_I2C3   0x0
  64 #define PIN_I2C3_IFC_MUX_IFC    0x1
  65 #define PIN_CAN3_USB2_MUX_USB2  0x0
  66 #define PIN_CAN3_USB2_MUX_CAN3  0x1
  67 #define PIN_QE_LCD_MUX_LCD      0x0
  68 #define PIN_QE_LCD_MUX_QE       0x1
  69
  70 struct cpld_data {
  71         u8 cpld_ver;            /* cpld revision */
  72         u8 cpld_ver_sub;        /* cpld sub revision */
  73         u8 pcba_ver;            /* pcb revision number */
  74         u8 system_rst;          /* reset system by cpld */
  75         u8 soft_mux_on;         /* CPLD override physical switches Enable */
  76         u8 cfg_rcw_src1;        /* Reset config word 1 */
  77         u8 cfg_rcw_src2;        /* Reset config word 2 */
  78         u8 vbank;               /* Flash bank selection Control */
  79         u8 gpio;                /* GPIO for TWR-ELEV */
  80         u8 i2c3_ifc_mux;
  81         u8 mux_spi2;
  82         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
  83         u8 qe_lcd_mux;          /* QE and LCD Selection */
  84         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
  85         u8 global_rst;          /* reset with init CPLD reg to default */
  86         u8 rev1;                /* Reserved */
  87         u8 rev2;                /* Reserved */
  88 };
  89
  90 #ifndef CONFIG_QSPI_BOOT
  91 static void convert_serdes_mux(int type, int need_reset);
  92
  93 void cpld_show(void)
  94 {
  95         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  96
  97         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
  98                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
  99                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
 100                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
 101                in_8(&cpld_data->vbank) & BANK_MASK);
 102
 103 #ifdef CONFIG_DEBUG
 104         printf("soft_mux_on =%x\n",
 105                in_8(&cpld_data->soft_mux_on));
 106         printf("cfg_rcw_src1 =%x\n",
 107                in_8(&cpld_data->cfg_rcw_src1));
 108         printf("cfg_rcw_src2 =%x\n",
 109                in_8(&cpld_data->cfg_rcw_src2));
 110         printf("vbank =%x\n",
 111                in_8(&cpld_data->vbank));
 112         printf("gpio =%x\n",
 113                in_8(&cpld_data->gpio));
 114         printf("i2c3_ifc_mux =%x\n",
 115                in_8(&cpld_data->i2c3_ifc_mux));
 116         printf("mux_spi2 =%x\n",
 117                in_8(&cpld_data->mux_spi2));
 118         printf("can3_usb2_mux =%x\n",
 119                in_8(&cpld_data->can3_usb2_mux));
 120         printf("qe_lcd_mux =%x\n",
 121                in_8(&cpld_data->qe_lcd_mux));
 122         printf("serdes_mux =%x\n",
 123                in_8(&cpld_data->serdes_mux));
 124 #endif
 125 }
 126 #endif
 127
 128 int checkboard(void)
 129 {
 130         puts("Board: LS1021ATWR\n");
 131 #ifndef CONFIG_QSPI_BOOT
 132         cpld_show();
 133 #endif
 134
 135         return 0;
 136 }
 137
 138 unsigned int get_soc_major_rev(void)
 139 {
 140         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 141         unsigned int svr, major;
 142
 143         svr = in_be32(&gur->svr);
 144         major = SVR_MAJ(svr);
 145
 146         return major;
 147 }
 148
 149 void ddrmc_init(void)
 150 {
 151         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
 152         u32 temp_sdram_cfg;
 153
 154         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 155
 156         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
 157         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
 158
 159         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
 160         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
 161         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
 162         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
 163         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
 164         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
 165
 166 #ifdef CONFIG_DEEP_SLEEP
 167         if (is_warm_boot()) {
 168                 out_be32(&ddr->sdram_cfg_2,
 169                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
 170                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 171                 out_be32(&ddr->init_ext_addr, (1 << 31));
 172
 173                 /* DRAM VRef will not be trained */
 174                 out_be32(&ddr->ddr_cdr2,
 175                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
 176         } else
 177 #endif
 178         {
 179                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
 180                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
 181         }
 182
 183         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
 184         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
 185
 186         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
 187
 188         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
 189
 190         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
 191         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
 192
 193         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
 194
 195         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
 196         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 197
 198         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
 199         udelay(1);
 200
 201 #ifdef CONFIG_DEEP_SLEEP
 202         if (is_warm_boot()) {
 203                 /* enter self-refresh */
 204                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 205                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 206                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 207
 208                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
 209         } else
 210 #endif
 211                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
 212
 213         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
 214
 215 #ifdef CONFIG_DEEP_SLEEP
 216         if (is_warm_boot()) {
 217                 /* exit self-refresh */
 218                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 219                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 220                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 221         }
 222 #endif
 223 }
 224
 225 int dram_init(void)
 226 {
 227 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 228         ddrmc_init();
 229 #endif
 230
 231         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 232
 233 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 234         fsl_dp_resume();
 235 #endif
 236
 237         return 0;
 238 }
 239
 240 #ifdef CONFIG_FSL_ESDHC
 241 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 242         {CONFIG_SYS_FSL_ESDHC_ADDR},
 243 };
 244
 245 int board_mmc_init(bd_t *bis)
 246 {
 247         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 248
 249         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 250 }
 251 #endif
 252
 253 #ifdef CONFIG_TSEC_ENET
 254 int board_eth_init(bd_t *bis)
 255 {
 256         struct fsl_pq_mdio_info mdio_info;
 257         struct tsec_info_struct tsec_info[4];
 258         int num = 0;
 259
 260 #ifdef CONFIG_TSEC1
 261         SET_STD_TSEC_INFO(tsec_info[num], 1);
 262         if (is_serdes_configured(SGMII_TSEC1)) {
 263                 puts("eTSEC1 is in sgmii mode.\n");
 264                 tsec_info[num].flags |= TSEC_SGMII;
 265         }
 266         num++;
 267 #endif
 268 #ifdef CONFIG_TSEC2
 269         SET_STD_TSEC_INFO(tsec_info[num], 2);
 270         if (is_serdes_configured(SGMII_TSEC2)) {
 271                 puts("eTSEC2 is in sgmii mode.\n");
 272                 tsec_info[num].flags |= TSEC_SGMII;
 273         }
 274         num++;
 275 #endif
 276 #ifdef CONFIG_TSEC3
 277         SET_STD_TSEC_INFO(tsec_info[num], 3);
 278         num++;
 279 #endif
 280         if (!num) {
 281                 printf("No TSECs initialized\n");
 282                 return 0;
 283         }
 284
 285         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 286         mdio_info.name = DEFAULT_MII_NAME;
 287         fsl_pq_mdio_init(bis, &mdio_info);
 288
 289         tsec_eth_init(bis, tsec_info, num);
 290
 291         return pci_eth_init(bis);
 292 }
 293 #endif
 294
 295 #ifndef CONFIG_QSPI_BOOT
 296 int config_serdes_mux(void)
 297 {
 298         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 299         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 300
 301         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 302         switch (protocol) {
 303         case 0x10:
 304                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 305                 convert_serdes_mux(LANED_PCIEX2 |
 306                                 LANEC_PCIEX1, KEEP_STATUS);
 307                 break;
 308         case 0x20:
 309                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
 310                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 311                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 312                 break;
 313         case 0x30:
 314                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 315                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
 316                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 317                 break;
 318         case 0x70:
 319                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 320                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 321                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 322                 break;
 323         }
 324
 325         return 0;
 326 }
 327 #endif
 328
 329 #ifndef CONFIG_QSPI_BOOT
 330 int config_board_mux(void)
 331 {
 332         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 333         int conflict_flag;
 334
 335         conflict_flag = 0;
 336         if (hwconfig("i2c3")) {
 337                 conflict_flag++;
 338                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 339                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
 340         }
 341
 342         if (hwconfig("ifc")) {
 343                 conflict_flag++;
 344                 /* some signals can not enable simultaneous*/
 345                 if (conflict_flag > 1)
 346                         goto conflict;
 347                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 348                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
 349         }
 350
 351         conflict_flag = 0;
 352         if (hwconfig("usb2")) {
 353                 conflict_flag++;
 354                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 355                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
 356         }
 357
 358         if (hwconfig("can3")) {
 359                 conflict_flag++;
 360                 /* some signals can not enable simultaneous*/
 361                 if (conflict_flag > 1)
 362                         goto conflict;
 363                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 364                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
 365         }
 366
 367         conflict_flag = 0;
 368         if (hwconfig("lcd")) {
 369                 conflict_flag++;
 370                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 371                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
 372         }
 373
 374         if (hwconfig("qe")) {
 375                 conflict_flag++;
 376                 /* some signals can not enable simultaneous*/
 377                 if (conflict_flag > 1)
 378                         goto conflict;
 379                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 380                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
 381         }
 382
 383         return 0;
 384
 385 conflict:
 386         printf("WARNING: pin conflict! MUX setting may failed!\n");
 387         return 0;
 388 }
 389 #endif
 390
 391 int board_early_init_f(void)
 392 {
 393         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 394         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 395         unsigned int major;
 396
 397 #ifdef CONFIG_TSEC_ENET
 398         out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 399         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 400 #endif
 401
 402 #ifdef CONFIG_FSL_IFC
 403         init_early_memctl_regs();
 404 #endif
 405
 406 #ifdef CONFIG_FSL_DCU_FB
 407         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 408 #endif
 409
 410 #ifdef CONFIG_FSL_QSPI
 411         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 412 #endif
 413
 414         /* Configure Little endian for SAI, ASRC and SPDIF */
 415         out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
 416
 417         /*
 418          * Enable snoop requests and DVM message requests for
 419          * Slave insterface S4 (A7 core cluster)
 420          */
 421         out_le32(&cci->slave[4].snoop_ctrl,
 422                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 423
 424         major = get_soc_major_rev();
 425         if (major == SOC_MAJOR_VER_1_0) {
 426                 /*
 427                  * Set CCI-400 Slave interface S1, S2 Shareable Override
 428                  * Register All transactions are treated as non-shareable
 429                  */
 430                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 431                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 432         }
 433
 434 #if defined(CONFIG_DEEP_SLEEP)
 435         if (is_warm_boot())
 436                 fsl_dp_disable_console();
 437 #endif
 438
 439         return 0;
 440 }
 441
 442 #ifdef CONFIG_SPL_BUILD
 443 void board_init_f(ulong dummy)
 444 {
 445         /* Clear the BSS */
 446         memset(__bss_start, 0, __bss_end - __bss_start);
 447
 448         get_clocks();
 449
 450 #if defined(CONFIG_DEEP_SLEEP)
 451         if (is_warm_boot())
 452                 fsl_dp_disable_console();
 453 #endif
 454
 455         preloader_console_init();
 456
 457         dram_init();
 458
 459         board_init_r(NULL, 0);
 460 }
 461 #endif
 462
 463 #ifdef CONFIG_LS102XA_NS_ACCESS
 464 static struct csu_ns_dev ns_dev[] = {
 465         { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
 466         { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
 467         { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
 468         { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
 469         { CSU_CSLX_OCRAM, CSU_ALL_RW },
 470         { CSU_CSLX_GIC, CSU_ALL_RW },
 471         { CSU_CSLX_PCIE1, CSU_ALL_RW },
 472         { CSU_CSLX_OCRAM2, CSU_ALL_RW },
 473         { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
 474         { CSU_CSLX_PCIE2, CSU_ALL_RW },
 475         { CSU_CSLX_SATA, CSU_ALL_RW },
 476         { CSU_CSLX_USB3, CSU_ALL_RW },
 477         { CSU_CSLX_SERDES, CSU_ALL_RW },
 478         { CSU_CSLX_QDMA, CSU_ALL_RW },
 479         { CSU_CSLX_LPUART2, CSU_ALL_RW },
 480         { CSU_CSLX_LPUART1, CSU_ALL_RW },
 481         { CSU_CSLX_LPUART4, CSU_ALL_RW },
 482         { CSU_CSLX_LPUART3, CSU_ALL_RW },
 483         { CSU_CSLX_LPUART6, CSU_ALL_RW },
 484         { CSU_CSLX_LPUART5, CSU_ALL_RW },
 485         { CSU_CSLX_DSPI2, CSU_ALL_RW },
 486         { CSU_CSLX_DSPI1, CSU_ALL_RW },
 487         { CSU_CSLX_QSPI, CSU_ALL_RW },
 488         { CSU_CSLX_ESDHC, CSU_ALL_RW },
 489         { CSU_CSLX_2D_ACE, CSU_ALL_RW },
 490         { CSU_CSLX_IFC, CSU_ALL_RW },
 491         { CSU_CSLX_I2C1, CSU_ALL_RW },
 492         { CSU_CSLX_USB2, CSU_ALL_RW },
 493         { CSU_CSLX_I2C3, CSU_ALL_RW },
 494         { CSU_CSLX_I2C2, CSU_ALL_RW },
 495         { CSU_CSLX_DUART2, CSU_ALL_RW },
 496         { CSU_CSLX_DUART1, CSU_ALL_RW },
 497         { CSU_CSLX_WDT2, CSU_ALL_RW },
 498         { CSU_CSLX_WDT1, CSU_ALL_RW },
 499         { CSU_CSLX_EDMA, CSU_ALL_RW },
 500         { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
 501         { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
 502         { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
 503         { CSU_CSLX_DDR, CSU_ALL_RW },
 504         { CSU_CSLX_QUICC, CSU_ALL_RW },
 505         { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
 506         { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
 507         { CSU_CSLX_SFP, CSU_ALL_RW },
 508         { CSU_CSLX_TMU, CSU_ALL_RW },
 509         { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
 510         { CSU_CSLX_RESERVED0, CSU_ALL_RW },
 511         { CSU_CSLX_ETSEC1, CSU_ALL_RW },
 512         { CSU_CSLX_SEC5_5, CSU_ALL_RW },
 513         { CSU_CSLX_ETSEC3, CSU_ALL_RW },
 514         { CSU_CSLX_ETSEC2, CSU_ALL_RW },
 515         { CSU_CSLX_GPIO2, CSU_ALL_RW },
 516         { CSU_CSLX_GPIO1, CSU_ALL_RW },
 517         { CSU_CSLX_GPIO4, CSU_ALL_RW },
 518         { CSU_CSLX_GPIO3, CSU_ALL_RW },
 519         { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
 520         { CSU_CSLX_CSU, CSU_ALL_RW },
 521         { CSU_CSLX_ASRC, CSU_ALL_RW },
 522         { CSU_CSLX_SPDIF, CSU_ALL_RW },
 523         { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
 524         { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
 525         { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
 526         { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
 527         { CSU_CSLX_SAI2, CSU_ALL_RW },
 528         { CSU_CSLX_SAI1, CSU_ALL_RW },
 529         { CSU_CSLX_SAI4, CSU_ALL_RW },
 530         { CSU_CSLX_SAI3, CSU_ALL_RW },
 531         { CSU_CSLX_FTM2, CSU_ALL_RW },
 532         { CSU_CSLX_FTM1, CSU_ALL_RW },
 533         { CSU_CSLX_FTM4, CSU_ALL_RW },
 534         { CSU_CSLX_FTM3, CSU_ALL_RW },
 535         { CSU_CSLX_FTM6, CSU_ALL_RW },
 536         { CSU_CSLX_FTM5, CSU_ALL_RW },
 537         { CSU_CSLX_FTM8, CSU_ALL_RW },
 538         { CSU_CSLX_FTM7, CSU_ALL_RW },
 539         { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
 540         { CSU_CSLX_EPU, CSU_ALL_RW },
 541         { CSU_CSLX_GDI, CSU_ALL_RW },
 542         { CSU_CSLX_DDI, CSU_ALL_RW },
 543         { CSU_CSLX_RESERVED1, CSU_ALL_RW },
 544         { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
 545         { CSU_CSLX_RESERVED2, CSU_ALL_RW },
 546 };
 547 #endif
 548
 549 struct liodn_id_table sec_liodn_tbl[] = {
 550         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
 551         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
 552         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
 553         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
 554         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
 555         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
 556         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
 557         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
 558         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
 559         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
 560         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
 561         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
 562         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
 563         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
 564         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
 565         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
 566 };
 567
 568 struct smmu_stream_id dev_stream_id[] = {
 569         { 0x100, 0x01, "ETSEC MAC1" },
 570         { 0x104, 0x02, "ETSEC MAC2" },
 571         { 0x108, 0x03, "ETSEC MAC3" },
 572         { 0x10c, 0x04, "PEX1" },
 573         { 0x110, 0x05, "PEX2" },
 574         { 0x114, 0x06, "qDMA" },
 575         { 0x118, 0x07, "SATA" },
 576         { 0x11c, 0x08, "USB3" },
 577         { 0x120, 0x09, "QE" },
 578         { 0x124, 0x0a, "eSDHC" },
 579         { 0x128, 0x0b, "eMA" },
 580         { 0x14c, 0x0c, "2D-ACE" },
 581         { 0x150, 0x0d, "USB2" },
 582         { 0x18c, 0x0e, "DEBUG" },
 583 };
 584
 585 int board_init(void)
 586 {
 587 #ifndef CONFIG_SYS_FSL_NO_SERDES
 588         fsl_serdes_init();
 589 #ifndef CONFIG_QSPI_BOOT
 590         config_serdes_mux();
 591 #endif
 592 #endif
 593
 594         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 595                                       ARRAY_SIZE(sec_liodn_tbl));
 596         ls102xa_config_smmu_stream_id(dev_stream_id,
 597                                       ARRAY_SIZE(dev_stream_id));
 598
 599 #ifdef CONFIG_LS102XA_NS_ACCESS
 600         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 601 #endif
 602
 603 #ifdef CONFIG_U_QE
 604         u_qe_init();
 605 #endif
 606
 607         return 0;
 608 }
 609
 610 #if defined(CONFIG_MISC_INIT_R)
 611 int misc_init_r(void)
 612 {
 613 #ifndef CONFIG_QSPI_BOOT
 614         config_board_mux();
 615 #endif
 616
 617 #ifdef CONFIG_FSL_CAAM
 618         return sec_init();
 619 #endif
 620 }
 621 #endif
 622
 623 #if defined(CONFIG_DEEP_SLEEP)
 624 void board_sleep_prepare(void)
 625 {
 626 #ifdef CONFIG_LS102XA_NS_ACCESS
 627         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 628 #endif
 629 }
 630 #endif
 631
 632 int ft_board_setup(void *blob, bd_t *bd)
 633 {
 634         ft_cpu_setup(blob, bd);
 635
 636 #ifdef CONFIG_PCI
 637         ft_pci_setup(blob, bd);
 638 #endif
 639
 640         return 0;
 641 }
 642
 643 u8 flash_read8(void *addr)
 644 {
 645         return __raw_readb(addr + 1);
 646 }
 647
 648 void flash_write16(u16 val, void *addr)
 649 {
 650         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 651
 652         __raw_writew(shftval, addr);
 653 }
 654
 655 u16 flash_read16(void *addr)
 656 {
 657         u16 val = __raw_readw(addr);
 658
 659         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 660 }
 661
 662 #ifndef CONFIG_QSPI_BOOT
 663 static void convert_flash_bank(char bank)
 664 {
 665         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 666
 667         printf("Now switch to boot from flash bank %d.\n", bank);
 668         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
 669         cpld_data->vbank = bank;
 670
 671         printf("Reset board to enable configuration.\n");
 672         cpld_data->system_rst = CONFIG_RESET;
 673 }
 674
 675 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 676                           char * const argv[])
 677 {
 678         if (argc != 2)
 679                 return CMD_RET_USAGE;
 680         if (strcmp(argv[1], "0") == 0)
 681                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
 682         else if (strcmp(argv[1], "1") == 0)
 683                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
 684         else
 685                 return CMD_RET_USAGE;
 686
 687         return 0;
 688 }
 689
 690 U_BOOT_CMD(
 691         boot_bank, 2, 0, flash_bank_cmd,
 692         "Flash bank Selection Control",
 693         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
 694 );
 695
 696 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 697                           char * const argv[])
 698 {
 699         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 700
 701         if (argc > 2)
 702                 return CMD_RET_USAGE;
 703         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
 704                 cpld_data->system_rst = CONFIG_RESET;
 705         else if (strcmp(argv[1], "init") == 0)
 706                 cpld_data->global_rst = INIT_RESET;
 707         else
 708                 return CMD_RET_USAGE;
 709
 710         return 0;
 711 }
 712
 713 U_BOOT_CMD(
 714         cpld_reset, 2, 0, cpld_reset_cmd,
 715         "Reset via CPLD",
 716         "conf\n"
 717         "       -reset with current CPLD configuration\n"
 718         "init\n"
 719         "       -reset and initial CPLD configuration with default value"
 720
 721 );
 722
 723 static void convert_serdes_mux(int type, int need_reset)
 724 {
 725         char current_serdes;
 726         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 727
 728         current_serdes = cpld_data->serdes_mux;
 729
 730         switch (type) {
 731         case LANEB_SATA:
 732                 current_serdes &= ~MASK_LANE_B;
 733                 break;
 734         case LANEB_SGMII1:
 735                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 736                 break;
 737         case LANEC_SGMII1:
 738                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 739                 break;
 740         case LANED_SGMII2:
 741                 current_serdes |= MASK_LANE_D;
 742                 break;
 743         case LANEC_PCIEX1:
 744                 current_serdes |= MASK_LANE_C;
 745                 break;
 746         case (LANED_PCIEX2 | LANEC_PCIEX1):
 747                 current_serdes |= MASK_LANE_C;
 748                 current_serdes &= ~MASK_LANE_D;
 749                 break;
 750         default:
 751                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
 752                 return;
 753         }
 754
 755         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
 756         cpld_data->serdes_mux = current_serdes;
 757
 758         if (need_reset == 1) {
 759                 printf("Reset board to enable configuration\n");
 760                 cpld_data->system_rst = CONFIG_RESET;
 761         }
 762 }
 763
 764 void print_serdes_mux(void)
 765 {
 766         char current_serdes;
 767         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 768
 769         current_serdes = cpld_data->serdes_mux;
 770
 771         printf("Serdes Lane B: ");
 772         if ((current_serdes & MASK_LANE_B) == 0)
 773                 printf("SATA,\n");
 774         else
 775                 printf("SGMII 1,\n");
 776
 777         printf("Serdes Lane C: ");
 778         if ((current_serdes & MASK_LANE_C) == 0)
 779                 printf("SGMII 1,\n");
 780         else
 781                 printf("PCIe,\n");
 782
 783         printf("Serdes Lane D: ");
 784         if ((current_serdes & MASK_LANE_D) == 0)
 785                 printf("PCIe,\n");
 786         else
 787                 printf("SGMII 2,\n");
 788
 789         printf("SGMII 1 is on lane ");
 790         if ((current_serdes & MASK_SGMII) == 0)
 791                 printf("C.\n");
 792         else
 793                 printf("B.\n");
 794 }
 795
 796 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 797                           char * const argv[])
 798 {
 799         if (argc != 2)
 800                 return CMD_RET_USAGE;
 801         if (strcmp(argv[1], "sata") == 0) {
 802                 printf("Set serdes lane B to SATA.\n");
 803                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
 804         } else if (strcmp(argv[1], "sgmii1b") == 0) {
 805                 printf("Set serdes lane B to SGMII 1.\n");
 806                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
 807         } else if (strcmp(argv[1], "sgmii1c") == 0) {
 808                 printf("Set serdes lane C to SGMII 1.\n");
 809                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
 810         } else if (strcmp(argv[1], "sgmii2") == 0) {
 811                 printf("Set serdes lane D to SGMII 2.\n");
 812                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
 813         } else if (strcmp(argv[1], "pciex1") == 0) {
 814                 printf("Set serdes lane C to PCIe X1.\n");
 815                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
 816         } else if (strcmp(argv[1], "pciex2") == 0) {
 817                 printf("Set serdes lane C & lane D to PCIe X2.\n");
 818                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
 819         } else if (strcmp(argv[1], "show") == 0) {
 820                 print_serdes_mux();
 821         } else {
 822                 return CMD_RET_USAGE;
 823         }
 824
 825         return 0;
 826 }
 827
 828 U_BOOT_CMD(
 829         lane_bank, 2, 0, serdes_mux_cmd,
 830         "Multiplexed function setting for SerDes Lanes",
 831         "sata\n"
 832         "       -change lane B to sata\n"
 833         "lane_bank sgmii1b\n"
 834         "       -change lane B to SGMII1\n"
 835         "lane_bank sgmii1c\n"
 836         "       -change lane C to SGMII1\n"
 837         "lane_bank sgmii2\n"
 838         "       -change lane D to SGMII2\n"
 839         "lane_bank pciex1\n"
 840         "       -change lane C to PCIeX1\n"
 841         "lane_bank pciex2\n"
 842         "       -change lane C & lane D to PCIeX2\n"
 843         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
 844 );
 845 #endif