board/freescale/ls2085ardb/eth_ls2085rdb.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <netdev.h>
  11 #include <malloc.h>
  12 #include <fsl_mdio.h>
  13 #include <miiphy.h>
  14 #include <phy.h>
  15 #include <fm_eth.h>
  16 #include <asm/io.h>
  17 #include <exports.h>
  18 #include <asm/arch/fsl_serdes.h>
  19 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
  20 #include <fsl-mc/ldpaa_wriop.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 int load_firmware_cortina(struct phy_device *phy_dev)
  25 {
  26         if (phy_dev->drv->config)
  27                 return phy_dev->drv->config(phy_dev);
  28
  29         return 0;
  30 }
  31
  32 void load_phy_firmware(void)
  33 {
  34         int i;
  35         u8 phy_addr;
  36         struct phy_device *phy_dev;
  37         struct mii_dev *dev;
  38         phy_interface_t interface;
  39
  40         /*Initialize and upload firmware for all the PHYs*/
  41         for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
  42                 interface = wriop_get_enet_if(i);
  43                 if (interface == PHY_INTERFACE_MODE_XGMII) {
  44                         dev = wriop_get_mdio(i);
  45                         phy_addr = wriop_get_phy_address(i);
  46                         phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
  47                                                 interface);
  48                         if (!phy_dev) {
  49                                 printf("No phydev for phyaddr %d\n", phy_addr);
  50                                 continue;
  51                         }
  52
  53                         /*Flash firmware for All CS4340 PHYS */
  54                         if (phy_dev->phy_id == PHY_UID_CS4340)
  55                                 load_firmware_cortina(phy_dev);
  56                 }
  57         }
  58 }
  59
  60 int board_eth_init(bd_t *bis)
  61 {
  62 #if defined(CONFIG_FSL_MC_ENET)
  63         int i, interface;
  64         struct memac_mdio_info mdio_info;
  65         struct mii_dev *dev;
  66         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  67         u32 srds_s1;
  68         struct memac_mdio_controller *reg;
  69
  70         srds_s1 = in_le32(&gur->rcwsr[28]) &
  71                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  72         srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  73
  74         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  75         mdio_info.regs = reg;
  76         mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  77
  78         /* Register the EMI 1 */
  79         fm_memac_mdio_init(bis, &mdio_info);
  80
  81         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  82         mdio_info.regs = reg;
  83         mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  84
  85         /* Register the EMI 2 */
  86         fm_memac_mdio_init(bis, &mdio_info);
  87
  88         switch (srds_s1) {
  89         case 0x2A:
  90                 wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
  91                 wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
  92                 wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
  93                 wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
  94                 wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
  95                 wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
  96                 wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
  97                 wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
  98
  99                 break;
 100         default:
 101                 printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n",
 102                        srds_s1);
 103                 break;
 104         }
 105
 106         for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
 107                 interface = wriop_get_enet_if(i);
 108                 switch (interface) {
 109                 case PHY_INTERFACE_MODE_XGMII:
 110                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 111                         wriop_set_mdio(i, dev);
 112                         break;
 113                 default:
 114                         break;
 115                 }
 116         }
 117
 118         for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
 119                 switch (wriop_get_enet_if(i)) {
 120                 case PHY_INTERFACE_MODE_XGMII:
 121                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
 122                         wriop_set_mdio(i, dev);
 123                         break;
 124                 default:
 125                         break;
 126                 }
 127         }
 128
 129         /* Load CORTINA CS4340 PHY firmware */
 130         load_phy_firmware();
 131
 132         cpu_eth_init(bis);
 133 #endif /* CONFIG_FMAN_ENET */
 134
 135 #ifdef CONFIG_PHY_AQUANTIA
 136         /*
 137          * Export functions to be used by AQ firmware
 138          * upload application
 139          */
 140         gd->jt->strcpy = strcpy;
 141         gd->jt->mdelay = mdelay;
 142         gd->jt->mdio_get_current_dev = mdio_get_current_dev;
 143         gd->jt->phy_find_by_mask = phy_find_by_mask;
 144         gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
 145         gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
 146 #endif
 147         return pci_eth_init(bis);
 148 }