board/freescale/mpc8572ds/mpc8572ds.c

   1 /*
   2  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <miiphy.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36 #include <tsec.h>
  37 #include <netdev.h>
  38
  39 #include "../common/pixis.h"
  40 #include "../common/sgmii_riser.h"
  41
  42 long int fixed_sdram(void);
  43
  44 int checkboard (void)
  45 {
  46         u8 vboot;
  47         u8 *pixis_base = (u8 *)PIXIS_BASE;
  48
  49         puts ("Board: MPC8572DS ");
  50 #ifdef CONFIG_PHYS_64BIT
  51         puts ("(36-bit addrmap) ");
  52 #endif
  53         printf ("Sys ID: 0x%02x, "
  54                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  55                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  56                 in_8(pixis_base + PIXIS_PVER));
  57
  58         vboot = in_8(pixis_base + PIXIS_VBOOT);
  59         switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
  60                 case PIXIS_VBOOT_LBMAP_NOR0:
  61                         puts ("vBank: 0\n");
  62                         break;
  63                 case PIXIS_VBOOT_LBMAP_PJET:
  64                         puts ("Promjet\n");
  65                         break;
  66                 case PIXIS_VBOOT_LBMAP_NAND:
  67                         puts ("NAND\n");
  68                         break;
  69                 case PIXIS_VBOOT_LBMAP_NOR1:
  70                         puts ("vBank: 1\n");
  71                         break;
  72         }
  73
  74         return 0;
  75 }
  76
  77 phys_size_t initdram(int board_type)
  78 {
  79         phys_size_t dram_size = 0;
  80
  81         puts("Initializing....");
  82
  83 #ifdef CONFIG_SPD_EEPROM
  84         dram_size = fsl_ddr_sdram();
  85 #else
  86         dram_size = fixed_sdram();
  87 #endif
  88         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  89         dram_size *= 0x100000;
  90
  91         puts("    DDR: ");
  92         return dram_size;
  93 }
  94
  95 #if !defined(CONFIG_SPD_EEPROM)
  96 /*
  97  * Fixed sdram init -- doesn't use serial presence detect.
  98  */
  99
 100 phys_size_t fixed_sdram (void)
 101 {
 102         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 103         volatile ccsr_ddr_t *ddr= &immap->im_ddr;
 104         uint d_init;
 105
 106         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 107         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 108
 109         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 110         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 111         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 112         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 113         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 114         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 115         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 116         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 117         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 118         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 119
 120 #if defined (CONFIG_DDR_ECC)
 121         ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 122         ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 123         ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 124 #endif
 125         asm("sync;isync");
 126
 127         udelay(500);
 128
 129         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 130
 131 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 132         d_init = 1;
 133         debug("DDR - 1st controller: memory initializing\n");
 134         /*
 135          * Poll until memory is initialized.
 136          * 512 Meg at 400 might hit this 200 times or so.
 137          */
 138         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 139                 udelay(1000);
 140         }
 141         debug("DDR: memory initialized\n\n");
 142         asm("sync; isync");
 143         udelay(500);
 144 #endif
 145
 146         return 512 * 1024 * 1024;
 147 }
 148
 149 #endif
 150
 151 #ifdef CONFIG_PCIE1
 152 static struct pci_controller pcie1_hose;
 153 #endif
 154
 155 #ifdef CONFIG_PCIE2
 156 static struct pci_controller pcie2_hose;
 157 #endif
 158
 159 #ifdef CONFIG_PCIE3
 160 static struct pci_controller pcie3_hose;
 161 #endif
 162
 163 int first_free_busno=0;
 164 #ifdef CONFIG_PCI
 165 void pci_init_board(void)
 166 {
 167         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 168         uint devdisr = gur->devdisr;
 169         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 170         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 171
 172         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 173                         devdisr, io_sel, host_agent);
 174
 175         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 176                 printf ("    eTSEC1 is in sgmii mode.\n");
 177         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 178                 printf ("    eTSEC2 is in sgmii mode.\n");
 179         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 180                 printf ("    eTSEC3 is in sgmii mode.\n");
 181         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 182                 printf ("    eTSEC4 is in sgmii mode.\n");
 183
 184
 185 #ifdef CONFIG_PCIE3
 186         {
 187                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 188                 struct pci_controller *hose = &pcie3_hose;
 189                 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
 190                 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
 191                 struct pci_region *r = hose->regions;
 192                 u32 temp32;
 193
 194                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
 195                         printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 196                                         pcie_ep ? "End Point" : "Root Complex",
 197                                         (uint)pci);
 198                         if (pci->pme_msg_det) {
 199                                 pci->pme_msg_det = 0xffffffff;
 200                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 201                         }
 202                         printf ("\n");
 203
 204                         /* outbound memory */
 205                         pci_set_region(r++,
 206                                         CONFIG_SYS_PCIE3_MEM_BUS,
 207                                         CONFIG_SYS_PCIE3_MEM_PHYS,
 208                                         CONFIG_SYS_PCIE3_MEM_SIZE,
 209                                         PCI_REGION_MEM);
 210
 211                         /* outbound io */
 212                         pci_set_region(r++,
 213                                         CONFIG_SYS_PCIE3_IO_BUS,
 214                                         CONFIG_SYS_PCIE3_IO_PHYS,
 215                                         CONFIG_SYS_PCIE3_IO_SIZE,
 216                                         PCI_REGION_IO);
 217
 218                         hose->region_count = r - hose->regions;
 219                         hose->first_busno=first_free_busno;
 220
 221                         fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 222
 223                         first_free_busno=hose->last_busno+1;
 224                         printf ("    PCIE3 on bus %02x - %02x\n",
 225                                         hose->first_busno,hose->last_busno);
 226
 227                         /*
 228                          * Activate ULI1575 legacy chip by performing a fake
 229                          * memory access.  Needed to make ULI RTC work.
 230                          * Device 1d has the first on-board memory BAR.
 231                          */
 232
 233                         pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
 234                                         PCI_BASE_ADDRESS_1, &temp32);
 235                         if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
 236                                 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
 237                                                                 temp32, 4, 0);
 238                                 debug(" uli1572 read to %p\n", p);
 239                                 in_be32(p);
 240                         }
 241                 } else {
 242                         printf ("    PCIE3: disabled\n");
 243                 }
 244
 245         }
 246 #else
 247         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 248 #endif
 249
 250 #ifdef CONFIG_PCIE2
 251         {
 252                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 253                 struct pci_controller *hose = &pcie2_hose;
 254                 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
 255                 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
 256                 struct pci_region *r = hose->regions;
 257
 258                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
 259                         printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 260                                         pcie_ep ? "End Point" : "Root Complex",
 261                                         (uint)pci);
 262                         if (pci->pme_msg_det) {
 263                                 pci->pme_msg_det = 0xffffffff;
 264                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 265                         }
 266                         printf ("\n");
 267
 268                         /* outbound memory */
 269                         pci_set_region(r++,
 270                                         CONFIG_SYS_PCIE2_MEM_BUS,
 271                                         CONFIG_SYS_PCIE2_MEM_PHYS,
 272                                         CONFIG_SYS_PCIE2_MEM_SIZE,
 273                                         PCI_REGION_MEM);
 274
 275                         /* outbound io */
 276                         pci_set_region(r++,
 277                                         CONFIG_SYS_PCIE2_IO_BUS,
 278                                         CONFIG_SYS_PCIE2_IO_PHYS,
 279                                         CONFIG_SYS_PCIE2_IO_SIZE,
 280                                         PCI_REGION_IO);
 281
 282                         hose->region_count = r - hose->regions;
 283                         hose->first_busno=first_free_busno;
 284
 285                         fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 286                         first_free_busno=hose->last_busno+1;
 287                         printf ("    PCIE2 on bus %02x - %02x\n",
 288                                         hose->first_busno,hose->last_busno);
 289
 290                 } else {
 291                         printf ("    PCIE2: disabled\n");
 292                 }
 293
 294         }
 295 #else
 296         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 297 #endif
 298 #ifdef CONFIG_PCIE1
 299         {
 300                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 301                 struct pci_controller *hose = &pcie1_hose;
 302                 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
 303                 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
 304                 struct pci_region *r = hose->regions;
 305
 306                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 307                         printf ("\n    PCIE1 connected to Slot 2 as %s (base address %x)",
 308                                         pcie_ep ? "End Point" : "Root Complex",
 309                                         (uint)pci);
 310                         if (pci->pme_msg_det) {
 311                                 pci->pme_msg_det = 0xffffffff;
 312                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 313                         }
 314                         printf ("\n");
 315
 316                         /* outbound memory */
 317                         pci_set_region(r++,
 318                                         CONFIG_SYS_PCIE1_MEM_BUS,
 319                                         CONFIG_SYS_PCIE1_MEM_PHYS,
 320                                         CONFIG_SYS_PCIE1_MEM_SIZE,
 321                                         PCI_REGION_MEM);
 322
 323                         /* outbound io */
 324                         pci_set_region(r++,
 325                                         CONFIG_SYS_PCIE1_IO_BUS,
 326                                         CONFIG_SYS_PCIE1_IO_PHYS,
 327                                         CONFIG_SYS_PCIE1_IO_SIZE,
 328                                         PCI_REGION_IO);
 329
 330                         hose->region_count = r - hose->regions;
 331                         hose->first_busno=first_free_busno;
 332
 333                         fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 334
 335                         first_free_busno=hose->last_busno+1;
 336                         printf("    PCIE1 on bus %02x - %02x\n",
 337                                         hose->first_busno,hose->last_busno);
 338
 339                 } else {
 340                         printf ("    PCIE1: disabled\n");
 341                 }
 342
 343         }
 344 #else
 345         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 346 #endif
 347 }
 348 #endif
 349
 350 int board_early_init_r(void)
 351 {
 352         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 353         const u8 flash_esel = 2;
 354
 355         /*
 356          * Remap Boot flash + PROMJET region to caching-inhibited
 357          * so that flash can be erased properly.
 358          */
 359
 360         /* Flush d-cache and invalidate i-cache of any FLASH data */
 361         flush_dcache();
 362         invalidate_icache();
 363
 364         /* invalidate existing TLB entry for flash + promjet */
 365         disable_tlb(flash_esel);
 366
 367         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,       /* tlb, epn, rpn */
 368                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 369                         0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
 370
 371         return 0;
 372 }
 373
 374 #ifdef CONFIG_GET_CLK_FROM_ICS307
 375 /* decode S[0-2] to Output Divider (OD) */
 376 static unsigned char ics307_S_to_OD[] = {
 377         10, 2, 8, 4, 5, 7, 3, 6
 378 };
 379
 380 /* Calculate frequency being generated by ICS307-02 clock chip based upon
 381  * the control bytes being programmed into it. */
 382 /* XXX: This function should probably go into a common library */
 383 static unsigned long
 384 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
 385 {
 386         const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
 387         unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 388         unsigned long RDW = cw2 & 0x7F;
 389         unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
 390         unsigned long freq;
 391
 392         /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
 393
 394         /* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 395          * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 396          * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 397          *
 398          * R6:R0 = Reference Divider Word (RDW)
 399          * V8:V0 = VCO Divider Word (VDW)
 400          * S2:S0 = Output Divider Select (OD)
 401          * F1:F0 = Function of CLK2 Output
 402          * TTL = duty cycle
 403          * C1:C0 = internal load capacitance for cyrstal
 404          */
 405
 406         /* Adding 1 to get a "nicely" rounded number, but this needs
 407          * more tweaking to get a "properly" rounded number. */
 408
 409         freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
 410
 411         debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
 412                         freq);
 413         return freq;
 414 }
 415
 416 unsigned long get_board_sys_clk(ulong dummy)
 417 {
 418         u8 *pixis_base = (u8 *)PIXIS_BASE;
 419
 420         return ics307_clk_freq (
 421                         in_8(pixis_base + PIXIS_VSYSCLK0),
 422                         in_8(pixis_base + PIXIS_VSYSCLK1),
 423                         in_8(pixis_base + PIXIS_VSYSCLK2)
 424                         );
 425 }
 426
 427 unsigned long get_board_ddr_clk(ulong dummy)
 428 {
 429         u8 *pixis_base = (u8 *)PIXIS_BASE;
 430
 431         return ics307_clk_freq (
 432                         in_8(pixis_base + PIXIS_VDDRCLK0),
 433                         in_8(pixis_base + PIXIS_VDDRCLK1),
 434                         in_8(pixis_base + PIXIS_VDDRCLK2)
 435                         );
 436 }
 437 #else
 438 unsigned long get_board_sys_clk(ulong dummy)
 439 {
 440         u8 i;
 441         ulong val = 0;
 442         u8 *pixis_base = (u8 *)PIXIS_BASE;
 443
 444         i = in_8(pixis_base + PIXIS_SPD);
 445         i &= 0x07;
 446
 447         switch (i) {
 448                 case 0:
 449                         val = 33333333;
 450                         break;
 451                 case 1:
 452                         val = 40000000;
 453                         break;
 454                 case 2:
 455                         val = 50000000;
 456                         break;
 457                 case 3:
 458                         val = 66666666;
 459                         break;
 460                 case 4:
 461                         val = 83333333;
 462                         break;
 463                 case 5:
 464                         val = 100000000;
 465                         break;
 466                 case 6:
 467                         val = 133333333;
 468                         break;
 469                 case 7:
 470                         val = 166666666;
 471                         break;
 472         }
 473
 474         return val;
 475 }
 476
 477 unsigned long get_board_ddr_clk(ulong dummy)
 478 {
 479         u8 i;
 480         ulong val = 0;
 481         u8 *pixis_base = (u8 *)PIXIS_BASE;
 482
 483         i = in_8(pixis_base + PIXIS_SPD);
 484         i &= 0x38;
 485         i >>= 3;
 486
 487         switch (i) {
 488                 case 0:
 489                         val = 33333333;
 490                         break;
 491                 case 1:
 492                         val = 40000000;
 493                         break;
 494                 case 2:
 495                         val = 50000000;
 496                         break;
 497                 case 3:
 498                         val = 66666666;
 499                         break;
 500                 case 4:
 501                         val = 83333333;
 502                         break;
 503                 case 5:
 504                         val = 100000000;
 505                         break;
 506                 case 6:
 507                         val = 133333333;
 508                         break;
 509                 case 7:
 510                         val = 166666666;
 511                         break;
 512         }
 513         return val;
 514 }
 515 #endif
 516
 517 #ifdef CONFIG_TSEC_ENET
 518 int board_eth_init(bd_t *bis)
 519 {
 520         struct tsec_info_struct tsec_info[4];
 521         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 522         int num = 0;
 523
 524 #ifdef CONFIG_TSEC1
 525         SET_STD_TSEC_INFO(tsec_info[num], 1);
 526         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 527                 tsec_info[num].flags |= TSEC_SGMII;
 528         num++;
 529 #endif
 530 #ifdef CONFIG_TSEC2
 531         SET_STD_TSEC_INFO(tsec_info[num], 2);
 532         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 533                 tsec_info[num].flags |= TSEC_SGMII;
 534         num++;
 535 #endif
 536 #ifdef CONFIG_TSEC3
 537         SET_STD_TSEC_INFO(tsec_info[num], 3);
 538         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 539                 tsec_info[num].flags |= TSEC_SGMII;
 540         num++;
 541 #endif
 542 #ifdef CONFIG_TSEC4
 543         SET_STD_TSEC_INFO(tsec_info[num], 4);
 544         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 545                 tsec_info[num].flags |= TSEC_SGMII;
 546         num++;
 547 #endif
 548
 549         if (!num) {
 550                 printf("No TSECs initialized\n");
 551
 552                 return 0;
 553         }
 554
 555 #ifdef CONFIG_FSL_SGMII_RISER
 556         fsl_sgmii_riser_init(tsec_info, num);
 557 #endif
 558
 559         tsec_eth_init(bis, tsec_info, num);
 560
 561         return pci_eth_init(bis);
 562 }
 563 #endif
 564
 565 #if defined(CONFIG_OF_BOARD_SETUP)
 566 void ft_board_setup(void *blob, bd_t *bd)
 567 {
 568         phys_addr_t base;
 569         phys_size_t size;
 570
 571         ft_cpu_setup(blob, bd);
 572
 573         base = getenv_bootm_low();
 574         size = getenv_bootm_size();
 575
 576         fdt_fixup_memory(blob, (u64)base, (u64)size);
 577
 578 #ifdef CONFIG_PCIE3
 579         ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
 580 #endif
 581 #ifdef CONFIG_PCIE2
 582         ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 583 #endif
 584 #ifdef CONFIG_PCIE1
 585         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 586 #endif
 587 #ifdef CONFIG_FSL_SGMII_RISER
 588         fsl_sgmii_riser_fdt_fixup(blob);
 589 #endif
 590 }
 591 #endif
 592
 593 #ifdef CONFIG_MP
 594 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
 595
 596 void board_lmb_reserve(struct lmb *lmb)
 597 {
 598         cpu_mp_lmb_reserve(lmb);
 599 }
 600 #endif