board/freescale/mpc8572ds/mpc8572ds.c

   1 /*
   2  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/immap_fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <miiphy.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36 #include <tsec.h>
  37
  38 #include "../common/pixis.h"
  39 #include "../common/sgmii_riser.h"
  40
  41 long int fixed_sdram(void);
  42
  43 int checkboard (void)
  44 {
  45         printf ("Board: MPC8572DS, System ID: 0x%02x, "
  46                 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
  47                 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
  48                 in8(PIXIS_BASE + PIXIS_PVER));
  49         return 0;
  50 }
  51
  52 phys_size_t initdram(int board_type)
  53 {
  54         phys_size_t dram_size = 0;
  55
  56         puts("Initializing....");
  57
  58 #ifdef CONFIG_SPD_EEPROM
  59         dram_size = fsl_ddr_sdram();
  60 #else
  61         dram_size = fixed_sdram();
  62 #endif
  63         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  64         dram_size *= 0x100000;
  65
  66         puts("    DDR: ");
  67         return dram_size;
  68 }
  69
  70 #if !defined(CONFIG_SPD_EEPROM)
  71 /*
  72  * Fixed sdram init -- doesn't use serial presence detect.
  73  */
  74
  75 phys_size_t fixed_sdram (void)
  76 {
  77         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  78         volatile ccsr_ddr_t *ddr= &immap->im_ddr;
  79         uint d_init;
  80
  81         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  82         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  83
  84         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  85         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  86         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  87         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  88         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  89         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  90         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  91         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  92         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  93         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
  94
  95 #if defined (CONFIG_DDR_ECC)
  96         ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
  97         ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
  98         ddr->err_sbe = CONFIG_SYS_DDR_SBE;
  99 #endif
 100         asm("sync;isync");
 101
 102         udelay(500);
 103
 104         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 105
 106 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 107         d_init = 1;
 108         debug("DDR - 1st controller: memory initializing\n");
 109         /*
 110          * Poll until memory is initialized.
 111          * 512 Meg at 400 might hit this 200 times or so.
 112          */
 113         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 114                 udelay(1000);
 115         }
 116         debug("DDR: memory initialized\n\n");
 117         asm("sync; isync");
 118         udelay(500);
 119 #endif
 120
 121         return 512 * 1024 * 1024;
 122 }
 123
 124 #endif
 125
 126 #ifdef CONFIG_PCIE1
 127 static struct pci_controller pcie1_hose;
 128 #endif
 129
 130 #ifdef CONFIG_PCIE2
 131 static struct pci_controller pcie2_hose;
 132 #endif
 133
 134 #ifdef CONFIG_PCIE3
 135 static struct pci_controller pcie3_hose;
 136 #endif
 137
 138 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
 139 extern void fsl_pci_init(struct pci_controller *hose);
 140
 141 int first_free_busno=0;
 142 #ifdef CONFIG_PCI
 143 void pci_init_board(void)
 144 {
 145         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 146         uint devdisr = gur->devdisr;
 147         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 148         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 149
 150         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 151                         devdisr, io_sel, host_agent);
 152
 153         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 154                 printf ("    eTSEC1 is in sgmii mode.\n");
 155         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 156                 printf ("    eTSEC2 is in sgmii mode.\n");
 157         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 158                 printf ("    eTSEC3 is in sgmii mode.\n");
 159         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 160                 printf ("    eTSEC4 is in sgmii mode.\n");
 161
 162
 163 #ifdef CONFIG_PCIE3
 164         {
 165                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 166                 struct pci_controller *hose = &pcie3_hose;
 167                 int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
 168                         (host_agent == 5) || (host_agent == 6);
 169                 int pcie_configured  = (io_sel == 0x7);
 170                 struct pci_region *r = hose->regions;
 171                 u32 temp32;
 172
 173                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
 174                         printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 175                                         pcie_ep ? "End Point" : "Root Complex",
 176                                         (uint)pci);
 177                         if (pci->pme_msg_det) {
 178                                 pci->pme_msg_det = 0xffffffff;
 179                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 180                         }
 181                         printf ("\n");
 182
 183                         /* inbound */
 184                         r += fsl_pci_setup_inbound_windows(r);
 185
 186                         /* outbound memory */
 187                         pci_set_region(r++,
 188                                         CONFIG_SYS_PCIE3_MEM_BASE,
 189                                         CONFIG_SYS_PCIE3_MEM_PHYS,
 190                                         CONFIG_SYS_PCIE3_MEM_SIZE,
 191                                         PCI_REGION_MEM);
 192
 193                         /* outbound io */
 194                         pci_set_region(r++,
 195                                         CONFIG_SYS_PCIE3_IO_BASE,
 196                                         CONFIG_SYS_PCIE3_IO_PHYS,
 197                                         CONFIG_SYS_PCIE3_IO_SIZE,
 198                                         PCI_REGION_IO);
 199
 200                         hose->region_count = r - hose->regions;
 201                         hose->first_busno=first_free_busno;
 202                         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 203
 204                         fsl_pci_init(hose);
 205
 206                         first_free_busno=hose->last_busno+1;
 207                         printf ("    PCIE3 on bus %02x - %02x\n",
 208                                         hose->first_busno,hose->last_busno);
 209
 210                         /*
 211                          * Activate ULI1575 legacy chip by performing a fake
 212                          * memory access.  Needed to make ULI RTC work.
 213                          * Device 1d has the first on-board memory BAR.
 214                          */
 215
 216                         pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
 217                                         PCI_BASE_ADDRESS_1, &temp32);
 218                         if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) {
 219                                 debug(" uli1572 read to %x\n", temp32);
 220                                 in_be32((unsigned *)temp32);
 221                         }
 222                 } else {
 223                         printf ("    PCIE3: disabled\n");
 224                 }
 225
 226         }
 227 #else
 228         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 229 #endif
 230
 231 #ifdef CONFIG_PCIE2
 232         {
 233                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 234                 struct pci_controller *hose = &pcie2_hose;
 235                 int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
 236                         (host_agent == 6) || (host_agent == 0);
 237                 int pcie_configured  = (io_sel == 0x3) || (io_sel == 0x7);
 238                 struct pci_region *r = hose->regions;
 239
 240                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
 241                         printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 242                                         pcie_ep ? "End Point" : "Root Complex",
 243                                         (uint)pci);
 244                         if (pci->pme_msg_det) {
 245                                 pci->pme_msg_det = 0xffffffff;
 246                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 247                         }
 248                         printf ("\n");
 249
 250                         /* inbound */
 251                         r += fsl_pci_setup_inbound_windows(r);
 252
 253                         /* outbound memory */
 254                         pci_set_region(r++,
 255                                         CONFIG_SYS_PCIE2_MEM_BASE,
 256                                         CONFIG_SYS_PCIE2_MEM_PHYS,
 257                                         CONFIG_SYS_PCIE2_MEM_SIZE,
 258                                         PCI_REGION_MEM);
 259
 260                         /* outbound io */
 261                         pci_set_region(r++,
 262                                         CONFIG_SYS_PCIE2_IO_BASE,
 263                                         CONFIG_SYS_PCIE2_IO_PHYS,
 264                                         CONFIG_SYS_PCIE2_IO_SIZE,
 265                                         PCI_REGION_IO);
 266
 267                         hose->region_count = r - hose->regions;
 268                         hose->first_busno=first_free_busno;
 269                         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 270
 271                         fsl_pci_init(hose);
 272                         first_free_busno=hose->last_busno+1;
 273                         printf ("    PCIE2 on bus %02x - %02x\n",
 274                                         hose->first_busno,hose->last_busno);
 275
 276                 } else {
 277                         printf ("    PCIE2: disabled\n");
 278                 }
 279
 280         }
 281 #else
 282         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 283 #endif
 284 #ifdef CONFIG_PCIE1
 285         {
 286                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 287                 struct pci_controller *hose = &pcie1_hose;
 288                 int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
 289                         (host_agent == 5);
 290                 int pcie_configured  = (io_sel == 0x2) || (io_sel == 0x3) ||
 291                                         (io_sel == 0x7) || (io_sel == 0xb) ||
 292                                         (io_sel == 0xc) || (io_sel == 0xf);
 293                 struct pci_region *r = hose->regions;
 294
 295                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 296                         printf ("\n    PCIE1 connected to Slot 2 as %s (base address %x)",
 297                                         pcie_ep ? "End Point" : "Root Complex",
 298                                         (uint)pci);
 299                         if (pci->pme_msg_det) {
 300                                 pci->pme_msg_det = 0xffffffff;
 301                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 302                         }
 303                         printf ("\n");
 304
 305                         /* inbound */
 306                         r += fsl_pci_setup_inbound_windows(r);
 307
 308                         /* outbound memory */
 309                         pci_set_region(r++,
 310                                         CONFIG_SYS_PCIE1_MEM_BASE,
 311                                         CONFIG_SYS_PCIE1_MEM_PHYS,
 312                                         CONFIG_SYS_PCIE1_MEM_SIZE,
 313                                         PCI_REGION_MEM);
 314
 315                         /* outbound io */
 316                         pci_set_region(r++,
 317                                         CONFIG_SYS_PCIE1_IO_BASE,
 318                                         CONFIG_SYS_PCIE1_IO_PHYS,
 319                                         CONFIG_SYS_PCIE1_IO_SIZE,
 320                                         PCI_REGION_IO);
 321
 322                         hose->region_count = r - hose->regions;
 323                         hose->first_busno=first_free_busno;
 324
 325                         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 326
 327                         fsl_pci_init(hose);
 328
 329                         first_free_busno=hose->last_busno+1;
 330                         printf("    PCIE1 on bus %02x - %02x\n",
 331                                         hose->first_busno,hose->last_busno);
 332
 333                 } else {
 334                         printf ("    PCIE1: disabled\n");
 335                 }
 336
 337         }
 338 #else
 339         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 340 #endif
 341 }
 342 #endif
 343
 344 int board_early_init_r(void)
 345 {
 346         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 347         const u8 flash_esel = 2;
 348
 349         /*
 350          * Remap Boot flash + PROMJET region to caching-inhibited
 351          * so that flash can be erased properly.
 352          */
 353
 354         /* Flush d-cache and invalidate i-cache of any FLASH data */
 355         flush_dcache();
 356         invalidate_icache();
 357
 358         /* invalidate existing TLB entry for flash + promjet */
 359         disable_tlb(flash_esel);
 360
 361         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,       /* tlb, epn, rpn */
 362                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 363                         0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
 364
 365         return 0;
 366 }
 367
 368 #ifdef CONFIG_GET_CLK_FROM_ICS307
 369 /* decode S[0-2] to Output Divider (OD) */
 370 static unsigned char ics307_S_to_OD[] = {
 371         10, 2, 8, 4, 5, 7, 3, 6
 372 };
 373
 374 /* Calculate frequency being generated by ICS307-02 clock chip based upon
 375  * the control bytes being programmed into it. */
 376 /* XXX: This function should probably go into a common library */
 377 static unsigned long
 378 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
 379 {
 380         const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
 381         unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 382         unsigned long RDW = cw2 & 0x7F;
 383         unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
 384         unsigned long freq;
 385
 386         /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
 387
 388         /* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 389          * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 390          * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 391          *
 392          * R6:R0 = Reference Divider Word (RDW)
 393          * V8:V0 = VCO Divider Word (VDW)
 394          * S2:S0 = Output Divider Select (OD)
 395          * F1:F0 = Function of CLK2 Output
 396          * TTL = duty cycle
 397          * C1:C0 = internal load capacitance for cyrstal
 398          */
 399
 400         /* Adding 1 to get a "nicely" rounded number, but this needs
 401          * more tweaking to get a "properly" rounded number. */
 402
 403         freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
 404
 405         debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
 406                         freq);
 407         return freq;
 408 }
 409
 410 unsigned long get_board_sys_clk(ulong dummy)
 411 {
 412         return ics307_clk_freq (
 413                         in8(PIXIS_BASE + PIXIS_VSYSCLK0),
 414                         in8(PIXIS_BASE + PIXIS_VSYSCLK1),
 415                         in8(PIXIS_BASE + PIXIS_VSYSCLK2)
 416                         );
 417 }
 418
 419 unsigned long get_board_ddr_clk(ulong dummy)
 420 {
 421         return ics307_clk_freq (
 422                         in8(PIXIS_BASE + PIXIS_VDDRCLK0),
 423                         in8(PIXIS_BASE + PIXIS_VDDRCLK1),
 424                         in8(PIXIS_BASE + PIXIS_VDDRCLK2)
 425                         );
 426 }
 427 #else
 428 unsigned long get_board_sys_clk(ulong dummy)
 429 {
 430         u8 i;
 431         ulong val = 0;
 432
 433         i = in8(PIXIS_BASE + PIXIS_SPD);
 434         i &= 0x07;
 435
 436         switch (i) {
 437                 case 0:
 438                         val = 33333333;
 439                         break;
 440                 case 1:
 441                         val = 40000000;
 442                         break;
 443                 case 2:
 444                         val = 50000000;
 445                         break;
 446                 case 3:
 447                         val = 66666666;
 448                         break;
 449                 case 4:
 450                         val = 83333333;
 451                         break;
 452                 case 5:
 453                         val = 100000000;
 454                         break;
 455                 case 6:
 456                         val = 133333333;
 457                         break;
 458                 case 7:
 459                         val = 166666666;
 460                         break;
 461         }
 462
 463         return val;
 464 }
 465
 466 unsigned long get_board_ddr_clk(ulong dummy)
 467 {
 468         u8 i;
 469         ulong val = 0;
 470
 471         i = in8(PIXIS_BASE + PIXIS_SPD);
 472         i &= 0x38;
 473         i >>= 3;
 474
 475         switch (i) {
 476                 case 0:
 477                         val = 33333333;
 478                         break;
 479                 case 1:
 480                         val = 40000000;
 481                         break;
 482                 case 2:
 483                         val = 50000000;
 484                         break;
 485                 case 3:
 486                         val = 66666666;
 487                         break;
 488                 case 4:
 489                         val = 83333333;
 490                         break;
 491                 case 5:
 492                         val = 100000000;
 493                         break;
 494                 case 6:
 495                         val = 133333333;
 496                         break;
 497                 case 7:
 498                         val = 166666666;
 499                         break;
 500         }
 501         return val;
 502 }
 503 #endif
 504
 505 #ifdef CONFIG_TSEC_ENET
 506 int board_eth_init(bd_t *bis)
 507 {
 508         struct tsec_info_struct tsec_info[4];
 509         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 510         int num = 0;
 511
 512 #ifdef CONFIG_TSEC1
 513         SET_STD_TSEC_INFO(tsec_info[num], 1);
 514         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 515                 tsec_info[num].flags |= TSEC_SGMII;
 516         num++;
 517 #endif
 518 #ifdef CONFIG_TSEC2
 519         SET_STD_TSEC_INFO(tsec_info[num], 2);
 520         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 521                 tsec_info[num].flags |= TSEC_SGMII;
 522         num++;
 523 #endif
 524 #ifdef CONFIG_TSEC3
 525         SET_STD_TSEC_INFO(tsec_info[num], 3);
 526         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 527                 tsec_info[num].flags |= TSEC_SGMII;
 528         num++;
 529 #endif
 530 #ifdef CONFIG_TSEC4
 531         SET_STD_TSEC_INFO(tsec_info[num], 4);
 532         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 533                 tsec_info[num].flags |= TSEC_SGMII;
 534         num++;
 535 #endif
 536
 537         if (!num) {
 538                 printf("No TSECs initialized\n");
 539
 540                 return 0;
 541         }
 542
 543         fsl_sgmii_riser_init(tsec_info, num);
 544
 545         tsec_eth_init(bis, tsec_info, num);
 546
 547         return 0;
 548 }
 549 #endif
 550
 551 #if defined(CONFIG_OF_BOARD_SETUP)
 552 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
 553                         struct pci_controller *hose);
 554
 555 void ft_board_setup(void *blob, bd_t *bd)
 556 {
 557         ulong base, size;
 558
 559         ft_cpu_setup(blob, bd);
 560
 561         base = getenv_bootm_low();
 562         size = getenv_bootm_size();
 563
 564         fdt_fixup_memory(blob, (u64)base, (u64)size);
 565
 566 #ifdef CONFIG_PCIE3
 567         ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
 568 #endif
 569 #ifdef CONFIG_PCIE2
 570         ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 571 #endif
 572 #ifdef CONFIG_PCIE1
 573         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 574 #endif
 575 }
 576 #endif
 577
 578 #ifdef CONFIG_MP
 579 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
 580
 581 void board_lmb_reserve(struct lmb *lmb)
 582 {
 583         cpu_mp_lmb_reserve(lmb);
 584 }
 585 #endif