board/freescale/mpc8610hpcd/ddr.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <i2c.h>
  11
  12 #include <asm/fsl_ddr_sdram.h>
  13 #include <asm/fsl_ddr_dimm_params.h>
  14
  15 static void
  16 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
  17 {
  18         i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
  19 }
  20
  21 unsigned int fsl_ddr_get_mem_data_rate(void)
  22 {
  23         return get_bus_freq(0);
  24 }
  25
  26 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
  27                       unsigned int ctrl_num)
  28 {
  29         unsigned int i;
  30         unsigned int i2c_address = 0;
  31
  32         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  33                 if (ctrl_num == 0 && i == 0) {
  34                         i2c_address = SPD_EEPROM_ADDRESS1;
  35                 }
  36                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
  37         }
  38 }
  39
  40 void fsl_ddr_board_options(memctl_options_t *popts,
  41                                 dimm_params_t *pdimm,
  42                                 unsigned int ctrl_num)
  43 {
  44         /*
  45          * Factors to consider for clock adjust:
  46          *      - number of chips on bus
  47          *      - position of slot
  48          *      - DDR1 vs. DDR2?
  49          *      - ???
  50          *
  51          * This needs to be determined on a board-by-board basis.
  52          *      0110    3/4 cycle late
  53          *      0111    7/8 cycle late
  54          */
  55         popts->clk_adjust = 7;
  56
  57         /*
  58          * Factors to consider for CPO:
  59          *      - frequency
  60          *      - ddr1 vs. ddr2
  61          */
  62         popts->cpo_override = 10;
  63
  64         /*
  65          * Factors to consider for write data delay:
  66          *      - number of DIMMs
  67          *
  68          * 1 = 1/4 clock delay
  69          * 2 = 1/2 clock delay
  70          * 3 = 3/4 clock delay
  71          * 4 = 1   clock delay
  72          * 5 = 5/4 clock delay
  73          * 6 = 3/2 clock delay
  74          */
  75         popts->write_data_delay = 3;
  76
  77         /* 2T timing enable */
  78         popts->twoT_en = 1;
  79
  80         /*
  81          * Factors to consider for half-strength driver enable:
  82          *      - number of DIMMs installed
  83          */
  84         popts->half_strength_driver_enable = 0;
  85 }