board/freescale/mx51_3stack/mx51_3stack.c

   1 /*
   2  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
   3  *
   4  * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/errno.h>
  28 #include <asm/arch/mx51.h>
  29 #include <asm/arch/mx51_pins.h>
  30 #include <asm/arch/iomux.h>
  31 #include <i2c.h>
  32 #include <asm/arch/keypad.h>
  33 #include "board-mx51_3stack.h"
  34 #include <netdev.h>
  35
  36 #ifdef CONFIG_CMD_MMC
  37 #include <mmc.h>
  38 #include <fsl_esdhc.h>
  39 #endif
  40
  41 #ifdef CONFIG_ARCH_MMU
  42 #include <asm/mmu.h>
  43 #include <asm/arch/mmu.h>
  44 #endif
  45
  46 #ifdef CONFIG_FSL_ANDROID
  47 #include <mxc_keyb.h>
  48 #include <part.h>
  49 #include <ext2fs.h>
  50 #include <linux/mtd/mtd.h>
  51 #include <linux/mtd/partitions.h>
  52 #include <ubi_uboot.h>
  53 #include <jffs2/load_kernel.h>
  54 #endif
  55
  56 DECLARE_GLOBAL_DATA_PTR;
  57
  58 static u32 system_rev;
  59 static enum boot_device boot_dev;
  60 u32     mx51_io_base_addr;
  61
  62 static inline void setup_boot_device(void)
  63 {
  64         uint *fis_addr = (uint *)IRAM_BASE_ADDR;
  65
  66         switch (*fis_addr) {
  67         case NAND_FLASH_BOOT:
  68                 boot_dev = NAND_BOOT;
  69                 break;
  70         case SPI_NOR_FLASH_BOOT:
  71                 boot_dev = SPI_NOR_BOOT;
  72                 break;
  73         case MMC_FLASH_BOOT:
  74                 boot_dev = MMC_BOOT;
  75                 break;
  76         default:
  77                 {
  78                         uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
  79                         uint bt_mem_ctl = soc_sbmr & 0x00000003;
  80                         uint bt_mem_type = (soc_sbmr & 0x00000180) >> 7;
  81
  82                         switch (bt_mem_ctl) {
  83                         case 0x3:
  84                                 if (bt_mem_type == 0)
  85                                         boot_dev = MMC_BOOT;
  86                                 else if (bt_mem_type == 3)
  87                                         boot_dev = SPI_NOR_BOOT;
  88                                 else
  89                                         boot_dev = UNKNOWN_BOOT;
  90                                 break;
  91                         case 0x1:
  92                                 boot_dev = NAND_BOOT;
  93                                 break;
  94                         default:
  95                                 boot_dev = UNKNOWN_BOOT;
  96                         }
  97                 }
  98                 break;
  99         }
 100 }
 101
 102 enum boot_device get_boot_device(void)
 103 {
 104         return boot_dev;
 105 }
 106
 107 u32 get_board_rev(void)
 108 {
 109         return system_rev;
 110 }
 111
 112 static inline void setup_soc_rev(void)
 113 {
 114         int reg;
 115 #ifdef CONFIG_ARCH_MMU
 116         reg = __REG(0x20000000 + ROM_SI_REV); /* Virtual address */
 117 #else
 118         reg = __REG(ROM_SI_REV); /* Virtual address */
 119 #endif
 120
 121         switch (reg) {
 122         case 0x02:
 123                 system_rev = 0x51000 | CHIP_REV_1_1;
 124                 break;
 125         case 0x10:
 126                 system_rev = 0x51000 | CHIP_REV_2_0;
 127                 break;
 128         default:
 129                 system_rev = 0x51000 | CHIP_REV_1_0;
 130         }
 131 }
 132
 133 static inline void set_board_rev(int rev)
 134 {
 135         system_rev |= (rev & 0xF) << 8;
 136 }
 137
 138 inline int is_soc_rev(int rev)
 139 {
 140         return (system_rev & 0xFF) - rev;
 141 }
 142
 143 #ifdef CONFIG_ARCH_MMU
 144 void board_mmu_init(void)
 145 {
 146         unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
 147         unsigned long i;
 148
 149         /*
 150         * Set the TTB register
 151         */
 152         asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/);
 153
 154         /*
 155         * Set the Domain Access Control Register
 156         */
 157         i = ARM_ACCESS_DACR_DEFAULT;
 158         asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/);
 159
 160         /*
 161         * First clear all TT entries - ie Set them to Faulting
 162         */
 163         memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
 164         /* Actual   Virtual  Size   Attributes          Function */
 165         /* Base     Base     MB     cached? buffered?  access permissions */
 166         /* xxx00000 xxx00000 */
 167         X_ARM_MMU_SECTION(0x000, 0x200, 0x1,
 168                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 169                         ARM_ACCESS_PERM_RW_RW); /* ROM */
 170         X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001,
 171                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 172                         ARM_ACCESS_PERM_RW_RW); /* IRAM */
 173         X_ARM_MMU_SECTION(0x300, 0x300, 0x100,
 174                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 175                         ARM_ACCESS_PERM_RW_RW); /* GPU */
 176         X_ARM_MMU_SECTION(0x400, 0x400, 0x200,
 177                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 178                         ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
 179         X_ARM_MMU_SECTION(0x600, 0x600, 0x300,
 180                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 181                         ARM_ACCESS_PERM_RW_RW); /* periperals */
 182         X_ARM_MMU_SECTION(0x900, 0x000, 0x080,
 183                         ARM_CACHEABLE, ARM_BUFFERABLE,
 184                         ARM_ACCESS_PERM_RW_RW); /* SDRAM */
 185         X_ARM_MMU_SECTION(0x900, 0x900, 0x080,
 186                         ARM_CACHEABLE, ARM_BUFFERABLE,
 187                         ARM_ACCESS_PERM_RW_RW); /* SDRAM */
 188         X_ARM_MMU_SECTION(0x900, 0x980, 0x080,
 189                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 190                         ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
 191         X_ARM_MMU_SECTION(0xA00, 0xA00, 0x100,
 192                         ARM_CACHEABLE, ARM_BUFFERABLE,
 193                         ARM_ACCESS_PERM_RW_RW); /* SDRAM */
 194         X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10,
 195                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 196                         ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
 197         X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040,
 198                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 199                         ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
 200
 201         /* Workaround for arm errata #709718 */
 202         /* Setup PRRR so device is always mapped to non-shared */
 203         asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
 204         i &= (~(3 << 0x10));
 205         asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
 206
 207         /* Enable MMU */
 208         MMU_ON();
 209 }
 210 #endif
 211
 212 int dram_init(void)
 213 {
 214         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 215         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 216         return 0;
 217 }
 218
 219 static void setup_uart(void)
 220 {
 221         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 222                          PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
 223         mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
 224         mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
 225         mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
 226         mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
 227         mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
 228         mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
 229         mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
 230         mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
 231 }
 232
 233 void setup_nfc(void)
 234 {
 235         /* Enable NFC IOMUX */
 236         mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
 237         mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
 238         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0);
 239         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0);
 240         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0);
 241         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0);
 242         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0);
 243         mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0);
 244 }
 245
 246 static void setup_expio(void)
 247 {
 248         u32 reg;
 249         /* CS5 setup */
 250         mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
 251         writel(0x00410089, WEIM_BASE_ADDR + 0x78 + CSGCR1);
 252         writel(0x00000002, WEIM_BASE_ADDR + 0x78 + CSGCR2);
 253         /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
 254         writel(0x32260000, WEIM_BASE_ADDR + 0x78 + CSRCR1);
 255         /* APR = 0 */
 256         writel(0x00000000, WEIM_BASE_ADDR + 0x78 + CSRCR2);
 257         /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
 258          * WCSA=0, WCSN=0
 259          */
 260         writel(0x72080F00, WEIM_BASE_ADDR + 0x78 + CSWCR1);
 261         if ((readw(CS5_BASE_ADDR + PBC_ID_AAAA) == 0xAAAA) &&
 262             (readw(CS5_BASE_ADDR + PBC_ID_5555) == 0x5555)) {
 263                 if (is_soc_rev(CHIP_REV_2_0) < 0) {
 264                         reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
 265                         reg = (reg & (~0x70000)) | 0x30000;
 266                         writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
 267                         /* make sure divider effective */
 268                         while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
 269                                 ;
 270                         writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
 271                 }
 272                 mx51_io_base_addr = CS5_BASE_ADDR;
 273         } else {
 274                 /* CS1 */
 275                 writel(0x00410089, WEIM_BASE_ADDR + 0x18 + CSGCR1);
 276                 writel(0x00000002, WEIM_BASE_ADDR + 0x18 + CSGCR2);
 277                 /*  RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
 278                 writel(0x32260000, WEIM_BASE_ADDR + 0x18 + CSRCR1);
 279                 /* APR=0 */
 280                 writel(0x00000000, WEIM_BASE_ADDR + 0x18 + CSRCR2);
 281                 /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
 282                  * WEN=0, WCSA=0, WCSN=0
 283                  */
 284                 writel(0x72080F00, WEIM_BASE_ADDR + 0x18 + CSWCR1);
 285                 mx51_io_base_addr = CS1_BASE_ADDR;
 286         }
 287
 288         /* Reset interrupt status reg */
 289         writew(0x1F, mx51_io_base_addr + PBC_INT_REST);
 290         writew(0x00, mx51_io_base_addr + PBC_INT_REST);
 291         writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK);
 292
 293         /* Reset the XUART and Ethernet controllers */
 294         reg = readw(mx51_io_base_addr + PBC_SW_RESET);
 295         reg |= 0x9;
 296         writew(reg, mx51_io_base_addr + PBC_SW_RESET);
 297         reg &= ~0x9;
 298         writew(reg, mx51_io_base_addr + PBC_SW_RESET);
 299 }
 300
 301 #if defined(CONFIG_MXC_ATA)
 302 int setup_ata(void)
 303 {
 304         u32 pad;
 305
 306         pad = (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH);
 307
 308         /* Need to disable nand iomux first */
 309         mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
 310         mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, pad);
 311
 312         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
 313         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, pad);
 314
 315         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
 316         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, pad);
 317
 318         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
 319         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, pad);
 320
 321         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
 322         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, pad);
 323
 324         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
 325         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, pad);
 326
 327         mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
 328         mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, pad);
 329
 330         mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
 331         mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, pad);
 332
 333         mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
 334         mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, pad);
 335
 336         mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
 337         mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, pad);
 338
 339         mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
 340         mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, pad);
 341
 342         /* TO 2.0 */
 343         mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
 344         mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, pad);
 345
 346         /* TO 1.0 */
 347         mxc_request_iomux(MX51_PIN_NANDF_RB5, IOMUX_CONFIG_ALT1);
 348         mxc_iomux_set_pad(MX51_PIN_NANDF_RB5, pad);
 349
 350         mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
 351         mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, pad);
 352
 353         mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
 354         mxc_iomux_set_pad(MX51_PIN_NANDF_D0, pad);
 355
 356         mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
 357         mxc_iomux_set_pad(MX51_PIN_NANDF_D1, pad);
 358
 359         mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
 360         mxc_iomux_set_pad(MX51_PIN_NANDF_D2, pad);
 361
 362         mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
 363         mxc_iomux_set_pad(MX51_PIN_NANDF_D3, pad);
 364
 365         mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
 366         mxc_iomux_set_pad(MX51_PIN_NANDF_D4, pad);
 367
 368         mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
 369         mxc_iomux_set_pad(MX51_PIN_NANDF_D5, pad);
 370
 371         mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
 372         mxc_iomux_set_pad(MX51_PIN_NANDF_D6, pad);
 373
 374         mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
 375         mxc_iomux_set_pad(MX51_PIN_NANDF_D7, pad);
 376
 377         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
 378         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, pad);
 379
 380         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
 381         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, pad);
 382
 383         mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
 384         mxc_iomux_set_pad(MX51_PIN_NANDF_D10, pad);
 385
 386         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
 387         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, pad);
 388
 389         mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
 390         mxc_iomux_set_pad(MX51_PIN_NANDF_D12, pad);
 391
 392         mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
 393         mxc_iomux_set_pad(MX51_PIN_NANDF_D13, pad);
 394
 395         mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
 396         mxc_iomux_set_pad(MX51_PIN_NANDF_D14, pad);
 397
 398         mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
 399         mxc_iomux_set_pad(MX51_PIN_NANDF_D15, pad);
 400
 401         return 0;
 402 }
 403 #endif
 404
 405 #ifdef CONFIG_I2C_MXC
 406 static setup_i2c(unsigned int module_base)
 407 {
 408         unsigned int reg;
 409
 410         switch (module_base) {
 411         case I2C1_BASE_ADDR:
 412                 reg = IOMUXC_BASE_ADDR + 0x210; /* i2c SDA */
 413                 writel(0x11, reg);
 414                 reg = IOMUXC_BASE_ADDR + 0x600;
 415                 writel(0x1ad, reg);
 416                 reg = IOMUXC_BASE_ADDR + 0x9B4;
 417                 writel(0x1, reg);
 418
 419                 reg = IOMUXC_BASE_ADDR + 0x224; /* i2c SCL */
 420                 writel(0x11, reg);
 421                 reg = IOMUXC_BASE_ADDR + 0x614;
 422                 writel(0x1ad, reg);
 423                 reg = IOMUXC_BASE_ADDR + 0x9B0;
 424                 writel(0x1, reg);
 425                 break;
 426         case I2C2_BASE_ADDR:
 427                 /* Workaround for Atlas Lite */
 428                 writel(0x0, IOMUXC_BASE_ADDR + 0x3CC); /* i2c SCL */
 429                 writel(0x0, IOMUXC_BASE_ADDR + 0x3D0); /* i2c SDA */
 430                 reg = readl(GPIO1_BASE_ADDR + 0x0);
 431                 reg |= 0xC;  /* write a 1 on the SCL and SDA lines */
 432                 writel(reg, GPIO1_BASE_ADDR + 0x0);
 433                 reg = readl(GPIO1_BASE_ADDR + 0x4);
 434                 reg |= 0xC;  /* configure GPIO lines as output */
 435                 writel(reg, GPIO1_BASE_ADDR + 0x4);
 436                 reg = readl(GPIO1_BASE_ADDR + 0x0);
 437                 reg &= ~0x4 ; /* set SCL low for a few milliseconds */
 438                 writel(reg, GPIO1_BASE_ADDR + 0x0);
 439                 udelay(20000);
 440                 reg |= 0x4;
 441                 writel(reg, GPIO1_BASE_ADDR + 0x0);
 442                 udelay(10);
 443                 reg = readl(GPIO1_BASE_ADDR + 0x4);
 444                 reg &= ~0xC;  /* configure GPIO lines back as input */
 445                 writel(reg, GPIO1_BASE_ADDR + 0x4);
 446
 447                 writel(0x12, IOMUXC_BASE_ADDR + 0x3CC);  /* i2c SCL */
 448                 writel(0x3, IOMUXC_BASE_ADDR + 0x9B8);
 449                 writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D4);
 450
 451                 writel(0x12, IOMUXC_BASE_ADDR + 0x3D0); /* i2c SDA */
 452                 writel(0x3, IOMUXC_BASE_ADDR + 0x9BC);
 453                 writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D8);
 454                 break;
 455         default:
 456                 printf("Invalid I2C base: 0x%x\n", module_base);
 457                 break;
 458         }
 459 }
 460
 461 #define REV_ATLAS_LITE_1_0         0x8
 462 #define REV_ATLAS_LITE_1_1         0x9
 463 #define REV_ATLAS_LITE_2_0         0x10
 464 #define REV_ATLAS_LITE_2_1         0x11
 465
 466 void setup_core_voltages(void)
 467 {
 468         unsigned char buf[4] = { 0 };
 469
 470         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 471
 472         if (is_soc_rev(CHIP_REV_2_0) <= 0) {
 473                 /* Set core voltage to 1.1V */
 474                 if (i2c_read(0x8, 24, 1, buf, 3)) {
 475                         puts("setup_core_voltages: read PMIC@0x08:0x18 fail\n");
 476                         return;
 477                 }
 478                 buf[2] = (buf[2] & (~0x1F)) | 0x14;
 479                 if (i2c_write(0x8, 24, 1, buf, 3)) {
 480                         puts("setup_core_voltages: write PMIC@0x08:0x18 fail\n");
 481                         return;
 482                 }
 483
 484                 /* Setup VCC (SW2) to 1.25 */
 485                 if (i2c_read(0x8, 25, 1, buf, 3)) {
 486                         puts("setup_core_voltages: read PMIC@0x08:0x19 fail\n");
 487                         return;
 488                 }
 489                 buf[2] = (buf[2] & (~0x1F)) | 0x1A;
 490                 if (i2c_write(0x8, 25, 1, buf, 3)) {
 491                         puts("setup_core_voltages: write PMIC@0x08:0x19 fail\n");
 492                         return;
 493                 }
 494
 495                 /* Setup 1V2_DIG1 (SW3) to 1.25 */
 496                 if (i2c_read(0x8, 26, 1, buf, 3)) {
 497                         puts("setup_core_voltages: read PMIC@0x08:0x1A fail\n");
 498                         return;
 499                 }
 500                 buf[2] = (buf[2] & (~0x1F)) | 0x1A;
 501                 if (i2c_write(0x8, 26, 1, buf, 3)) {
 502                         puts("setup_core_voltages: write PMIC@0x08:0x1A fail\n");
 503                         return;
 504                 }
 505
 506                 udelay(50);
 507
 508                 /* Raise the core frequency to 800MHz */
 509                 writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
 510         } else {
 511                 /* TO 3.0 */
 512                 /* Setup VCC (SW2) to 1.225 */
 513                 if (i2c_read(0x8, 25, 1, buf, 3)) {
 514                         puts("setup_core_voltages: read PMIC@0x08:0x19 fail\n");
 515                         return;
 516                 }
 517                 buf[2] = (buf[2] & (~0x1F)) | 0x19;
 518                 if (i2c_write(0x8, 25, 1, buf, 3)) {
 519                         puts("setup_core_voltages: write PMIC@0x08:0x19 fail\n");
 520                         return;
 521                 }
 522
 523                 /* Setup 1V2_DIG1 (SW3) to 1.2 */
 524                 if (i2c_read(0x8, 26, 1, buf, 3)) {
 525                         puts("setup_core_voltages: read PMIC@0x08:0x1A fail\n");
 526                         return;
 527                 }
 528                 buf[2] = (buf[2] & (~0x1F)) | 0x18;
 529                 if (i2c_write(0x8, 26, 1, buf, 3)) {
 530                         puts("setup_core_voltages: write PMIC@0x08:0x1A fail\n");
 531                         return;
 532                 }
 533         }
 534
 535         if (i2c_read(0x8, 7, 1, buf, 3)) {
 536                 puts("setup_core_voltages: read PMIC@0x08:0x07 fail\n");
 537                 return;
 538         }
 539
 540         if (((buf[2] & 0x1F) < REV_ATLAS_LITE_2_0) || (((buf[1] >> 1) & 0x3) == 0)) {
 541                 /* Set switchers in PWM mode for Atlas 2.0 and lower */
 542                 /* Setup the switcher mode for SW1 & SW2*/
 543                 if (i2c_read(0x8, 28, 1, buf, 3)) {
 544                         puts("setup_core_voltages: read PMIC@0x08:0x1C fail\n");
 545                         return;
 546                 }
 547                 buf[2] = (buf[2] & (~0xF)) | 0x5;
 548                 buf[1] = (buf[1] & (~0x3C)) | 0x14;
 549                 if (i2c_write(0x8, 28, 1, buf, 3)) {
 550                         puts("setup_core_voltages: write PMIC@0x08:0x1C fail\n");
 551                         return;
 552                 }
 553
 554                 /* Setup the switcher mode for SW3 & SW4*/
 555                 if (i2c_read(0x8, 29, 1, buf, 3)) {
 556                         puts("setup_core_voltages: read PMIC@0x08:0x1D fail\n");
 557                         return;
 558                 }
 559                 buf[2] = (buf[2] & (~0xF)) | 0x5;
 560                 buf[1] = (buf[1] & (~0xF)) | 0x5;
 561                 if (i2c_write(0x8, 29, 1, buf, 3)) {
 562                         puts("setup_core_voltages: write PMIC@0x08:0x1D fail\n");
 563                         return;
 564                 }
 565         } else {
 566                 /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
 567                 /* Setup the switcher mode for SW1 & SW2*/
 568                 if (i2c_read(0x8, 28, 1, buf, 3)) {
 569                         puts("setup_core_voltages: read PMIC@0x08:0x1C fail\n");
 570                         return;
 571                 }
 572                 buf[2] = (buf[2] & (~0xF)) | 0x8;
 573                 buf[1] = (buf[1] & (~0x3C)) | 0x20;
 574                 if (i2c_write(0x8, 28, 1, buf, 3)) {
 575                         puts("setup_core_voltages: write PMIC@0x08:0x1C fail\n");
 576                         return;
 577                 }
 578
 579                 /* Setup the switcher mode for SW3 & SW4*/
 580                 if (i2c_read(0x8, 29, 1, buf, 3)) {
 581                         puts("setup_core_voltages: read PMIC@0x08:0x1D fail\n");
 582                         return;
 583                 }
 584                 buf[2] = (buf[2] & (~0xF)) | 0x8;
 585                 buf[1] = (buf[1] & (~0xF)) | 0x8;
 586                 if (i2c_write(0x8, 29, 1, buf, 3)) {
 587                         puts("setup_core_voltages: write PMIC@0x08:0x1D fail\n");
 588                         return;
 589                 }
 590         }
 591 }
 592
 593 #endif
 594
 595 int board_init(void)
 596 {
 597         setup_boot_device();
 598         setup_soc_rev();
 599
 600         gd->bd->bi_arch_number = MACH_TYPE_MX51_3DS;    /* board id for linux */
 601         /* address of boot parameters */
 602         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 603
 604         setup_uart();
 605         setup_nfc();
 606         setup_expio();
 607 #ifdef CONFIG_I2C_MXC
 608         setup_i2c(I2C2_BASE_ADDR);
 609         setup_core_voltages();
 610 #endif
 611         return 0;
 612 }
 613
 614 #ifdef BOARD_LATE_INIT
 615
 616 #if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD)
 617 static int waiting_for_func_key_pressing(void)
 618 {
 619         struct kpp_key_info key_info = {0, 0};
 620         int switch_delay = CONFIG_ANDROID_BOOTMOD_DELAY;
 621         int state = 0, boot_mode_switch = 0;
 622
 623         mxc_kpp_init();
 624
 625         puts("Press home + power to enter recovery mode ...\n");
 626
 627         while ((switch_delay > 0) && (!boot_mode_switch)) {
 628                 int i;
 629
 630                 --switch_delay;
 631                 /* delay 100 * 10ms */
 632                 for (i = 0; !boot_mode_switch && i < 100; ++i) {
 633                         /* A state machine to scan home + power key */
 634                         /* Check for home + power */
 635                         if (mxc_kpp_getc(&key_info)) {
 636                                 switch (state) {
 637                                 case 0:
 638                                         /* First press */
 639                                         if (TEST_HOME_KEY_DEPRESS(key_info.val, key_info.evt)) {
 640                                                 /* Press Home */
 641                                                 state = 1;
 642                                         } else if (TEST_POWER_KEY_DEPRESS(key_info.val, key_info.evt)) {
 643                                                 state = 2;
 644                                         } else {
 645                                                 state = 0;
 646                                         }
 647                                         break;
 648                                 case 1:
 649                                         /* Home is already pressed, try to detect Power */
 650                                         if (TEST_POWER_KEY_DEPRESS(key_info.val,
 651                                                     key_info.evt)) {
 652                                                 boot_mode_switch = 1;
 653                                         } else {
 654                                             if (TEST_HOME_KEY_DEPRESS(key_info.val,
 655                                                         key_info.evt))
 656                                                 state = 2;
 657                                             else
 658                                                 state = 0;
 659                                         }
 660                                         break;
 661                                 case 2:
 662                                         /* Power is already pressed, try to detect Home */
 663                                         if (TEST_HOME_KEY_DEPRESS(key_info.val,
 664                                                     key_info.evt)) {
 665                                                 boot_mode_switch = 1;
 666                                         } else {
 667                                                 if (TEST_POWER_KEY_DEPRESS(key_info.val,
 668                                                             key_info.evt))
 669                                                         state = 1;
 670                                                 else
 671                                                         state = 0;
 672                                         }
 673                                         break;
 674                                 default:
 675                                         break;
 676                                 }
 677
 678                                 if (1 == boot_mode_switch)
 679                                         return 1;
 680                         }
 681                 }
 682                 for (i = 0; i < 100; ++i)
 683                         udelay(10000);
 684         }
 685
 686         return 0;
 687 }
 688
 689 static int switch_to_recovery_mode(void)
 690 {
 691         char *env = NULL;
 692         char *boot_args = NULL;
 693         char *boot_cmd = NULL;
 694
 695         printf("Boot mode switched to recovery mode!\n");
 696
 697         switch (get_boot_device()) {
 698         case MMC_BOOT:
 699                 boot_args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC;
 700                 boot_cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC;
 701                 break;
 702         case NAND_BOOT:
 703                 boot_args = CONFIG_ANDROID_RECOVERY_BOOTARGS_NAND;
 704                 boot_cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_NAND;
 705                 break;
 706         case SPI_NOR_BOOT:
 707                 printf("Recovery mode not supported in SPI NOR boot\n");
 708                 return -1;
 709                 break;
 710         case UNKNOWN_BOOT:
 711         default:
 712                 printf("Unknown boot device!\n");
 713                 return -1;
 714                 break;
 715         }
 716
 717         env = getenv("bootargs_android_recovery");
 718         /* Set env to recovery mode */
 719         if (!env)
 720                 setenv("bootargs_android", boot_args);
 721         else
 722                 setenv("bootargs_android", env);
 723
 724         env = getenv("bootcmd_android_recovery");
 725         if (!env)
 726                 setenv("bootcmd_android", boot_cmd);
 727         else
 728                 setenv("bootcmd_android", env);
 729         setenv("bootcmd", "run bootcmd_android");
 730
 731         return 0;
 732 }
 733
 734 static int check_mmc_recovery_cmd_file(int dev_num, int part_num, char *path)
 735 {
 736         block_dev_desc_t *dev_desc = NULL;
 737         struct mmc *mmc = find_mmc_device(dev_num);
 738         disk_partition_t info;
 739         ulong part_length = 0;
 740         int filelen = 0;
 741
 742         memset(&info, 0, sizeof(disk_partition_t));
 743
 744         dev_desc = get_dev("mmc", dev_num);
 745
 746         if (NULL == dev_desc) {
 747                 printf("** Block device MMC %d not supported\n",
 748                                 dev_num);
 749                 return 0;
 750         }
 751
 752         mmc_init(mmc);
 753
 754         if (get_partition_info(dev_desc,
 755                         part_num,
 756                         &info)) {
 757                 printf("** Bad partition %d **\n",
 758                         part_num);
 759                 return 0;
 760         }
 761
 762         part_length = ext2fs_set_blk_dev(dev_desc,
 763                                                 part_num);
 764         if (part_length == 0) {
 765                 printf("** Bad partition - mmc 0:%d **\n",
 766                         part_num);
 767                 ext2fs_close();
 768                 return 0;
 769         }
 770
 771         if (!ext2fs_mount(part_length)) {
 772                 printf("** Bad ext2 partition or disk - mmc 0:%d **\n",
 773                         part_num);
 774                 ext2fs_close();
 775                 return 0;
 776         }
 777
 778         filelen = ext2fs_open(path);
 779
 780         ext2fs_close();
 781
 782         return (filelen > 0) ? 1 : 0;
 783 }
 784
 785 extern int ubifs_init(void);
 786 extern int ubifs_mount(char *vol_name);
 787 extern int ubifs_load(char *filename, u32 addr, u32 size);
 788
 789 static int check_nand_recovery_cmd_file(char *mtd_part_name,
 790                                 char *ubi_part_name,
 791                                 char *path)
 792 {
 793         struct mtd_device *dev_desc = NULL;
 794         struct part_info *part = NULL;
 795         struct mtd_partition mtd_part;
 796         struct mtd_info *mtd_info = NULL;
 797         char mtd_dev[16] = { 0 };
 798         char mtd_buffer[80] = { 0 };
 799         u8 pnum = 0,
 800            read_test = 0;
 801         int err = 0,
 802                 filelen = 0;
 803
 804         memset(&mtd_part, 0, sizeof(struct mtd_partition));
 805
 806         /* ========== ubi and mtd operations ========== */
 807         if (mtdparts_init() != 0) {
 808                 printf("Error initializing mtdparts!\n");
 809                 return 0;
 810         }
 811
 812         if (find_dev_and_part(mtd_part_name, &dev_desc, &pnum, &part)) {
 813                 printf("Partition %s not found!\n", mtd_part_name);
 814                 return 0;
 815         }
 816         sprintf(mtd_dev, "%s%d",
 817                         MTD_DEV_TYPE(dev_desc->id->type),
 818                         dev_desc->id->num);
 819         mtd_info = get_mtd_device_nm(mtd_dev);
 820         if (IS_ERR(mtd_info)) {
 821                 printf("Partition %s not found on device %s!\n",
 822                         "nand", mtd_dev);
 823                 return 0;
 824         }
 825
 826         sprintf(mtd_buffer, "mtd=%d", pnum);
 827         memset(&mtd_part, 0, sizeof(mtd_part));
 828         mtd_part.name = mtd_buffer;
 829         mtd_part.size = part->size;
 830         mtd_part.offset = part->offset;
 831         add_mtd_partitions(mtd_info, &mtd_part, 1);
 832
 833         err = ubi_mtd_param_parse(mtd_buffer, NULL);
 834         if (err) {
 835                 del_mtd_partitions(mtd_info);
 836                 return 0;
 837         }
 838
 839         err = ubi_init();
 840         if (err) {
 841                 del_mtd_partitions(mtd_info);
 842                 return 0;
 843         }
 844
 845         /* ========== ubifs operations ========== */
 846         /* Init ubifs */
 847         ubifs_init();
 848
 849         if (ubifs_mount(ubi_part_name)) {
 850                 printf("Mount ubifs volume %s fail!\n",
 851                                 ubi_part_name);
 852                 return 0;
 853         }
 854
 855         /* Try to read one byte for a read test. */
 856         if (ubifs_load(path, (u32)&read_test, 1)) {
 857                 /* File not found */
 858                 filelen = 0;
 859         } else
 860                 filelen = 1;
 861
 862         return filelen;
 863 }
 864
 865 static int check_recovery_cmd_file(void)
 866 {
 867         int if_exist = 0;
 868         char *env = NULL;
 869
 870         switch (get_boot_device()) {
 871         case MMC_BOOT:
 872                 if_exist = check_mmc_recovery_cmd_file(0,
 873                                 CONFIG_ANDROID_CACHE_PARTITION_MMC,
 874                                 CONFIG_ANDROID_RECOVERY_CMD_FILE);
 875                 break;
 876         case NAND_BOOT:
 877                 env = getenv("mtdparts");
 878                 if (!env)
 879                         setenv("mtdparts", MTDPARTS_DEFAULT);
 880
 881                 env = getenv("mtdids");
 882                 if (!env)
 883                         setenv("mtdids", MTDIDS_DEFAULT);
 884
 885                 env = getenv("partition");
 886                 if (!env)
 887                         setenv("partition", MTD_ACTIVE_PART);
 888
 889                 /*
 890                 if_exist = check_nand_recovery_cmd_file(CONFIG_ANDROID_UBIFS_PARTITION_NM,
 891                                                 CONFIG_ANDROID_CACHE_PARTITION_NAND,
 892                                                 CONFIG_ANDROID_RECOVERY_CMD_FILE);
 893                 */
 894                 break;
 895         case SPI_NOR_BOOT:
 896                 return 0;
 897                 break;
 898         case UNKNOWN_BOOT:
 899         default:
 900                 return 0;
 901                 break;
 902         }
 903
 904         return if_exist;
 905 }
 906 #endif
 907
 908 int board_late_init(void)
 909 {
 910 #if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD)
 911         if (waiting_for_func_key_pressing())
 912                 switch_to_recovery_mode();
 913         else {
 914                 if (check_recovery_cmd_file()) {
 915                         puts("Recovery command file detected!\n");
 916                         switch_to_recovery_mode();
 917                 }
 918         }
 919 #endif
 920
 921         return 0;
 922 }
 923 #endif
 924
 925 int checkboard(void)
 926 {
 927         printf("Board: MX51 3STACK ");
 928
 929         if (system_rev & CHIP_REV_2_0) {
 930                 printf("2.0 [");
 931         } else if (system_rev & CHIP_REV_1_1) {
 932                 printf("1.1 [");
 933         } else {
 934                 printf("1.0 [");
 935         }
 936
 937         switch (__REG(SRC_BASE_ADDR + 0x8)) {
 938         case 0x0001:
 939                 printf("POR");
 940                 break;
 941         case 0x0009:
 942                 printf("RST");
 943                 break;
 944         case 0x0010:
 945         case 0x0011:
 946                 printf("WDOG");
 947                 break;
 948         default:
 949                 printf("unknown");
 950         }
 951         printf("]\n");
 952
 953         printf("Boot Device: ");
 954         switch (get_boot_device()) {
 955         case NAND_BOOT:
 956                 printf("NAND\n");
 957                 break;
 958         case SPI_NOR_BOOT:
 959                 printf("SPI NOR\n");
 960                 break;
 961         case MMC_BOOT:
 962                 printf("MMC\n");
 963                 break;
 964         case UNKNOWN_BOOT:
 965         default:
 966                 printf("UNKNOWN\n");
 967                 break;
 968         }
 969
 970         return 0;
 971 }
 972
 973 #if defined(CONFIG_SMC911X)
 974 extern int smc911x_initialize(u8 dev_num, int base_addr);
 975 #endif
 976
 977 #ifdef CONFIG_NET_MULTI
 978 int board_eth_init(bd_t *bis)
 979 {
 980         int rc = -ENODEV;
 981 #if defined(CONFIG_SMC911X)
 982         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 983 #endif
 984
 985         cpu_eth_init(bis);
 986
 987         return rc;
 988 }
 989 #endif
 990
 991 #ifdef CONFIG_CMD_MMC
 992
 993 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 994         {MMC_SDHC1_BASE_ADDR, 1, 1},
 995 };
 996
 997 #ifdef CONFIG_DYNAMIC_MMC_DEVNO
 998 int get_mmc_env_devno()
 999 {
1000         uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
1001         return (soc_sbmr & 0x00180000) ? 1 : 0;
1002 }
1003 #endif
1004
1005 int esdhc_gpio_init(bd_t *bis)
1006 {
1007         u32 index = 0;
1008         s32 status = 0;
1009
1010         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
1011                 ++index) {
1012                 switch (index) {
1013                 case 0:
1014                         mxc_request_iomux(MX51_PIN_SD1_CMD,
1015                                   IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
1016                         mxc_request_iomux(MX51_PIN_SD1_CLK,
1017                                   IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
1018
1019                         mxc_request_iomux(MX51_PIN_SD1_DATA0,
1020                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
1021                         mxc_request_iomux(MX51_PIN_SD1_DATA1,
1022                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
1023                         mxc_request_iomux(MX51_PIN_SD1_DATA2,
1024                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
1025                         mxc_request_iomux(MX51_PIN_SD1_DATA3,
1026                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
1027                         mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
1028                                         PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
1029                                         PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
1030                                         PAD_CTL_PUE_PULL |
1031                                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
1032                         mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
1033                                         PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
1034                                         PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
1035                                         PAD_CTL_PUE_PULL |
1036                                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
1037                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
1038                                         PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
1039                                         PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
1040                                         PAD_CTL_PUE_PULL |
1041                                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
1042                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
1043                                         PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
1044                                         PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
1045                                         PAD_CTL_PUE_PULL |
1046                                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
1047                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
1048                                         PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
1049                                         PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
1050                                         PAD_CTL_PUE_PULL |
1051                                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
1052                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
1053                                         PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
1054                                         PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
1055                                         PAD_CTL_PUE_PULL |
1056                                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
1057                         break;
1058                 case 1:
1059                         status = 1;
1060                         break;
1061                 case 2:
1062                         status = 1;
1063                         break;
1064                 case 3:
1065                         status = 1;
1066                         break;
1067                 default:
1068                         status = 1;
1069                         break;
1070                 }
1071                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
1072         }
1073
1074         return status;
1075 }
1076
1077 int board_mmc_init(bd_t *bis)
1078 {
1079         if (!esdhc_gpio_init(bis))
1080                 return fsl_esdhc_mmc_init(gd->bd);
1081         else
1082                 return -1;
1083 }
1084 #endif
1085
1086 #if defined(CONFIG_MXC_KPD)
1087 int setup_mxc_kpd(void)
1088 {
1089         mxc_request_iomux(MX51_PIN_KEY_COL0, IOMUX_CONFIG_ALT0);
1090         mxc_request_iomux(MX51_PIN_KEY_COL1, IOMUX_CONFIG_ALT0);
1091         mxc_request_iomux(MX51_PIN_KEY_COL2, IOMUX_CONFIG_ALT0);
1092         mxc_request_iomux(MX51_PIN_KEY_COL3, IOMUX_CONFIG_ALT0);
1093         mxc_request_iomux(MX51_PIN_KEY_COL4, IOMUX_CONFIG_ALT0);
1094         mxc_request_iomux(MX51_PIN_KEY_COL5, IOMUX_CONFIG_ALT0);
1095         mxc_request_iomux(MX51_PIN_KEY_ROW0, IOMUX_CONFIG_ALT0);
1096         mxc_request_iomux(MX51_PIN_KEY_ROW1, IOMUX_CONFIG_ALT0);
1097         mxc_request_iomux(MX51_PIN_KEY_ROW2, IOMUX_CONFIG_ALT0);
1098         mxc_request_iomux(MX51_PIN_KEY_ROW3, IOMUX_CONFIG_ALT0);
1099
1100         return 0;
1101 }
1102 #endif