2 * (C) Copyright 2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/arch/crm_regs.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/iomux-mx53.h>
30 #include <asm/errno.h>
31 #include <asm/imx-common/boot_mode.h>
35 #include <fsl_esdhc.h>
36 #include <power/pmic.h>
41 DECLARE_GLOBAL_DATA_PTR;
45 /* dram_init must store complete ramsize in gd->ram_size */
46 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
51 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
52 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
54 static void setup_iomux_uart(void)
56 static const iomux_v3_cfg_t uart_pads[] = {
57 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
58 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
61 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
64 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
65 PAD_CTL_HYS | PAD_CTL_ODE)
67 static void setup_i2c(unsigned int port_number)
69 static const iomux_v3_cfg_t i2c1_pads[] = {
70 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
71 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
74 static const iomux_v3_cfg_t i2c2_pads[] = {
75 NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL),
76 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL),
79 switch (port_number) {
81 imx_iomux_v3_setup_multiple_pads(i2c1_pads,
82 ARRAY_SIZE(i2c1_pads));
85 imx_iomux_v3_setup_multiple_pads(i2c2_pads,
86 ARRAY_SIZE(i2c2_pads));
89 printf("Warning: Wrong I2C port number\n");
100 ret = pmic_init(I2C_PMIC);
104 p = pmic_get("FSL_PMIC");
108 /* Set VDDA to 1.25V */
109 pmic_reg_read(p, REG_SW_2, &val);
110 val &= ~SWX_OUT_MASK;
112 pmic_reg_write(p, REG_SW_2, val);
115 * Need increase VCC and VDDA to 1.3V
116 * according to MX53 IC TO2 datasheet.
118 if (is_soc_rev(CHIP_REV_2_0) == 0) {
119 /* Set VCC to 1.3V for TO2 */
120 pmic_reg_read(p, REG_SW_1, &val);
121 val &= ~SWX_OUT_MASK;
123 pmic_reg_write(p, REG_SW_1, val);
125 /* Set VDDA to 1.3V for TO2 */
126 pmic_reg_read(p, REG_SW_2, &val);
127 val &= ~SWX_OUT_MASK;
129 pmic_reg_write(p, REG_SW_2, val);
133 static void setup_iomux_fec(void)
135 static const iomux_v3_cfg_t fec_pads[] = {
136 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
137 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
138 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
139 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
140 PAD_CTL_HYS | PAD_CTL_PKE),
141 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
142 PAD_CTL_HYS | PAD_CTL_PKE),
143 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
144 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
145 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
146 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
147 PAD_CTL_HYS | PAD_CTL_PKE),
148 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
149 PAD_CTL_HYS | PAD_CTL_PKE),
150 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
151 PAD_CTL_HYS | PAD_CTL_PKE),
154 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
157 #ifdef CONFIG_FSL_ESDHC
158 struct fsl_esdhc_cfg esdhc_cfg[2] = {
159 {MMC_SDHC1_BASE_ADDR},
160 {MMC_SDHC3_BASE_ADDR},
163 int board_mmc_getcd(struct mmc *mmc)
165 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
168 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
169 gpio_direction_input(IMX_GPIO_NR(3, 11));
170 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
171 gpio_direction_input(IMX_GPIO_NR(3, 13));
173 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
174 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
176 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
181 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
183 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
186 int board_mmc_init(bd_t *bis)
188 static const iomux_v3_cfg_t sd1_pads[] = {
189 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
190 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
191 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
192 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
193 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
194 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
195 MX53_PAD_EIM_DA13__GPIO3_13,
198 static const iomux_v3_cfg_t sd2_pads[] = {
199 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
201 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
202 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
203 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
204 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
205 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
206 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
207 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
208 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
209 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
210 MX53_PAD_EIM_DA11__GPIO3_11,
216 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
217 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
219 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
222 imx_iomux_v3_setup_multiple_pads(sd1_pads,
223 ARRAY_SIZE(sd1_pads));
226 imx_iomux_v3_setup_multiple_pads(sd2_pads,
227 ARRAY_SIZE(sd2_pads));
230 printf("Warning: you configured more ESDHC controller"
231 "(%d) as supported by the board(2)\n",
232 CONFIG_SYS_FSL_ESDHC_NUM);
235 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
242 int board_early_init_f(void)
252 /* address of boot parameters */
253 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
258 #ifdef CONFIG_CMD_BMODE
259 static const struct boot_mode board_boot_modes[] = {
260 /* 4 bit bus width */
261 {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
262 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
267 int board_late_init(void)
272 #ifdef CONFIG_CMD_BMODE
273 add_board_boot_modes(board_boot_modes);
280 puts("Board: MX53EVK\n");