board/freescale/mx53evk/mx53evk.c

   1 /*
   2  * (C) Copyright 2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/mx5x_pins.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/iomux.h>
  30 #include <asm/errno.h>
  31 #include <asm/imx-common/boot_mode.h>
  32 #include <netdev.h>
  33 #include <i2c.h>
  34 #include <mmc.h>
  35 #include <fsl_esdhc.h>
  36 #include <pmic.h>
  37 #include <fsl_pmic.h>
  38 #include <asm/gpio.h>
  39 #include <mc13892.h>
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 int dram_init(void)
  44 {
  45         /* dram_init must store complete ramsize in gd->ram_size */
  46         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  47                                 PHYS_SDRAM_1_SIZE);
  48         return 0;
  49 }
  50
  51 static void setup_iomux_uart(void)
  52 {
  53         /* UART1 RXD */
  54         mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
  55         mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
  56                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  57                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  58                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  59                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  60         mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
  61
  62         /* UART1 TXD */
  63         mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
  64         mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
  65                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  66                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  67                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  68                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  69 }
  70
  71 static void setup_i2c(unsigned int port_number)
  72 {
  73         switch (port_number) {
  74         case 0:
  75                 /* i2c1 SDA */
  76                 mxc_request_iomux(MX53_PIN_CSI0_D8,
  77                                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
  78                 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
  79                                 INPUT_CTL_PATH0);
  80                 mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
  81                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
  82                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
  83                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  84                 /* i2c1 SCL */
  85                 mxc_request_iomux(MX53_PIN_CSI0_D9,
  86                                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
  87                 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
  88                                 INPUT_CTL_PATH0);
  89                 mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
  90                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
  91                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
  92                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  93                 break;
  94         case 1:
  95                 /* i2c2 SDA */
  96                 mxc_request_iomux(MX53_PIN_KEY_ROW3,
  97                                 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
  98                 mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
  99                                 INPUT_CTL_PATH0);
 100                 mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
 101                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 102                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
 103                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 104
 105                 /* i2c2 SCL */
 106                 mxc_request_iomux(MX53_PIN_KEY_COL3,
 107                                 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
 108                 mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
 109                                 INPUT_CTL_PATH0);
 110                 mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
 111                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 112                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
 113                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 114                 break;
 115         default:
 116                 printf("Warning: Wrong I2C port number\n");
 117                 break;
 118         }
 119 }
 120
 121 void power_init(void)
 122 {
 123         unsigned int val;
 124         struct pmic *p;
 125
 126         pmic_init();
 127         p = get_pmic();
 128
 129         /* Set VDDA to 1.25V */
 130         pmic_reg_read(p, REG_SW_2, &val);
 131         val &= ~SWX_OUT_MASK;
 132         val |= SWX_OUT_1_25;
 133         pmic_reg_write(p, REG_SW_2, val);
 134
 135         /*
 136          * Need increase VCC and VDDA to 1.3V
 137          * according to MX53 IC TO2 datasheet.
 138          */
 139         if (is_soc_rev(CHIP_REV_2_0) == 0) {
 140                 /* Set VCC to 1.3V for TO2 */
 141                 pmic_reg_read(p, REG_SW_1, &val);
 142                 val &= ~SWX_OUT_MASK;
 143                 val |= SWX_OUT_1_30;
 144                 pmic_reg_write(p, REG_SW_1, val);
 145
 146                 /* Set VDDA to 1.3V for TO2 */
 147                 pmic_reg_read(p, REG_SW_2, &val);
 148                 val &= ~SWX_OUT_MASK;
 149                 val |= SWX_OUT_1_30;
 150                 pmic_reg_write(p, REG_SW_2, val);
 151         }
 152 }
 153
 154 static void setup_iomux_fec(void)
 155 {
 156         /*FEC_MDIO*/
 157         mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
 158         mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
 159                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 160                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 161                                 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
 162         mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
 163
 164         /*FEC_MDC*/
 165         mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
 166         mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
 167
 168         /* FEC RXD1 */
 169         mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
 170         mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
 171                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 172
 173         /* FEC RXD0 */
 174         mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
 175         mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
 176                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 177
 178          /* FEC TXD1 */
 179         mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
 180         mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
 181
 182         /* FEC TXD0 */
 183         mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
 184         mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
 185
 186         /* FEC TX_EN */
 187         mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
 188         mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
 189
 190         /* FEC TX_CLK */
 191         mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
 192         mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
 193                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 194
 195         /* FEC RX_ER */
 196         mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
 197         mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
 198                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 199
 200         /* FEC CRS */
 201         mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
 202         mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
 203                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 204 }
 205
 206 #ifdef CONFIG_FSL_ESDHC
 207 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 208         {MMC_SDHC1_BASE_ADDR},
 209         {MMC_SDHC3_BASE_ADDR},
 210 };
 211
 212 int board_mmc_getcd(struct mmc *mmc)
 213 {
 214         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 215         int ret;
 216
 217         mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
 218         gpio_direction_input(IMX_GPIO_NR(3, 11));
 219         mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
 220         gpio_direction_input(IMX_GPIO_NR(3, 13));
 221
 222         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 223                 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
 224         else
 225                 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
 226
 227         return ret;
 228 }
 229
 230 int board_mmc_init(bd_t *bis)
 231 {
 232         u32 index;
 233         s32 status = 0;
 234
 235         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 236                 switch (index) {
 237                 case 0:
 238                         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 239                         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 240                         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 241                                                 IOMUX_CONFIG_ALT0);
 242                         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 243                                                 IOMUX_CONFIG_ALT0);
 244                         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 245                                                 IOMUX_CONFIG_ALT0);
 246                         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 247                                                 IOMUX_CONFIG_ALT0);
 248                         mxc_request_iomux(MX53_PIN_EIM_DA13,
 249                                                 IOMUX_CONFIG_ALT1);
 250
 251                         mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
 252                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 253                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 254                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 255                         mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
 256                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 257                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 258                                 PAD_CTL_DRV_HIGH);
 259                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
 260                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 261                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 262                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 263                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
 264                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 265                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 266                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 267                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
 268                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 269                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 270                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 271                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
 272                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 273                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 274                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 275                         break;
 276                 case 1:
 277                         mxc_request_iomux(MX53_PIN_ATA_RESET_B,
 278                                                 IOMUX_CONFIG_ALT2);
 279                         mxc_request_iomux(MX53_PIN_ATA_IORDY,
 280                                                 IOMUX_CONFIG_ALT2);
 281                         mxc_request_iomux(MX53_PIN_ATA_DATA8,
 282                                                 IOMUX_CONFIG_ALT4);
 283                         mxc_request_iomux(MX53_PIN_ATA_DATA9,
 284                                                 IOMUX_CONFIG_ALT4);
 285                         mxc_request_iomux(MX53_PIN_ATA_DATA10,
 286                                                 IOMUX_CONFIG_ALT4);
 287                         mxc_request_iomux(MX53_PIN_ATA_DATA11,
 288                                                 IOMUX_CONFIG_ALT4);
 289                         mxc_request_iomux(MX53_PIN_ATA_DATA0,
 290                                                 IOMUX_CONFIG_ALT4);
 291                         mxc_request_iomux(MX53_PIN_ATA_DATA1,
 292                                                 IOMUX_CONFIG_ALT4);
 293                         mxc_request_iomux(MX53_PIN_ATA_DATA2,
 294                                                 IOMUX_CONFIG_ALT4);
 295                         mxc_request_iomux(MX53_PIN_ATA_DATA3,
 296                                                 IOMUX_CONFIG_ALT4);
 297                         mxc_request_iomux(MX53_PIN_EIM_DA11,
 298                                                 IOMUX_CONFIG_ALT1);
 299
 300                         mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
 301                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 302                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 303                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 304                         mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
 305                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 306                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 307                                 PAD_CTL_DRV_HIGH);
 308                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
 309                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 310                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 311                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 312                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
 313                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 314                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 315                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 316                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
 317                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 318                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 319                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 320                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
 321                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 322                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 323                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 324                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
 325                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 326                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 327                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 328                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
 329                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 330                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 331                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 332                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
 333                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 334                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 335                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 336                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
 337                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 338                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 339                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 340
 341                         break;
 342                 default:
 343                         printf("Warning: you configured more ESDHC controller"
 344                                 "(%d) as supported by the board(2)\n",
 345                                 CONFIG_SYS_FSL_ESDHC_NUM);
 346                         return status;
 347                 }
 348                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 349         }
 350
 351         return status;
 352 }
 353 #endif
 354
 355 int board_early_init_f(void)
 356 {
 357         setup_iomux_uart();
 358         setup_iomux_fec();
 359
 360         return 0;
 361 }
 362
 363 int board_init(void)
 364 {
 365         /* address of boot parameters */
 366         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 367
 368         return 0;
 369 }
 370
 371 #ifdef CONFIG_CMD_BMODE
 372 static const struct boot_mode board_boot_modes[] = {
 373         /* 4 bit bus width */
 374         {"mmc0",        MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
 375         {"mmc1",        MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
 376         {NULL,          0},
 377 };
 378 #endif
 379
 380 int board_late_init(void)
 381 {
 382         setup_i2c(1);
 383         power_init();
 384
 385 #ifdef CONFIG_CMD_BMODE
 386         add_board_boot_modes(board_boot_modes);
 387 #endif
 388         return 0;
 389 }
 390
 391 int checkboard(void)
 392 {
 393         puts("Board: MX53EVK\n");
 394
 395         return 0;
 396 }