board/freescale/mx6sabresd/mx6sabresd.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/imx-common/mxc_i2c.h>
  16 #include <asm/imx-common/iomux-v3.h>
  17 #include <asm/imx-common/boot_mode.h>
  18 #include <asm/imx-common/video.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <miiphy.h>
  22 #include <netdev.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <i2c.h>
  28 #include <power/pmic.h>
  29 #include <power/pfuze100_pmic.h>
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  33         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  34         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  35
  36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  37         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  38         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  42
  43 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  44                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  45
  46 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  48         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  49
  50 #define I2C_PMIC        1
  51
  52 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  53
  54 #define DISP0_PWR_EN    IMX_GPIO_NR(1, 21)
  55
  56 int dram_init(void)
  57 {
  58         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  59
  60         return 0;
  61 }
  62
  63 iomux_v3_cfg_t const uart1_pads[] = {
  64         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  65         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  66 };
  67
  68 iomux_v3_cfg_t const enet_pads[] = {
  69         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  76         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  79         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  80         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         /* AR8031 PHY Reset */
  85         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL),
  86 };
  87
  88 static void setup_iomux_enet(void)
  89 {
  90         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  91
  92         /* Reset AR8031 PHY */
  93         gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
  94         udelay(500);
  95         gpio_set_value(IMX_GPIO_NR(1, 25), 1);
  96 }
  97
  98 iomux_v3_cfg_t const usdhc2_pads[] = {
  99         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_NANDF_D4__SD2_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106         MX6_PAD_NANDF_D5__SD2_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 107         MX6_PAD_NANDF_D6__SD2_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 108         MX6_PAD_NANDF_D7__SD2_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 109         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 110 };
 111
 112 iomux_v3_cfg_t const usdhc3_pads[] = {
 113         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123         MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 124 };
 125
 126 iomux_v3_cfg_t const usdhc4_pads[] = {
 127         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137 };
 138
 139 iomux_v3_cfg_t const ecspi1_pads[] = {
 140         MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 141         MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 142         MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 143         MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 144 };
 145
 146 static iomux_v3_cfg_t const rgb_pads[] = {
 147         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
 148         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 149         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 150         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
 151         MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
 152         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 153         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
 154         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 155         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
 156         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
 157         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 158         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 159         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 160         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 161         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 162         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 163         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 164         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 165         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
 166         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 167         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 168         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 169         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
 170         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 171         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 172         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
 173         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 174         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 175         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
 176         MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 177 };
 178
 179 static void enable_rgb(struct display_info_t const *dev)
 180 {
 181         imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
 182         gpio_direction_output(DISP0_PWR_EN, 1);
 183 }
 184
 185 static struct i2c_pads_info i2c_pad_info1 = {
 186         .scl = {
 187                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 188                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 189                 .gp = IMX_GPIO_NR(4, 12)
 190         },
 191         .sda = {
 192                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 193                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 194                 .gp = IMX_GPIO_NR(4, 13)
 195         }
 196 };
 197
 198 static void setup_spi(void)
 199 {
 200         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 201 }
 202
 203 iomux_v3_cfg_t const pcie_pads[] = {
 204         MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),        /* POWER */
 205         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),        /* RESET */
 206 };
 207
 208 static void setup_pcie(void)
 209 {
 210         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 211 }
 212
 213 iomux_v3_cfg_t const di0_pads[] = {
 214         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,        /* DISP0_CLK */
 215         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,               /* DISP0_HSYNC */
 216         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,               /* DISP0_VSYNC */
 217 };
 218
 219 static void setup_iomux_uart(void)
 220 {
 221         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 222 }
 223
 224 #ifdef CONFIG_FSL_ESDHC
 225 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 226         {USDHC2_BASE_ADDR},
 227         {USDHC3_BASE_ADDR},
 228         {USDHC4_BASE_ADDR},
 229 };
 230
 231 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 2)
 232 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 0)
 233
 234 int board_mmc_getcd(struct mmc *mmc)
 235 {
 236         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 237         int ret = 0;
 238
 239         switch (cfg->esdhc_base) {
 240         case USDHC2_BASE_ADDR:
 241                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 242                 break;
 243         case USDHC3_BASE_ADDR:
 244                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 245                 break;
 246         case USDHC4_BASE_ADDR:
 247                 ret = 1; /* eMMC/uSDHC4 is always present */
 248                 break;
 249         }
 250
 251         return ret;
 252 }
 253
 254 int board_mmc_init(bd_t *bis)
 255 {
 256         s32 status = 0;
 257         int i;
 258
 259         /*
 260          * According to the board_mmc_init() the following map is done:
 261          * (U-boot device node)    (Physical Port)
 262          * mmc0                    SD2
 263          * mmc1                    SD3
 264          * mmc2                    eMMC
 265          */
 266         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 267                 switch (i) {
 268                 case 0:
 269                         imx_iomux_v3_setup_multiple_pads(
 270                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 271                         gpio_direction_input(USDHC2_CD_GPIO);
 272                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 273                         break;
 274                 case 1:
 275                         imx_iomux_v3_setup_multiple_pads(
 276                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 277                         gpio_direction_input(USDHC3_CD_GPIO);
 278                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 279                         break;
 280                 case 2:
 281                         imx_iomux_v3_setup_multiple_pads(
 282                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 283                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 284                         break;
 285                 default:
 286                         printf("Warning: you configured more USDHC controllers"
 287                                "(%d) then supported by the board (%d)\n",
 288                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 289                         return status;
 290                 }
 291
 292                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 293         }
 294
 295         return status;
 296 }
 297 #endif
 298
 299 int mx6_rgmii_rework(struct phy_device *phydev)
 300 {
 301         unsigned short val;
 302
 303         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 304         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 305         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 306         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 307
 308         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 309         val &= 0xffe3;
 310         val |= 0x18;
 311         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 312
 313         /* introduce tx clock delay */
 314         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 315         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 316         val |= 0x0100;
 317         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 318
 319         return 0;
 320 }
 321
 322 int board_phy_config(struct phy_device *phydev)
 323 {
 324         mx6_rgmii_rework(phydev);
 325
 326         if (phydev->drv->config)
 327                 phydev->drv->config(phydev);
 328
 329         return 0;
 330 }
 331
 332 #if defined(CONFIG_VIDEO_IPUV3)
 333 static void disable_lvds(struct display_info_t const *dev)
 334 {
 335         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 336
 337         int reg = readl(&iomux->gpr[2]);
 338
 339         reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 340                  IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 341
 342         writel(reg, &iomux->gpr[2]);
 343 }
 344
 345 static void do_enable_hdmi(struct display_info_t const *dev)
 346 {
 347         disable_lvds(dev);
 348         imx_enable_hdmi_phy();
 349 }
 350
 351 static void enable_lvds(struct display_info_t const *dev)
 352 {
 353         struct iomuxc *iomux = (struct iomuxc *)
 354                                 IOMUXC_BASE_ADDR;
 355         u32 reg = readl(&iomux->gpr[2]);
 356         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
 357                IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
 358         writel(reg, &iomux->gpr[2]);
 359 }
 360
 361 struct display_info_t const displays[] = {{
 362         .bus    = -1,
 363         .addr   = 0,
 364         .pixfmt = IPU_PIX_FMT_RGB666,
 365         .detect = NULL,
 366         .enable = enable_lvds,
 367         .mode   = {
 368                 .name           = "Hannstar-XGA",
 369                 .refresh        = 60,
 370                 .xres           = 1024,
 371                 .yres           = 768,
 372                 .pixclock       = 15385,
 373                 .left_margin    = 220,
 374                 .right_margin   = 40,
 375                 .upper_margin   = 21,
 376                 .lower_margin   = 7,
 377                 .hsync_len      = 60,
 378                 .vsync_len      = 10,
 379                 .sync           = FB_SYNC_EXT,
 380                 .vmode          = FB_VMODE_NONINTERLACED
 381 } }, {
 382         .bus    = -1,
 383         .addr   = 0,
 384         .pixfmt = IPU_PIX_FMT_RGB24,
 385         .detect = detect_hdmi,
 386         .enable = do_enable_hdmi,
 387         .mode   = {
 388                 .name           = "HDMI",
 389                 .refresh        = 60,
 390                 .xres           = 1024,
 391                 .yres           = 768,
 392                 .pixclock       = 15385,
 393                 .left_margin    = 220,
 394                 .right_margin   = 40,
 395                 .upper_margin   = 21,
 396                 .lower_margin   = 7,
 397                 .hsync_len      = 60,
 398                 .vsync_len      = 10,
 399                 .sync           = FB_SYNC_EXT,
 400                 .vmode          = FB_VMODE_NONINTERLACED
 401 } }, {
 402         .bus    = 0,
 403         .addr   = 0,
 404         .pixfmt = IPU_PIX_FMT_RGB24,
 405         .detect = NULL,
 406         .enable = enable_rgb,
 407         .mode   = {
 408                 .name           = "SEIKO-WVGA",
 409                 .refresh        = 60,
 410                 .xres           = 800,
 411                 .yres           = 480,
 412                 .pixclock       = 29850,
 413                 .left_margin    = 89,
 414                 .right_margin   = 164,
 415                 .upper_margin   = 23,
 416                 .lower_margin   = 10,
 417                 .hsync_len      = 10,
 418                 .vsync_len      = 10,
 419                 .sync           = 0,
 420                 .vmode          = FB_VMODE_NONINTERLACED
 421 } } };
 422 size_t display_count = ARRAY_SIZE(displays);
 423
 424 static void setup_display(void)
 425 {
 426         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 427         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 428         int reg;
 429
 430         /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
 431         imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
 432
 433         enable_ipu_clock();
 434         imx_setup_hdmi();
 435
 436         /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 437         reg = readl(&mxc_ccm->CCGR3);
 438         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 439         writel(reg, &mxc_ccm->CCGR3);
 440
 441         /* set LDB0, LDB1 clk select to 011/011 */
 442         reg = readl(&mxc_ccm->cs2cdr);
 443         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 444                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 445         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 446               | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 447         writel(reg, &mxc_ccm->cs2cdr);
 448
 449         reg = readl(&mxc_ccm->cscmr2);
 450         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
 451         writel(reg, &mxc_ccm->cscmr2);
 452
 453         reg = readl(&mxc_ccm->chsccdr);
 454         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 455                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 456         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 457                 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 458         writel(reg, &mxc_ccm->chsccdr);
 459
 460         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 461              | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 462              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 463              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 464              | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 465              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 466              | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 467              | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 468              | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 469         writel(reg, &iomux->gpr[2]);
 470
 471         reg = readl(&iomux->gpr[3]);
 472         reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
 473                         | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 474             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 475                << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 476         writel(reg, &iomux->gpr[3]);
 477 }
 478 #endif /* CONFIG_VIDEO_IPUV3 */
 479
 480 /*
 481  * Do not overwrite the console
 482  * Use always serial for U-Boot console
 483  */
 484 int overwrite_console(void)
 485 {
 486         return 1;
 487 }
 488
 489 int board_eth_init(bd_t *bis)
 490 {
 491         setup_iomux_enet();
 492         setup_pcie();
 493
 494         return cpu_eth_init(bis);
 495 }
 496
 497 int board_early_init_f(void)
 498 {
 499         setup_iomux_uart();
 500 #if defined(CONFIG_VIDEO_IPUV3)
 501         setup_display();
 502 #endif
 503
 504         return 0;
 505 }
 506
 507 int board_init(void)
 508 {
 509         /* address of boot parameters */
 510         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 511
 512 #ifdef CONFIG_MXC_SPI
 513         setup_spi();
 514 #endif
 515         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 516
 517         return 0;
 518 }
 519
 520 static int pfuze_init(void)
 521 {
 522         struct pmic *p;
 523         int ret;
 524         unsigned int reg;
 525
 526         ret = power_pfuze100_init(I2C_PMIC);
 527         if (ret)
 528                 return ret;
 529
 530         p = pmic_get("PFUZE100");
 531         ret = pmic_probe(p);
 532         if (ret)
 533                 return ret;
 534
 535         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 536         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 537
 538         /* Increase VGEN3 from 2.5 to 2.8V */
 539         pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
 540         reg &= ~0xf;
 541         reg |= 0xa;
 542         pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
 543
 544         /* Increase VGEN5 from 2.8 to 3V */
 545         pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
 546         reg &= ~0xf;
 547         reg |= 0xc;
 548         pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
 549
 550         /* Set SW1AB stanby volage to 0.975V */
 551         pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 552         reg &= ~0x3f;
 553         reg |= 0x1b;
 554         pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 555
 556         /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 557         pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
 558         reg &= ~0xc0;
 559         reg |= 0x40;
 560         pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
 561
 562         /* Set SW1C standby voltage to 0.975V */
 563         pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
 564         reg &= ~0x3f;
 565         reg |= 0x1b;
 566         pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
 567
 568         /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
 569         pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
 570         reg &= ~0xc0;
 571         reg |= 0x40;
 572         pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 573
 574         return 0;
 575 }
 576
 577 #ifdef CONFIG_MXC_SPI
 578 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 579 {
 580         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 581 }
 582 #endif
 583
 584 #ifdef CONFIG_CMD_BMODE
 585 static const struct boot_mode board_boot_modes[] = {
 586         /* 4 bit bus width */
 587         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 588         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 589         /* 8 bit bus width */
 590         {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 591         {NULL,   0},
 592 };
 593 #endif
 594
 595 int board_late_init(void)
 596 {
 597 #ifdef CONFIG_CMD_BMODE
 598         add_board_boot_modes(board_boot_modes);
 599 #endif
 600         pfuze_init();
 601
 602         return 0;
 603 }
 604
 605 int checkboard(void)
 606 {
 607         puts("Board: MX6-SabreSD\n");
 608         return 0;
 609 }