board/freescale/mx6sabresd/mx6sabresd.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/imx-common/iomux-v3.h>
  16 #include <asm/imx-common/boot_mode.h>
  17 #include <mmc.h>
  18 #include <fsl_esdhc.h>
  19 #include <miiphy.h>
  20 #include <netdev.h>
  21 #include <asm/arch/mxc_hdmi.h>
  22 #include <asm/arch/crm_regs.h>
  23 #include <linux/fb.h>
  24 #include <ipu_pixfmt.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  30         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  31         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  32
  33 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  34         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  35         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  36
  37 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  38         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  39
  40 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  41                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  42
  43 int dram_init(void)
  44 {
  45         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  46
  47         return 0;
  48 }
  49
  50 iomux_v3_cfg_t const uart1_pads[] = {
  51         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  52         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  53 };
  54
  55 iomux_v3_cfg_t const enet_pads[] = {
  56         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  57         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  58         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  59         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  60         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  61         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  63         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  64         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  65         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  66         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71         /* AR8031 PHY Reset */
  72         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL),
  73 };
  74
  75 static void setup_iomux_enet(void)
  76 {
  77         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  78
  79         /* Reset AR8031 PHY */
  80         gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
  81         udelay(500);
  82         gpio_set_value(IMX_GPIO_NR(1, 25), 1);
  83 }
  84
  85 iomux_v3_cfg_t const usdhc2_pads[] = {
  86         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         MX6_PAD_NANDF_D4__SD2_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         MX6_PAD_NANDF_D5__SD2_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94         MX6_PAD_NANDF_D6__SD2_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95         MX6_PAD_NANDF_D7__SD2_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  97 };
  98
  99 iomux_v3_cfg_t const usdhc3_pads[] = {
 100         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 107         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 108         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 109         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 110         MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 111 };
 112
 113 iomux_v3_cfg_t const usdhc4_pads[] = {
 114         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124 };
 125
 126 iomux_v3_cfg_t const ecspi1_pads[] = {
 127         MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 128         MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 129         MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 130         MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 131 };
 132
 133 static void setup_spi(void)
 134 {
 135         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 136 }
 137
 138 static void setup_iomux_uart(void)
 139 {
 140         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 141 }
 142
 143 #ifdef CONFIG_FSL_ESDHC
 144 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 145         {USDHC2_BASE_ADDR},
 146         {USDHC3_BASE_ADDR},
 147         {USDHC4_BASE_ADDR},
 148 };
 149
 150 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 2)
 151 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 0)
 152
 153 int board_mmc_getcd(struct mmc *mmc)
 154 {
 155         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 156         int ret = 0;
 157
 158         switch (cfg->esdhc_base) {
 159         case USDHC2_BASE_ADDR:
 160                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 161                 break;
 162         case USDHC3_BASE_ADDR:
 163                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 164                 break;
 165         case USDHC4_BASE_ADDR:
 166                 ret = 1; /* eMMC/uSDHC4 is always present */
 167                 break;
 168         }
 169
 170         return ret;
 171 }
 172
 173 int board_mmc_init(bd_t *bis)
 174 {
 175         s32 status = 0;
 176         int i;
 177
 178         /*
 179          * According to the board_mmc_init() the following map is done:
 180          * (U-boot device node)    (Physical Port)
 181          * mmc0                    SD2
 182          * mmc1                    SD3
 183          * mmc2                    eMMC
 184          */
 185         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 186                 switch (i) {
 187                 case 0:
 188                         imx_iomux_v3_setup_multiple_pads(
 189                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 190                         gpio_direction_input(USDHC2_CD_GPIO);
 191                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 192                         break;
 193                 case 1:
 194                         imx_iomux_v3_setup_multiple_pads(
 195                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 196                         gpio_direction_input(USDHC3_CD_GPIO);
 197                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 198                         break;
 199                 case 2:
 200                         imx_iomux_v3_setup_multiple_pads(
 201                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 202                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 203                         break;
 204                 default:
 205                         printf("Warning: you configured more USDHC controllers"
 206                                "(%d) then supported by the board (%d)\n",
 207                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 208                         return status;
 209                 }
 210
 211                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 212         }
 213
 214         return status;
 215 }
 216 #endif
 217
 218 int mx6_rgmii_rework(struct phy_device *phydev)
 219 {
 220         unsigned short val;
 221
 222         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 223         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 224         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 225         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 226
 227         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 228         val &= 0xffe3;
 229         val |= 0x18;
 230         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 231
 232         /* introduce tx clock delay */
 233         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 234         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 235         val |= 0x0100;
 236         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 237
 238         return 0;
 239 }
 240
 241 int board_phy_config(struct phy_device *phydev)
 242 {
 243         mx6_rgmii_rework(phydev);
 244
 245         if (phydev->drv->config)
 246                 phydev->drv->config(phydev);
 247
 248         return 0;
 249 }
 250
 251 #if defined(CONFIG_VIDEO_IPUV3)
 252 struct display_info_t {
 253         int     bus;
 254         int     addr;
 255         int     pixfmt;
 256         int     (*detect)(struct display_info_t const *dev);
 257         void    (*enable)(struct display_info_t const *dev);
 258         struct  fb_videomode mode;
 259 };
 260
 261 static int detect_hdmi(struct display_info_t const *dev)
 262 {
 263         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 264         return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
 265 }
 266
 267
 268 static void disable_lvds(struct display_info_t const *dev)
 269 {
 270         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 271
 272         int reg = readl(&iomux->gpr[2]);
 273
 274         reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 275                  IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 276
 277         writel(reg, &iomux->gpr[2]);
 278 }
 279
 280 static void do_enable_hdmi(struct display_info_t const *dev)
 281 {
 282         disable_lvds(dev);
 283         imx_enable_hdmi_phy();
 284 }
 285
 286 static void enable_lvds(struct display_info_t const *dev)
 287 {
 288         struct iomuxc *iomux = (struct iomuxc *)
 289                                 IOMUXC_BASE_ADDR;
 290         u32 reg = readl(&iomux->gpr[2]);
 291         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 292                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT;
 293         writel(reg, &iomux->gpr[2]);
 294 }
 295
 296 static struct display_info_t const displays[] = {{
 297         .bus    = -1,
 298         .addr   = 0,
 299         .pixfmt = IPU_PIX_FMT_LVDS666,
 300         .detect = NULL,
 301         .enable = enable_lvds,
 302         .mode   = {
 303                 .name           = "Hannstar-XGA",
 304                 .refresh        = 60,
 305                 .xres           = 1024,
 306                 .yres           = 768,
 307                 .pixclock       = 15385,
 308                 .left_margin    = 220,
 309                 .right_margin   = 40,
 310                 .upper_margin   = 21,
 311                 .lower_margin   = 7,
 312                 .hsync_len      = 60,
 313                 .vsync_len      = 10,
 314                 .sync           = FB_SYNC_EXT,
 315                 .vmode          = FB_VMODE_NONINTERLACED
 316 } }, {
 317         .bus    = -1,
 318         .addr   = 0,
 319         .pixfmt = IPU_PIX_FMT_RGB24,
 320         .detect = detect_hdmi,
 321         .enable = do_enable_hdmi,
 322         .mode   = {
 323                 .name           = "HDMI",
 324                 .refresh        = 60,
 325                 .xres           = 1024,
 326                 .yres           = 768,
 327                 .pixclock       = 15385,
 328                 .left_margin    = 220,
 329                 .right_margin   = 40,
 330                 .upper_margin   = 21,
 331                 .lower_margin   = 7,
 332                 .hsync_len      = 60,
 333                 .vsync_len      = 10,
 334                 .sync           = FB_SYNC_EXT,
 335                 .vmode          = FB_VMODE_NONINTERLACED
 336 } } };
 337
 338 int board_video_skip(void)
 339 {
 340         int i;
 341         int ret;
 342         char const *panel = getenv("panel");
 343         if (!panel) {
 344                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 345                         struct display_info_t const *dev = displays+i;
 346                         if (dev->detect && dev->detect(dev)) {
 347                                 panel = dev->mode.name;
 348                                 printf("auto-detected panel %s\n", panel);
 349                                 break;
 350                         }
 351                 }
 352                 if (!panel) {
 353                         panel = displays[0].mode.name;
 354                         printf("No panel detected: default to %s\n", panel);
 355                         i = 0;
 356                 }
 357         } else {
 358                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 359                         if (!strcmp(panel, displays[i].mode.name))
 360                                 break;
 361                 }
 362         }
 363         if (i < ARRAY_SIZE(displays)) {
 364                 ret = ipuv3_fb_init(&displays[i].mode, 0,
 365                                     displays[i].pixfmt);
 366                 if (!ret) {
 367                         displays[i].enable(displays+i);
 368                         printf("Display: %s (%ux%u)\n",
 369                                displays[i].mode.name,
 370                                displays[i].mode.xres,
 371                                displays[i].mode.yres);
 372                 } else
 373                         printf("LCD %s cannot be configured: %d\n",
 374                                displays[i].mode.name, ret);
 375         } else {
 376                 printf("unsupported panel %s\n", panel);
 377                 return -EINVAL;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static void setup_display(void)
 384 {
 385         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 386         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 387         int reg;
 388
 389         enable_ipu_clock();
 390         imx_setup_hdmi();
 391
 392         /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 393         reg = __raw_readl(&mxc_ccm->CCGR3);
 394         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 395         writel(reg, &mxc_ccm->CCGR3);
 396
 397         /* set LDB0, LDB1 clk select to 011/011 */
 398         reg = readl(&mxc_ccm->cs2cdr);
 399         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 400                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 401         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 402               | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 403         writel(reg, &mxc_ccm->cs2cdr);
 404
 405         reg = readl(&mxc_ccm->cscmr2);
 406         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
 407         writel(reg, &mxc_ccm->cscmr2);
 408
 409         reg = readl(&mxc_ccm->chsccdr);
 410         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 411                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 412         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 413                 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 414         writel(reg, &mxc_ccm->chsccdr);
 415
 416         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 417              | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 418              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 419              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 420              | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 421              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 422              | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 423              | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 424              | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 425         writel(reg, &iomux->gpr[2]);
 426
 427         reg = readl(&iomux->gpr[3]);
 428         reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
 429                         | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 430             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 431                << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 432         writel(reg, &iomux->gpr[3]);
 433 }
 434 #endif /* CONFIG_VIDEO_IPUV3 */
 435
 436 /*
 437  * Do not overwrite the console
 438  * Use always serial for U-Boot console
 439  */
 440 int overwrite_console(void)
 441 {
 442         return 1;
 443 }
 444
 445 int board_eth_init(bd_t *bis)
 446 {
 447         int ret;
 448
 449         setup_iomux_enet();
 450
 451         ret = cpu_eth_init(bis);
 452         if (ret)
 453                 printf("FEC MXC: %s:failed\n", __func__);
 454
 455         return ret;
 456 }
 457
 458 int board_early_init_f(void)
 459 {
 460         setup_iomux_uart();
 461 #if defined(CONFIG_VIDEO_IPUV3)
 462         setup_display();
 463 #endif
 464
 465         return 0;
 466 }
 467
 468 int board_init(void)
 469 {
 470         /* address of boot parameters */
 471         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 472
 473 #ifdef CONFIG_MXC_SPI
 474         setup_spi();
 475 #endif
 476
 477         return 0;
 478 }
 479
 480 #ifdef CONFIG_CMD_BMODE
 481 static const struct boot_mode board_boot_modes[] = {
 482         /* 4 bit bus width */
 483         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 484         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 485         /* 8 bit bus width */
 486         {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 487         {NULL,   0},
 488 };
 489 #endif
 490
 491 int board_late_init(void)
 492 {
 493 #ifdef CONFIG_CMD_BMODE
 494         add_board_boot_modes(board_boot_modes);
 495 #endif
 496
 497         return 0;
 498 }
 499
 500 int checkboard(void)
 501 {
 502         puts("Board: MX6-SabreSD\n");
 503         return 0;
 504 }