board/freescale/p1010rdb/p1010rdb.c

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/processor.h>
   9 #include <asm/mmu.h>
  10 #include <asm/cache.h>
  11 #include <asm/immap_85xx.h>
  12 #include <asm/io.h>
  13 #include <miiphy.h>
  14 #include <libfdt.h>
  15 #include <fdt_support.h>
  16 #include <fsl_mdio.h>
  17 #include <tsec.h>
  18 #include <mmc.h>
  19 #include <netdev.h>
  20 #include <pci.h>
  21 #include <asm/fsl_serdes.h>
  22 #include <fsl_ifc.h>
  23 #include <asm/fsl_pci.h>
  24 #include <hwconfig.h>
  25 #include <i2c.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define GPIO4_PCIE_RESET_SET            0x08000000
  30 #define MUX_CPLD_CAN_UART               0x00
  31 #define MUX_CPLD_TDM                    0x01
  32 #define MUX_CPLD_SPICS0_FLASH           0x00
  33 #define MUX_CPLD_SPICS0_SLIC            0x02
  34 #define PMUXCR1_IFC_MASK       0x00ffff00
  35 #define PMUXCR1_SDHC_MASK      0x00fff000
  36 #define PMUXCR1_SDHC_ENABLE    0x00555000
  37
  38 enum {
  39         MUX_TYPE_IFC,
  40         MUX_TYPE_SDHC,
  41         MUX_TYPE_SPIFLASH,
  42         MUX_TYPE_TDM,
  43         MUX_TYPE_CAN,
  44         MUX_TYPE_CS0_NOR,
  45         MUX_TYPE_CS0_NAND,
  46 };
  47
  48 enum {
  49         I2C_READ_BANK,
  50         I2C_READ_PCB_VER,
  51 };
  52
  53 static uint sd_ifc_mux;
  54
  55 struct cpld_data {
  56         u8 cpld_ver; /* cpld revision */
  57 #if defined(CONFIG_P1010RDB_PA)
  58         u8 pcba_ver; /* pcb revision number */
  59         u8 twindie_ddr3;
  60         u8 res1[6];
  61         u8 bank_sel; /* NOR Flash bank */
  62         u8 res2[5];
  63         u8 usb2_sel;
  64         u8 res3[1];
  65         u8 porsw_sel;
  66         u8 tdm_can_sel;
  67         u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
  68         u8 por0; /* POR Options */
  69         u8 por1; /* POR Options */
  70         u8 por2; /* POR Options */
  71         u8 por3; /* POR Options */
  72 #elif defined(CONFIG_P1010RDB_PB)
  73         u8 rom_loc;
  74 #endif
  75 };
  76
  77 int board_early_init_f(void)
  78 {
  79         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  80         struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
  81
  82         /* Clock configuration to access CPLD using IFC(GPCM) */
  83         setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
  84         /*
  85         * Reset PCIe slots via GPIO4
  86         */
  87         setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
  88         setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
  89
  90         return 0;
  91 }
  92
  93 int board_early_init_r(void)
  94 {
  95         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  96         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  97
  98         /*
  99          * Remap Boot flash region to caching-inhibited
 100          * so that flash can be erased properly.
 101          */
 102
 103         /* Flush d-cache and invalidate i-cache of any FLASH data */
 104         flush_dcache();
 105         invalidate_icache();
 106
 107         /* invalidate existing TLB entry for flash */
 108         disable_tlb(flash_esel);
 109
 110         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 111                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 112                         0, flash_esel, BOOKE_PAGESZ_16M, 1);
 113
 114         set_tlb(1, flashbase + 0x1000000,
 115                         CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
 116                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 117                         0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
 118         return 0;
 119 }
 120
 121 #ifdef CONFIG_PCI
 122 void pci_init_board(void)
 123 {
 124         fsl_pcie_init_board(0);
 125 }
 126 #endif /* ifdef CONFIG_PCI */
 127
 128 int config_board_mux(int ctrl_type)
 129 {
 130         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 131         u8 tmp;
 132
 133 #if defined(CONFIG_P1010RDB_PA)
 134         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 135
 136         switch (ctrl_type) {
 137         case MUX_TYPE_IFC:
 138                 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 139                 tmp = 0xf0;
 140                 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
 141                 tmp = 0x01;
 142                 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
 143                 sd_ifc_mux = MUX_TYPE_IFC;
 144                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 145                 break;
 146         case MUX_TYPE_SDHC:
 147                 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 148                 tmp = 0xf0;
 149                 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
 150                 tmp = 0x05;
 151                 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
 152                 sd_ifc_mux = MUX_TYPE_SDHC;
 153                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 154                                 PMUXCR1_SDHC_ENABLE);
 155                 break;
 156         case MUX_TYPE_SPIFLASH:
 157                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
 158                 break;
 159         case MUX_TYPE_TDM:
 160                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
 161                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
 162                 break;
 163         case MUX_TYPE_CAN:
 164                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
 165                 break;
 166         default:
 167                 break;
 168         }
 169 #elif defined(CONFIG_P1010RDB_PB)
 170         uint orig_bus = i2c_get_bus_num();
 171         i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 172
 173         switch (ctrl_type) {
 174         case MUX_TYPE_IFC:
 175                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 176                 clrbits_8(&tmp, 0x04);
 177                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 178                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 179                 clrbits_8(&tmp, 0x04);
 180                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 181                 sd_ifc_mux = MUX_TYPE_IFC;
 182                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 183                 break;
 184         case MUX_TYPE_SDHC:
 185                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 186                 setbits_8(&tmp, 0x04);
 187                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 188                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 189                 clrbits_8(&tmp, 0x04);
 190                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 191                 sd_ifc_mux = MUX_TYPE_SDHC;
 192                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 193                                 PMUXCR1_SDHC_ENABLE);
 194                 break;
 195         case MUX_TYPE_SPIFLASH:
 196                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 197                 clrbits_8(&tmp, 0x80);
 198                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 199                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 200                 clrbits_8(&tmp, 0x80);
 201                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 202                 break;
 203         case MUX_TYPE_TDM:
 204                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 205                 setbits_8(&tmp, 0x82);
 206                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 207                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 208                 clrbits_8(&tmp, 0x82);
 209                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 210                 break;
 211         case MUX_TYPE_CAN:
 212                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 213                 clrbits_8(&tmp, 0x02);
 214                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 215                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 216                 clrbits_8(&tmp, 0x02);
 217                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 218                 break;
 219         case MUX_TYPE_CS0_NOR:
 220                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 221                 clrbits_8(&tmp, 0x08);
 222                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 223                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 224                 clrbits_8(&tmp, 0x08);
 225                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 226                 break;
 227         case MUX_TYPE_CS0_NAND:
 228                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 229                 setbits_8(&tmp, 0x08);
 230                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 231                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 232                 clrbits_8(&tmp, 0x08);
 233                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 234                 break;
 235         default:
 236                 break;
 237         }
 238         i2c_set_bus_num(orig_bus);
 239 #endif
 240         return 0;
 241 }
 242
 243 #ifdef CONFIG_P1010RDB_PB
 244 int i2c_pca9557_read(int type)
 245 {
 246         u8 val;
 247
 248         i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 249         i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
 250
 251         switch (type) {
 252         case I2C_READ_BANK:
 253                 val = (val & 0x10) >> 4;
 254                 break;
 255         case I2C_READ_PCB_VER:
 256                 val = ((val & 0x60) >> 5) + 1;
 257                 break;
 258         default:
 259                 break;
 260         }
 261
 262         return val;
 263 }
 264 #endif
 265
 266 int checkboard(void)
 267 {
 268         struct cpu_type *cpu;
 269         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 270         u8 val;
 271
 272         cpu = gd->arch.cpu;
 273 #if defined(CONFIG_P1010RDB_PA)
 274         printf("Board: %sRDB-PA, ", cpu->name);
 275 #elif defined(CONFIG_P1010RDB_PB)
 276         printf("Board: %sRDB-PB, ", cpu->name);
 277         i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 278         i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
 279         val = 0x0;  /* no polarity inversion */
 280         i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
 281 #endif
 282
 283 #ifdef CONFIG_SDCARD
 284         /* switch to IFC to read info from CPLD */
 285         config_board_mux(MUX_TYPE_IFC);
 286 #endif
 287
 288 #if defined(CONFIG_P1010RDB_PA)
 289         val = (in_8(&cpld_data->pcba_ver) & 0xf);
 290         printf("PCB: v%x.0\n", val);
 291 #elif defined(CONFIG_P1010RDB_PB)
 292         val = in_8(&cpld_data->cpld_ver);
 293         printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
 294         printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
 295         val = in_8(&cpld_data->rom_loc) & 0xf;
 296         puts("Boot from: ");
 297         switch (val) {
 298         case 0xf:
 299                 config_board_mux(MUX_TYPE_CS0_NOR);
 300                 printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
 301                 break;
 302         case 0xe:
 303                 puts("SDHC\n");
 304                 val = 0x60; /* set pca9557 pin input/output */
 305                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
 306                 break;
 307         case 0x5:
 308                 config_board_mux(MUX_TYPE_IFC);
 309                 config_board_mux(MUX_TYPE_CS0_NAND);
 310                 puts("NAND\n");
 311                 break;
 312         case 0x6:
 313                 config_board_mux(MUX_TYPE_IFC);
 314                 puts("SPI\n");
 315                 break;
 316         default:
 317                 puts("unknown\n");
 318                 break;
 319         }
 320 #endif
 321         return 0;
 322 }
 323
 324 #ifdef CONFIG_TSEC_ENET
 325 int board_eth_init(bd_t *bis)
 326 {
 327         struct fsl_pq_mdio_info mdio_info;
 328         struct tsec_info_struct tsec_info[4];
 329         struct cpu_type *cpu;
 330         int num = 0;
 331
 332         cpu = gd->arch.cpu;
 333
 334 #ifdef CONFIG_TSEC1
 335         SET_STD_TSEC_INFO(tsec_info[num], 1);
 336         num++;
 337 #endif
 338 #ifdef CONFIG_TSEC2
 339         SET_STD_TSEC_INFO(tsec_info[num], 2);
 340         num++;
 341 #endif
 342 #ifdef CONFIG_TSEC3
 343         /* P1014 and it's derivatives do not support eTSEC3 */
 344         if (cpu->soc_ver != SVR_P1014) {
 345                 SET_STD_TSEC_INFO(tsec_info[num], 3);
 346                 num++;
 347         }
 348 #endif
 349         if (!num) {
 350                 printf("No TSECs initialized\n");
 351                 return 0;
 352         }
 353
 354         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 355         mdio_info.name = DEFAULT_MII_NAME;
 356
 357         fsl_pq_mdio_init(bis, &mdio_info);
 358
 359         tsec_eth_init(bis, tsec_info, num);
 360
 361         return pci_eth_init(bis);
 362 }
 363 #endif
 364
 365 #if defined(CONFIG_OF_BOARD_SETUP)
 366 void fdt_del_flexcan(void *blob)
 367 {
 368         int nodeoff = 0;
 369
 370         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 371                                 "fsl,p1010-flexcan")) >= 0) {
 372                 fdt_del_node(blob, nodeoff);
 373         }
 374 }
 375
 376 void fdt_del_spi_flash(void *blob)
 377 {
 378         int nodeoff = 0;
 379
 380         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 381                                 "spansion,s25sl12801")) >= 0) {
 382                 fdt_del_node(blob, nodeoff);
 383         }
 384 }
 385
 386 void fdt_del_spi_slic(void *blob)
 387 {
 388         int nodeoff = 0;
 389
 390         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 391                                 "zarlink,le88266")) >= 0) {
 392                 fdt_del_node(blob, nodeoff);
 393         }
 394 }
 395
 396 void fdt_del_tdm(void *blob)
 397 {
 398         int nodeoff = 0;
 399
 400         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 401                                 "fsl,starlite-tdm")) >= 0) {
 402                 fdt_del_node(blob, nodeoff);
 403         }
 404 }
 405
 406 void fdt_del_sdhc(void *blob)
 407 {
 408         int nodeoff = 0;
 409
 410         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 411                         "fsl,esdhc")) >= 0) {
 412                 fdt_del_node(blob, nodeoff);
 413         }
 414 }
 415
 416 void fdt_del_ifc(void *blob)
 417 {
 418         int nodeoff = 0;
 419
 420         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 421                                 "fsl,ifc")) >= 0) {
 422                 fdt_del_node(blob, nodeoff);
 423         }
 424 }
 425
 426 void fdt_disable_uart1(void *blob)
 427 {
 428         int nodeoff;
 429
 430         nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
 431                                         CONFIG_SYS_NS16550_COM2);
 432
 433         if (nodeoff > 0) {
 434                 fdt_status_disabled(blob, nodeoff);
 435         } else {
 436                 printf("WARNING unable to set status for fsl,ns16550 "
 437                         "uart1: %s\n", fdt_strerror(nodeoff));
 438         }
 439 }
 440
 441 void ft_board_setup(void *blob, bd_t *bd)
 442 {
 443         phys_addr_t base;
 444         phys_size_t size;
 445         struct cpu_type *cpu;
 446
 447         cpu = gd->arch.cpu;
 448
 449         ft_cpu_setup(blob, bd);
 450
 451         base = getenv_bootm_low();
 452         size = getenv_bootm_size();
 453
 454 #if defined(CONFIG_PCI)
 455         FT_FSL_PCI_SETUP;
 456 #endif
 457
 458         fdt_fixup_memory(blob, (u64)base, (u64)size);
 459
 460 #if defined(CONFIG_HAS_FSL_DR_USB)
 461         fdt_fixup_dr_usb(blob, bd);
 462 #endif
 463
 464        /* P1014 and it's derivatives don't support CAN and eTSEC3 */
 465         if (cpu->soc_ver == SVR_P1014) {
 466                 fdt_del_flexcan(blob);
 467                 fdt_del_node_and_alias(blob, "ethernet2");
 468         }
 469
 470         /* Delete IFC node as IFC pins are multiplexing with SDHC */
 471         if (sd_ifc_mux != MUX_TYPE_IFC)
 472                 fdt_del_ifc(blob);
 473         else
 474                 fdt_del_sdhc(blob);
 475
 476         if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 477                 fdt_del_tdm(blob);
 478                 fdt_del_spi_slic(blob);
 479         } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 480                 fdt_del_flexcan(blob);
 481                 fdt_del_spi_flash(blob);
 482                 fdt_disable_uart1(blob);
 483         } else {
 484                 /*
 485                  * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
 486                  * explicitly, defaultly spi_cs_sel to spi-flash instead of
 487                  * to tdm/slic.
 488                  */
 489                 fdt_del_tdm(blob);
 490                 fdt_del_flexcan(blob);
 491                 fdt_disable_uart1(blob);
 492         }
 493 }
 494 #endif
 495
 496 #ifdef CONFIG_SDCARD
 497 int board_mmc_init(bd_t *bis)
 498 {
 499         config_board_mux(MUX_TYPE_SDHC);
 500                 return -1;
 501 }
 502 #else
 503 void board_reset(void)
 504 {
 505         /* mux to IFC to enable CPLD for reset */
 506         if (sd_ifc_mux != MUX_TYPE_IFC)
 507                 config_board_mux(MUX_TYPE_IFC);
 508 }
 509 #endif
 510
 511
 512 int misc_init_r(void)
 513 {
 514         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 515
 516         if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 517                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
 518                                 MPC85xx_PMUXCR_CAN1_UART |
 519                                 MPC85xx_PMUXCR_CAN2_TDM |
 520                                 MPC85xx_PMUXCR_CAN2_UART);
 521                 config_board_mux(MUX_TYPE_CAN);
 522         } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 523                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
 524                                 MPC85xx_PMUXCR_CAN1_UART);
 525                 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
 526                                 MPC85xx_PMUXCR_CAN1_TDM);
 527                 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
 528                 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
 529                 config_board_mux(MUX_TYPE_TDM);
 530         } else {
 531                 /* defaultly spi_cs_sel to flash */
 532                 config_board_mux(MUX_TYPE_SPIFLASH);
 533         }
 534
 535         if (hwconfig("esdhc"))
 536                 config_board_mux(MUX_TYPE_SDHC);
 537         else if (hwconfig("ifc"))
 538                 config_board_mux(MUX_TYPE_IFC);
 539
 540 #ifdef CONFIG_P1010RDB_PB
 541         setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
 542 #endif
 543         return 0;
 544 }
 545
 546 static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 547                                 char * const argv[])
 548 {
 549         if (argc < 2)
 550                 return CMD_RET_USAGE;
 551         if (strcmp(argv[1], "ifc") == 0)
 552                 config_board_mux(MUX_TYPE_IFC);
 553         else if (strcmp(argv[1], "sdhc") == 0)
 554                 config_board_mux(MUX_TYPE_SDHC);
 555         else
 556                 return CMD_RET_USAGE;
 557         return 0;
 558 }
 559
 560 U_BOOT_CMD(
 561         mux, 2, 0, pin_mux_cmd,
 562         "configure multiplexing pin for IFC/SDHC bus in runtime",
 563         "bus_type (e.g. mux sdhc)"
 564 );