board/freescale/p2020ds/p2020ds.c

   1 /*
   2  * Copyright 2007-2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <miiphy.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36 #include <tsec.h>
  37 #include <asm/fsl_law.h>
  38 #include <asm/mp.h>
  39 #include <netdev.h>
  40
  41 #include "../common/pixis.h"
  42 #include "../common/sgmii_riser.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 phys_size_t fixed_sdram(void);
  47
  48 int checkboard(void)
  49 {
  50         u8 sw7;
  51         u8 *pixis_base = (u8 *)PIXIS_BASE;
  52
  53         puts("Board: P2020DS ");
  54 #ifdef CONFIG_PHYS_64BIT
  55         puts("(36-bit addrmap) ");
  56 #endif
  57
  58         printf("Sys ID: 0x%02x, "
  59                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  60                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  61                 in_8(pixis_base + PIXIS_PVER));
  62
  63         sw7 = in_8(pixis_base + PIXIS_SW(7));
  64         switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
  65                 case 0:
  66                 case 1:
  67                         printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
  68                         break;
  69                 case 2:
  70                 case 3:
  71                         puts ("Promjet\n");
  72                         break;
  73         }
  74
  75         return 0;
  76 }
  77
  78 phys_size_t initdram(int board_type)
  79 {
  80         phys_size_t dram_size = 0;
  81
  82         puts("Initializing....");
  83
  84 #ifdef CONFIG_SPD_EEPROM
  85         dram_size = fsl_ddr_sdram();
  86 #else
  87         dram_size = fixed_sdram();
  88
  89         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  90                          dram_size,
  91                          LAW_TRGT_IF_DDR) < 0) {
  92                 printf("ERROR setting Local Access Windows for DDR\n");
  93                 return 0;
  94         };
  95 #endif
  96         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  97         dram_size *= 0x100000;
  98
  99         puts("    DDR: ");
 100         return dram_size;
 101 }
 102
 103 #if !defined(CONFIG_SPD_EEPROM)
 104 /*
 105  * Fixed sdram init -- doesn't use serial presence detect.
 106  */
 107
 108 phys_size_t fixed_sdram(void)
 109 {
 110         volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
 111         uint d_init;
 112
 113         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 114         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 115         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 116         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 117         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 118         ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
 119         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 120         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 121         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 122         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 123         ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
 124         ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
 125         ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
 126         ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
 127         ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
 128
 129         if (!strcmp("performance", getenv("perf_mode"))) {
 130                 /* Performance Mode Values */
 131
 132                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
 133                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
 134                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
 135                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
 136                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
 137
 138                 asm("sync;isync");
 139
 140                 udelay(500);
 141
 142                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
 143         } else {
 144                 /* Stable Mode Values */
 145
 146                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
 147                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 148                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
 149                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 150                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 151
 152                 /* ECC will be assumed in stable mode */
 153                 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 154                 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 155                 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 156
 157                 asm("sync;isync");
 158
 159                 udelay(500);
 160
 161                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 162         }
 163
 164 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 165         d_init = 1;
 166         debug("DDR - 1st controller: memory initializing\n");
 167         /*
 168          * Poll until memory is initialized.
 169          * 512 Meg at 400 might hit this 200 times or so.
 170          */
 171         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 172                 udelay(1000);
 173         debug("DDR: memory initialized\n\n");
 174         asm("sync; isync");
 175         udelay(500);
 176 #endif
 177
 178         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 179 }
 180
 181 #endif
 182
 183 #ifdef CONFIG_PCIE1
 184 static struct pci_controller pcie1_hose;
 185 #endif
 186
 187 #ifdef CONFIG_PCIE2
 188 static struct pci_controller pcie2_hose;
 189 #endif
 190
 191 #ifdef CONFIG_PCIE3
 192 static struct pci_controller pcie3_hose;
 193 #endif
 194
 195 int first_free_busno = 0;
 196
 197 #ifdef CONFIG_PCI
 198 void pci_init_board(void)
 199 {
 200         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 201         uint devdisr = gur->devdisr;
 202         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 203         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 204
 205         volatile ccsr_fsl_pci_t *pci;
 206         struct pci_controller *hose;
 207         int pcie_ep, pcie_configured;
 208         struct pci_region *r;
 209 /*              u32 temp32; */
 210
 211         debug("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 212                         devdisr, io_sel, host_agent);
 213
 214         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 215                 printf("    eTSEC2 is in sgmii mode.\n");
 216         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 217                 printf("    eTSEC3 is in sgmii mode.\n");
 218
 219 #ifdef CONFIG_PCIE2
 220         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 221         hose = &pcie2_hose;
 222         pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
 223         pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
 224         r = hose->regions;
 225
 226         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
 227                 printf("\n    PCIE2 connected to ULI as %s (base addr %x)",
 228                                 pcie_ep ? "End Point" : "Root Complex",
 229                                 (uint)pci);
 230                 if (pci->pme_msg_det) {
 231                         pci->pme_msg_det = 0xffffffff;
 232                         debug(" with errors.  Clearing.  Now 0x%08x",
 233                                 pci->pme_msg_det);
 234                 }
 235                 printf("\n");
 236
 237                 /* outbound memory */
 238                 pci_set_region(r++,
 239                                 CONFIG_SYS_PCIE2_MEM_BUS,
 240                                 CONFIG_SYS_PCIE2_MEM_PHYS,
 241                                 CONFIG_SYS_PCIE2_MEM_SIZE,
 242                                 PCI_REGION_MEM);
 243
 244                 /* outbound io */
 245                 pci_set_region(r++,
 246                                 CONFIG_SYS_PCIE2_IO_BUS,
 247                                 CONFIG_SYS_PCIE2_IO_PHYS,
 248                                 CONFIG_SYS_PCIE2_IO_SIZE,
 249                                 PCI_REGION_IO);
 250
 251                 hose->region_count = r - hose->regions;
 252                 hose->first_busno = first_free_busno;
 253
 254                 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 255                 first_free_busno = hose->last_busno+1;
 256                 printf("    PCIE2 on bus %02x - %02x\n",
 257                         hose->first_busno, hose->last_busno);
 258
 259                 /*
 260                  * The workaround doesn't work on p2020 because the location
 261                  * we try and read isn't valid on p2020, fix this later
 262                  */
 263 #if 0
 264                 /*
 265                  * Activate ULI1575 legacy chip by performing a fake
 266                  * memory access.  Needed to make ULI RTC work.
 267                  * Device 1d has the first on-board memory BAR.
 268                  */
 269
 270                 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
 271                                 PCI_BASE_ADDRESS_1, &temp32);
 272                 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
 273                         void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
 274                                                         temp32, 4, 0);
 275                         debug(" uli1575 read to %p\n", p);
 276                         in_be32(p);
 277                 }
 278 #endif
 279         } else {
 280                 printf("    PCIE2: disabled\n");
 281         }
 282 #else
 283         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 284 #endif
 285
 286 #ifdef CONFIG_PCIE3
 287         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 288         hose = &pcie3_hose;
 289         pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
 290         pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
 291         r = hose->regions;
 292
 293         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
 294                 printf("\n    PCIE3 connected to Slot 1 as %s (base addr %x)",
 295                                 pcie_ep ? "End Point" : "Root Complex",
 296                                 (uint)pci);
 297                 if (pci->pme_msg_det) {
 298                         pci->pme_msg_det = 0xffffffff;
 299                         debug(" with errors.  Clearing.  Now 0x%08x",
 300                                 pci->pme_msg_det);
 301                 }
 302                 printf("\n");
 303
 304                 /* outbound memory */
 305                 pci_set_region(r++,
 306                                 CONFIG_SYS_PCIE3_MEM_BUS,
 307                                 CONFIG_SYS_PCIE3_MEM_PHYS,
 308                                 CONFIG_SYS_PCIE3_MEM_SIZE,
 309                                 PCI_REGION_MEM);
 310
 311                 /* outbound io */
 312                 pci_set_region(r++,
 313                                 CONFIG_SYS_PCIE3_IO_BUS,
 314                                 CONFIG_SYS_PCIE3_IO_PHYS,
 315                                 CONFIG_SYS_PCIE3_IO_SIZE,
 316                                 PCI_REGION_IO);
 317
 318                 hose->region_count = r - hose->regions;
 319                 hose->first_busno = first_free_busno;
 320
 321                 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 322
 323                 first_free_busno = hose->last_busno+1;
 324                 printf("    PCIE3 on bus %02x - %02x\n",
 325                                 hose->first_busno, hose->last_busno);
 326
 327         } else {
 328                 printf("    PCIE3: disabled\n");
 329         }
 330 #else
 331         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 332 #endif
 333
 334 #ifdef CONFIG_PCIE1
 335         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 336         hose = &pcie1_hose;
 337         pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
 338         pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
 339         r = hose->regions;
 340
 341         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
 342                 printf("\n    PCIE1 connected to Slot 2 as %s (base addr %x)",
 343                                 pcie_ep ? "End Point" : "Root Complex",
 344                                 (uint)pci);
 345                 if (pci->pme_msg_det) {
 346                         pci->pme_msg_det = 0xffffffff;
 347                         debug(" with errors.  Clearing.  Now 0x%08x",
 348                                 pci->pme_msg_det);
 349                 }
 350                 printf("\n");
 351
 352                 /* outbound memory */
 353                 pci_set_region(r++,
 354                                 CONFIG_SYS_PCIE1_MEM_BUS,
 355                                 CONFIG_SYS_PCIE1_MEM_PHYS,
 356                                 CONFIG_SYS_PCIE1_MEM_SIZE,
 357                                 PCI_REGION_MEM);
 358
 359                 /* outbound io */
 360                 pci_set_region(r++,
 361                                 CONFIG_SYS_PCIE1_IO_BUS,
 362                                 CONFIG_SYS_PCIE1_IO_PHYS,
 363                                 CONFIG_SYS_PCIE1_IO_SIZE,
 364                                 PCI_REGION_IO);
 365
 366                 hose->region_count = r - hose->regions;
 367                 hose->first_busno = first_free_busno;
 368
 369                 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 370
 371                 first_free_busno = hose->last_busno+1;
 372                 printf("    PCIE1 on bus %02x - %02x\n",
 373                         hose->first_busno, hose->last_busno);
 374
 375         } else {
 376                 printf("    PCIE1: disabled\n");
 377         }
 378 #else
 379         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 380 #endif
 381 }
 382 #endif
 383
 384 int board_early_init_r(void)
 385 {
 386         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 387         const u8 flash_esel = 2;
 388
 389         /*
 390          * Remap Boot flash + PROMJET region to caching-inhibited
 391          * so that flash can be erased properly.
 392          */
 393
 394         /* Flush d-cache and invalidate i-cache of any FLASH data */
 395         flush_dcache();
 396         invalidate_icache();
 397
 398         /* invalidate existing TLB entry for flash + promjet */
 399         disable_tlb(flash_esel);
 400
 401         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 402                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 403                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 404
 405         return 0;
 406 }
 407
 408 #ifdef CONFIG_GET_CLK_FROM_ICS307
 409 /* decode S[0-2] to Output Divider (OD) */
 410 static unsigned char ics307_S_to_OD[] = {
 411         10, 2, 8, 4, 5, 7, 3, 6
 412 };
 413
 414 /* Calculate frequency being generated by ICS307-02 clock chip based upon
 415  * the control bytes being programmed into it. */
 416 /* XXX: This function should probably go into a common library */
 417 static unsigned long
 418 ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
 419 {
 420         const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
 421         unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 422         unsigned long RDW = cw2 & 0x7F;
 423         unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
 424         unsigned long freq;
 425
 426         /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
 427
 428         /* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 429          * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 430          * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 431          *
 432          * R6:R0 = Reference Divider Word (RDW)
 433          * V8:V0 = VCO Divider Word (VDW)
 434          * S2:S0 = Output Divider Select (OD)
 435          * F1:F0 = Function of CLK2 Output
 436          * TTL = duty cycle
 437          * C1:C0 = internal load capacitance for cyrstal
 438          */
 439
 440         /* Adding 1 to get a "nicely" rounded number, but this needs
 441          * more tweaking to get a "properly" rounded number. */
 442
 443         freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
 444
 445         debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
 446                         freq);
 447         return freq;
 448 }
 449
 450 unsigned long get_board_sys_clk(ulong dummy)
 451 {
 452         return gd->bus_clk;
 453 }
 454
 455 unsigned long get_board_ddr_clk(ulong dummy)
 456 {
 457         return gd->mem_clk;
 458 }
 459
 460 unsigned long
 461 calculate_board_sys_clk(ulong dummy)
 462 {
 463         ulong val;
 464         u8 *pixis_base = (u8 *)PIXIS_BASE;
 465
 466         val = ics307_clk_freq(
 467             in_8(pixis_base + PIXIS_VSYSCLK0),
 468             in_8(pixis_base + PIXIS_VSYSCLK1),
 469             in_8(pixis_base + PIXIS_VSYSCLK2));
 470         debug("sysclk val = %lu\n", val);
 471         return val;
 472 }
 473
 474 unsigned long
 475 calculate_board_ddr_clk(ulong dummy)
 476 {
 477         ulong val;
 478         u8 *pixis_base = (u8 *)PIXIS_BASE;
 479
 480         val = ics307_clk_freq(
 481             in_8(pixis_base + PIXIS_VDDRCLK0),
 482             in_8(pixis_base + PIXIS_VDDRCLK1),
 483             in_8(pixis_base + PIXIS_VDDRCLK2));
 484         debug("ddrclk val = %lu\n", val);
 485         return val;
 486 }
 487 #else
 488 unsigned long get_board_sys_clk(ulong dummy)
 489 {
 490         u8 i;
 491         ulong val = 0;
 492         u8 *pixis_base = (u8 *)PIXIS_BASE;
 493
 494         i = in_8(pixis_base + PIXIS_SPD);
 495         i &= 0x07;
 496
 497         switch (i) {
 498                 case 0:
 499                         val = 33333333;
 500                         break;
 501                 case 1:
 502                         val = 40000000;
 503                         break;
 504                 case 2:
 505                         val = 50000000;
 506                         break;
 507                 case 3:
 508                         val = 66666666;
 509                         break;
 510                 case 4:
 511                         val = 83333333;
 512                         break;
 513                 case 5:
 514                         val = 100000000;
 515                         break;
 516                 case 6:
 517                         val = 133333333;
 518                         break;
 519                 case 7:
 520                         val = 166666666;
 521                         break;
 522         }
 523
 524         return val;
 525 }
 526
 527 unsigned long get_board_ddr_clk(ulong dummy)
 528 {
 529         u8 i;
 530         ulong val = 0;
 531         u8 *pixis_base = (u8 *)PIXIS_BASE;
 532
 533         i = in_8(pixis_base + PIXIS_SPD);
 534         i &= 0x38;
 535         i >>= 3;
 536
 537         switch (i) {
 538                 case 0:
 539                         val = 33333333;
 540                         break;
 541                 case 1:
 542                         val = 40000000;
 543                         break;
 544                 case 2:
 545                         val = 50000000;
 546                         break;
 547                 case 3:
 548                         val = 66666666;
 549                         break;
 550                 case 4:
 551                         val = 83333333;
 552                         break;
 553                 case 5:
 554                         val = 100000000;
 555                         break;
 556                 case 6:
 557                         val = 133333333;
 558                         break;
 559                 case 7:
 560                         val = 166666666;
 561                         break;
 562         }
 563         return val;
 564 }
 565 #endif
 566
 567 #ifdef CONFIG_TSEC_ENET
 568 int board_eth_init(bd_t *bis)
 569 {
 570         struct tsec_info_struct tsec_info[4];
 571         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 572         int num = 0;
 573
 574 #ifdef CONFIG_TSEC1
 575         SET_STD_TSEC_INFO(tsec_info[num], 1);
 576         num++;
 577 #endif
 578 #ifdef CONFIG_TSEC2
 579         SET_STD_TSEC_INFO(tsec_info[num], 2);
 580         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 581                 tsec_info[num].flags |= TSEC_SGMII;
 582         num++;
 583 #endif
 584 #ifdef CONFIG_TSEC3
 585         SET_STD_TSEC_INFO(tsec_info[num], 3);
 586         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 587                 tsec_info[num].flags |= TSEC_SGMII;
 588         num++;
 589 #endif
 590
 591         if (!num) {
 592                 printf("No TSECs initialized\n");
 593
 594                 return 0;
 595         }
 596
 597 #ifdef CONFIG_FSL_SGMII_RISER
 598         fsl_sgmii_riser_init(tsec_info, num);
 599 #endif
 600
 601         tsec_eth_init(bis, tsec_info, num);
 602
 603         return pci_eth_init(bis);
 604 }
 605 #endif
 606
 607 #if defined(CONFIG_OF_BOARD_SETUP)
 608 void ft_board_setup(void *blob, bd_t *bd)
 609 {
 610         phys_addr_t base;
 611         phys_size_t size;
 612
 613         ft_cpu_setup(blob, bd);
 614
 615         base = getenv_bootm_low();
 616         size = getenv_bootm_size();
 617
 618         fdt_fixup_memory(blob, (u64)base, (u64)size);
 619
 620 #ifdef CONFIG_PCIE3
 621         ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
 622 #endif
 623 #ifdef CONFIG_PCIE2
 624         ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 625 #endif
 626 #ifdef CONFIG_PCIE1
 627         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 628 #endif
 629 #ifdef CONFIG_FSL_SGMII_RISER
 630         fsl_sgmii_riser_fdt_fixup(blob);
 631 #endif
 632 }
 633 #endif
 634
 635 #ifdef CONFIG_MP
 636 void board_lmb_reserve(struct lmb *lmb)
 637 {
 638         cpu_mp_lmb_reserve(lmb);
 639 }
 640 #endif