board/freescale/t104xrdb/t104xrdb.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <netdev.h>
  10 #include <linux/compiler.h>
  11 #include <asm/mmu.h>
  12 #include <asm/processor.h>
  13 #include <asm/cache.h>
  14 #include <asm/immap_85xx.h>
  15 #include <asm/fsl_law.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_portals.h>
  18 #include <asm/fsl_liodn.h>
  19 #include <fm_eth.h>
  20 #include "../common/sleep.h"
  21 #include "t104xrdb.h"
  22 #include "cpld.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 int checkboard(void)
  27 {
  28         struct cpu_type *cpu = gd->arch.cpu;
  29         u8 sw;
  30
  31 #ifdef CONFIG_T104XD4RDB
  32         printf("Board: %sD4RDB\n", cpu->name);
  33 #else
  34         printf("Board: %sRDB\n", cpu->name);
  35 #endif
  36         printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
  37                CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  38
  39         sw = CPLD_READ(flash_ctl_status);
  40         sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  41
  42         if (sw <= 7)
  43                 printf("vBank: %d\n", sw);
  44         else
  45                 printf("Unsupported Bank=%x\n", sw);
  46
  47         return 0;
  48 }
  49
  50 int board_early_init_f(void)
  51 {
  52 #if defined(CONFIG_DEEP_SLEEP)
  53         if (is_warm_boot())
  54                 fsl_dp_disable_console();
  55 #endif
  56
  57         return 0;
  58 }
  59
  60 int board_early_init_r(void)
  61 {
  62 #ifdef CONFIG_SYS_FLASH_BASE
  63         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  64         int flash_esel = find_tlb_idx((void *)flashbase, 1);
  65
  66         /*
  67          * Remap Boot flash region to caching-inhibited
  68          * so that flash can be erased properly.
  69          */
  70
  71         /* Flush d-cache and invalidate i-cache of any FLASH data */
  72         flush_dcache();
  73         invalidate_icache();
  74
  75         if (flash_esel == -1) {
  76                 /* very unlikely unless something is messed up */
  77                 puts("Error: Could not find TLB for FLASH BASE\n");
  78                 flash_esel = 2; /* give our best effort to continue */
  79         } else {
  80                 /* invalidate existing TLB entry for flash */
  81                 disable_tlb(flash_esel);
  82         }
  83
  84         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  85                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  86                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  87 #endif
  88         set_liodns();
  89 #ifdef CONFIG_SYS_DPAA_QBMAN
  90         setup_portals();
  91 #endif
  92
  93         return 0;
  94 }
  95
  96 int misc_init_r(void)
  97 {
  98         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  99         u32 srds_s1;
 100
 101         srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
 102
 103         printf("SERDES Reference : 0x%X\n", srds_s1);
 104
 105         /* select SGMII*/
 106         if (srds_s1 == 0x86)
 107                 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
 108                                          MISC_CTL_SG_SEL);
 109
 110         /* select SGMII and Aurora*/
 111         if (srds_s1 == 0x8E)
 112                 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
 113                                          MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
 114
 115 #if defined(CONFIG_T1040D4RDB)
 116         /* Mask all CPLD interrupt sources, except QSGMII interrupts */
 117         if (CPLD_READ(sw_ver) < 0x03) {
 118                 debug("CPLD SW version 0x%02x doesn't support int_mask\n",
 119                       CPLD_READ(sw_ver));
 120         } else {
 121                 CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
 122                            ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
 123         }
 124 #endif
 125
 126         return 0;
 127 }
 128
 129 int ft_board_setup(void *blob, bd_t *bd)
 130 {
 131         phys_addr_t base;
 132         phys_size_t size;
 133
 134         ft_cpu_setup(blob, bd);
 135
 136         base = getenv_bootm_low();
 137         size = getenv_bootm_size();
 138
 139         fdt_fixup_memory(blob, (u64)base, (u64)size);
 140
 141 #ifdef CONFIG_PCI
 142         pci_of_setup(blob, bd);
 143 #endif
 144
 145         fdt_fixup_liodn(blob);
 146
 147 #ifdef CONFIG_HAS_FSL_DR_USB
 148         fdt_fixup_dr_usb(blob, bd);
 149 #endif
 150
 151 #ifdef CONFIG_SYS_DPAA_FMAN
 152         fdt_fixup_fman_ethernet(blob);
 153 #endif
 154
 155         return 0;
 156 }