board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/imx-common/iomux-v3.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/sata.h>
  23 #include <asm/imx-common/spi.h>
  24 #include <asm/imx-common/video.h>
  25 #include <jffs2/load_kernel.h>
  26 #include <hwconfig.h>
  27 #include <i2c.h>
  28 #include <linux/ctype.h>
  29 #include <fdt_support.h>
  30 #include <fsl_esdhc.h>
  31 #include <miiphy.h>
  32 #include <mmc.h>
  33 #include <mtd_node.h>
  34 #include <netdev.h>
  35 #include <pci.h>
  36 #include <power/pmic.h>
  37 #include <power/ltc3676_pmic.h>
  38 #include <power/pfuze100_pmic.h>
  39 #include <fdt_support.h>
  40 #include <jffs2/load_kernel.h>
  41 #include <spi_flash.h>
  42
  43 #include "gsc.h"
  44 #include "ventana_eeprom.h"
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 /* GPIO's common to all baseboards */
  49 #define GP_PHY_RST      IMX_GPIO_NR(1, 30)
  50 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  51 #define GP_SD3_CD       IMX_GPIO_NR(7, 0)
  52 #define GP_RS232_EN     IMX_GPIO_NR(2, 11)
  53 #define GP_MSATA_SEL    IMX_GPIO_NR(2, 8)
  54
  55 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  56         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  57         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  58
  59 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  60         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  61         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  62
  63 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  64         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  65         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  66
  67 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  68         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  69         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  70
  71 #define DIO_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  72         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  73         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  74
  75 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  76         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  77         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  78
  79 #define IRQ_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  80         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  81         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  82
  83 #define DIO_PAD_CFG   (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
  84
  85
  86 /*
  87  * EEPROM board info struct populated by read_eeprom so that we only have to
  88  * read it once.
  89  */
  90 struct ventana_board_info ventana_info;
  91
  92 static int board_type;
  93
  94 /* UART1: Function varies per baseboard */
  95 static iomux_v3_cfg_t const uart1_pads[] = {
  96         IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  97         IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  98 };
  99
 100 /* UART2: Serial Console */
 101 static iomux_v3_cfg_t const uart2_pads[] = {
 102         IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 103         IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 104 };
 105
 106 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 107
 108 /* I2C1: GSC */
 109 static struct i2c_pads_info mx6q_i2c_pad_info0 = {
 110         .scl = {
 111                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
 112                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
 113                 .gp = IMX_GPIO_NR(3, 21)
 114         },
 115         .sda = {
 116                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
 117                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
 118                 .gp = IMX_GPIO_NR(3, 28)
 119         }
 120 };
 121 static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
 122         .scl = {
 123                 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
 124                 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
 125                 .gp = IMX_GPIO_NR(3, 21)
 126         },
 127         .sda = {
 128                 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
 129                 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
 130                 .gp = IMX_GPIO_NR(3, 28)
 131         }
 132 };
 133
 134 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
 135 static struct i2c_pads_info mx6q_i2c_pad_info1 = {
 136         .scl = {
 137                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 138                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
 139                 .gp = IMX_GPIO_NR(4, 12)
 140         },
 141         .sda = {
 142                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 143                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 144                 .gp = IMX_GPIO_NR(4, 13)
 145         }
 146 };
 147 static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 148         .scl = {
 149                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
 150                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
 151                 .gp = IMX_GPIO_NR(4, 12)
 152         },
 153         .sda = {
 154                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 155                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 156                 .gp = IMX_GPIO_NR(4, 13)
 157         }
 158 };
 159
 160 /* I2C3: Misc/Expansion */
 161 static struct i2c_pads_info mx6q_i2c_pad_info2 = {
 162         .scl = {
 163                 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
 164                 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
 165                 .gp = IMX_GPIO_NR(1, 3)
 166         },
 167         .sda = {
 168                 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
 169                 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
 170                 .gp = IMX_GPIO_NR(1, 6)
 171         }
 172 };
 173 static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
 174         .scl = {
 175                 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
 176                 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
 177                 .gp = IMX_GPIO_NR(1, 3)
 178         },
 179         .sda = {
 180                 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
 181                 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
 182                 .gp = IMX_GPIO_NR(1, 6)
 183         }
 184 };
 185
 186 /* MMC */
 187 static iomux_v3_cfg_t const usdhc3_pads[] = {
 188         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 189         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 190         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 191         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 192         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 193         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 194         /* CD */
 195         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 196 };
 197
 198 /* ENET */
 199 static iomux_v3_cfg_t const enet_pads[] = {
 200         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 201         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 202         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 203         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 204         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 205         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 206         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 207         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 208                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 209         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
 210                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 211         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 212         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 213         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 214         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 215         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 216         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 217                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 218         /* PHY nRST */
 219         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
 220 };
 221
 222 /* NAND */
 223 static iomux_v3_cfg_t const nfc_pads[] = {
 224         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 225         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 226         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 227         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 228         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 229         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 230         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 231         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 232         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 233         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 234         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 235         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 236         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 237         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 238         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 239 };
 240
 241 #ifdef CONFIG_CMD_NAND
 242 static void setup_gpmi_nand(void)
 243 {
 244         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 245
 246         /* config gpmi nand iomux */
 247         SETUP_IOMUX_PADS(nfc_pads);
 248
 249         /* config gpmi and bch clock to 100 MHz */
 250         clrsetbits_le32(&mxc_ccm->cs2cdr,
 251                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 252                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 253                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 254                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 255                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 256                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 257
 258         /* enable gpmi and bch clock gating */
 259         setbits_le32(&mxc_ccm->CCGR4,
 260                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 261                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 262                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 263                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 264                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 265
 266         /* enable apbh clock gating */
 267         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 268 }
 269 #endif
 270
 271 static void setup_iomux_enet(void)
 272 {
 273         SETUP_IOMUX_PADS(enet_pads);
 274
 275         /* toggle PHY_RST# */
 276         gpio_direction_output(GP_PHY_RST, 0);
 277         mdelay(2);
 278         gpio_set_value(GP_PHY_RST, 1);
 279 }
 280
 281 static void setup_iomux_uart(void)
 282 {
 283         SETUP_IOMUX_PADS(uart1_pads);
 284         SETUP_IOMUX_PADS(uart2_pads);
 285 }
 286
 287 #ifdef CONFIG_USB_EHCI_MX6
 288 static iomux_v3_cfg_t const usb_pads[] = {
 289         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 290         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 291         /* OTG PWR */
 292         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 293 };
 294
 295 int board_ehci_hcd_init(int port)
 296 {
 297         struct ventana_board_info *info = &ventana_info;
 298
 299         SETUP_IOMUX_PADS(usb_pads);
 300
 301         /* Reset USB HUB (present on GW54xx/GW53xx) */
 302         switch (info->model[3]) {
 303         case '3': /* GW53xx */
 304         case '5': /* GW552x */
 305                 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
 306                 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
 307                 mdelay(2);
 308                 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
 309                 break;
 310         case '4': /* GW54xx */
 311                 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
 312                 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
 313                 mdelay(2);
 314                 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
 315                 break;
 316         }
 317
 318         return 0;
 319 }
 320
 321 int board_ehci_power(int port, int on)
 322 {
 323         if (port)
 324                 return 0;
 325         gpio_set_value(GP_USB_OTG_PWR, on);
 326         return 0;
 327 }
 328 #endif /* CONFIG_USB_EHCI_MX6 */
 329
 330 #ifdef CONFIG_FSL_ESDHC
 331 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 332
 333 int board_mmc_getcd(struct mmc *mmc)
 334 {
 335         /* Card Detect */
 336         gpio_direction_input(GP_SD3_CD);
 337         return !gpio_get_value(GP_SD3_CD);
 338 }
 339
 340 int board_mmc_init(bd_t *bis)
 341 {
 342         /* Only one USDHC controller on Ventana */
 343         SETUP_IOMUX_PADS(usdhc3_pads);
 344         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 345         usdhc_cfg.max_bus_width = 4;
 346
 347         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 348 }
 349 #endif /* CONFIG_FSL_ESDHC */
 350
 351 #ifdef CONFIG_MXC_SPI
 352 iomux_v3_cfg_t const ecspi1_pads[] = {
 353         /* SS1 */
 354         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 355         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 356         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 357         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 358 };
 359
 360 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 361 {
 362         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 363 }
 364
 365 static void setup_spi(void)
 366 {
 367         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 368         SETUP_IOMUX_PADS(ecspi1_pads);
 369 }
 370 #endif
 371
 372 /* configure eth0 PHY board-specific LED behavior */
 373 int board_phy_config(struct phy_device *phydev)
 374 {
 375         unsigned short val;
 376
 377         /* Marvel 88E1510 */
 378         if (phydev->phy_id == 0x1410dd1) {
 379                 /*
 380                  * Page 3, Register 16: LED[2:0] Function Control Register
 381                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 382                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 383                  */
 384                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 385                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 386                 val &= 0xff00;
 387                 val |= 0x0017;
 388                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 389                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 390         }
 391
 392         if (phydev->drv->config)
 393                 phydev->drv->config(phydev);
 394
 395         return 0;
 396 }
 397
 398 int board_eth_init(bd_t *bis)
 399 {
 400 #ifdef CONFIG_FEC_MXC
 401         if (board_type != GW551x && board_type != GW552x) {
 402                 setup_iomux_enet();
 403                 cpu_eth_init(bis);
 404         }
 405 #endif
 406
 407 #ifdef CONFIG_E1000
 408         e1000_initialize(bis);
 409 #endif
 410
 411 #ifdef CONFIG_CI_UDC
 412         /* For otg ethernet*/
 413         usb_eth_initialize(bis);
 414 #endif
 415
 416         /* default to the first detected enet dev */
 417         if (!getenv("ethprime")) {
 418                 struct eth_device *dev = eth_get_dev_by_index(0);
 419                 if (dev) {
 420                         setenv("ethprime", dev->name);
 421                         printf("set ethprime to %s\n", getenv("ethprime"));
 422                 }
 423         }
 424
 425         return 0;
 426 }
 427
 428 #if defined(CONFIG_VIDEO_IPUV3)
 429
 430 static void enable_hdmi(struct display_info_t const *dev)
 431 {
 432         imx_enable_hdmi_phy();
 433 }
 434
 435 static int detect_i2c(struct display_info_t const *dev)
 436 {
 437         return i2c_set_bus_num(dev->bus) == 0 &&
 438                 i2c_probe(dev->addr) == 0;
 439 }
 440
 441 static void enable_lvds(struct display_info_t const *dev)
 442 {
 443         struct iomuxc *iomux = (struct iomuxc *)
 444                                 IOMUXC_BASE_ADDR;
 445
 446         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 447         u32 reg = readl(&iomux->gpr[2]);
 448         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 449         writel(reg, &iomux->gpr[2]);
 450
 451         /* Enable Backlight */
 452         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 453         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 454 }
 455
 456 struct display_info_t const displays[] = {{
 457         /* HDMI Output */
 458         .bus    = -1,
 459         .addr   = 0,
 460         .pixfmt = IPU_PIX_FMT_RGB24,
 461         .detect = detect_hdmi,
 462         .enable = enable_hdmi,
 463         .mode   = {
 464                 .name           = "HDMI",
 465                 .refresh        = 60,
 466                 .xres           = 1024,
 467                 .yres           = 768,
 468                 .pixclock       = 15385,
 469                 .left_margin    = 220,
 470                 .right_margin   = 40,
 471                 .upper_margin   = 21,
 472                 .lower_margin   = 7,
 473                 .hsync_len      = 60,
 474                 .vsync_len      = 10,
 475                 .sync           = FB_SYNC_EXT,
 476                 .vmode          = FB_VMODE_NONINTERLACED
 477 } }, {
 478         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 479         .bus    = 2,
 480         .addr   = 0x4,
 481         .pixfmt = IPU_PIX_FMT_LVDS666,
 482         .detect = detect_i2c,
 483         .enable = enable_lvds,
 484         .mode   = {
 485                 .name           = "Hannstar-XGA",
 486                 .refresh        = 60,
 487                 .xres           = 1024,
 488                 .yres           = 768,
 489                 .pixclock       = 15385,
 490                 .left_margin    = 220,
 491                 .right_margin   = 40,
 492                 .upper_margin   = 21,
 493                 .lower_margin   = 7,
 494                 .hsync_len      = 60,
 495                 .vsync_len      = 10,
 496                 .sync           = FB_SYNC_EXT,
 497                 .vmode          = FB_VMODE_NONINTERLACED
 498 } }, {
 499         /* DLC700JMG-T-4 */
 500         .bus    = 0,
 501         .addr   = 0,
 502         .detect = NULL,
 503         .enable = enable_lvds,
 504         .pixfmt = IPU_PIX_FMT_LVDS666,
 505         .mode   = {
 506                 .name           = "DLC700JMGT4",
 507                 .refresh        = 60,
 508                 .xres           = 1024,         /* 1024x600active pixels */
 509                 .yres           = 600,
 510                 .pixclock       = 15385,        /* 64MHz */
 511                 .left_margin    = 220,
 512                 .right_margin   = 40,
 513                 .upper_margin   = 21,
 514                 .lower_margin   = 7,
 515                 .hsync_len      = 60,
 516                 .vsync_len      = 10,
 517                 .sync           = FB_SYNC_EXT,
 518                 .vmode          = FB_VMODE_NONINTERLACED
 519 } }, {
 520         /* DLC800FIG-T-3 */
 521         .bus    = 0,
 522         .addr   = 0,
 523         .detect = NULL,
 524         .enable = enable_lvds,
 525         .pixfmt = IPU_PIX_FMT_LVDS666,
 526         .mode   = {
 527                 .name           = "DLC800FIGT3",
 528                 .refresh        = 60,
 529                 .xres           = 1024,         /* 1024x768 active pixels */
 530                 .yres           = 768,
 531                 .pixclock       = 15385,        /* 64MHz */
 532                 .left_margin    = 220,
 533                 .right_margin   = 40,
 534                 .upper_margin   = 21,
 535                 .lower_margin   = 7,
 536                 .hsync_len      = 60,
 537                 .vsync_len      = 10,
 538                 .sync           = FB_SYNC_EXT,
 539                 .vmode          = FB_VMODE_NONINTERLACED
 540 } } };
 541 size_t display_count = ARRAY_SIZE(displays);
 542
 543 static void setup_display(void)
 544 {
 545         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 546         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 547         int reg;
 548
 549         enable_ipu_clock();
 550         imx_setup_hdmi();
 551         /* Turn on LDB0,IPU,IPU DI0 clocks */
 552         reg = __raw_readl(&mxc_ccm->CCGR3);
 553         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 554         writel(reg, &mxc_ccm->CCGR3);
 555
 556         /* set LDB0, LDB1 clk select to 011/011 */
 557         reg = readl(&mxc_ccm->cs2cdr);
 558         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 559                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 560         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 561               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 562         writel(reg, &mxc_ccm->cs2cdr);
 563
 564         reg = readl(&mxc_ccm->cscmr2);
 565         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 566         writel(reg, &mxc_ccm->cscmr2);
 567
 568         reg = readl(&mxc_ccm->chsccdr);
 569         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 570                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 571         writel(reg, &mxc_ccm->chsccdr);
 572
 573         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 574              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 575              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 576              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 577              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 578              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 579              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 580              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 581              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 582         writel(reg, &iomux->gpr[2]);
 583
 584         reg = readl(&iomux->gpr[3]);
 585         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 586             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 587                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 588         writel(reg, &iomux->gpr[3]);
 589
 590         /* Backlight CABEN on LVDS connector */
 591         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 592         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 593 }
 594 #endif /* CONFIG_VIDEO_IPUV3 */
 595
 596 /*
 597  * Baseboard specific GPIO
 598  */
 599
 600 /* common to add baseboards */
 601 static iomux_v3_cfg_t const gw_gpio_pads[] = {
 602         /* MSATA_EN */
 603         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 604         /* RS232_EN# */
 605         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 606 };
 607
 608 /* prototype */
 609 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
 610         /* PANLEDG# */
 611         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 612         /* PANLEDR# */
 613         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 614         /* LOCLED# */
 615         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 616         /* RS485_EN */
 617         IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
 618         /* IOEXP_PWREN# */
 619         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 620         /* IOEXP_IRQ# */
 621         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 622         /* VID_EN */
 623         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 624         /* DIOI2C_DIS# */
 625         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 626         /* PCICK_SSON */
 627         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
 628         /* PCI_RST# */
 629         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 630 };
 631
 632 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 633         /* PANLEDG# */
 634         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 635         /* PANLEDR# */
 636         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 637         /* IOEXP_PWREN# */
 638         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 639         /* IOEXP_IRQ# */
 640         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 641
 642         /* GPS_SHDN */
 643         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 644         /* VID_PWR */
 645         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 646         /* PCI_RST# */
 647         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
 648         /* PCIESKT_WDIS# */
 649         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 650 };
 651
 652 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 653         /* PANLEDG# */
 654         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 655         /* PANLEDR# */
 656         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 657         /* IOEXP_PWREN# */
 658         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 659         /* IOEXP_IRQ# */
 660         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 661
 662         /* MX6_LOCLED# */
 663         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 664         /* GPS_SHDN */
 665         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 666         /* USBOTG_SEL */
 667         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 668         /* VID_PWR */
 669         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 670         /* PCI_RST# */
 671         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 672         /* PCI_RST# (GW522x) */
 673         IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG),
 674         /* PCIESKT_WDIS# */
 675         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 676 };
 677
 678 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 679         /* PANLEDG# */
 680         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 681         /* PANLEDR# */
 682         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 683         /* MX6_LOCLED# */
 684         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 685         /* IOEXP_PWREN# */
 686         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 687         /* IOEXP_IRQ# */
 688         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 689         /* DIOI2C_DIS# */
 690         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 691         /* GPS_SHDN */
 692         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 693         /* VID_EN */
 694         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 695         /* PCI_RST# */
 696         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 697         /* PCIESKT_WDIS# */
 698         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 699 };
 700
 701 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
 702         /* PANLEDG# */
 703         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 704         /* PANLEDR# */
 705         IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
 706         /* MX6_LOCLED# */
 707         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 708         /* MIPI_DIO */
 709         IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
 710         /* RS485_EN */
 711         IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
 712         /* IOEXP_PWREN# */
 713         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 714         /* IOEXP_IRQ# */
 715         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 716         /* DIOI2C_DIS# */
 717         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 718         /* PCI_RST# */
 719         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 720         /* VID_EN */
 721         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 722         /* PCIESKT_WDIS# */
 723         IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
 724 };
 725
 726 static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
 727         /* PANLED# */
 728         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 729         /* PCI_RST# */
 730         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
 731         /* PCIESKT_WDIS# */
 732         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 733 };
 734
 735 static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
 736         /* PANLEDG# */
 737         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 738         /* PANLEDR# */
 739         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 740         /* MX6_LOCLED# */
 741         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 742         /* PCI_RST# */
 743         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 744         /* MX6_DIO[4:9] */
 745         IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
 746         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 747         IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
 748         IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
 749         IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
 750         IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
 751         /* PCIEGBE1_OFF# */
 752         IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
 753         /* PCIEGBE2_OFF# */
 754         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 755         /* PCIESKT_WDIS# */
 756         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 757 };
 758
 759 /*
 760  * each baseboard has 4 user configurable Digital IO lines which can
 761  * be pinmuxed as a GPIO or in some cases a PWM
 762  */
 763 struct dio_cfg {
 764         iomux_v3_cfg_t gpio_padmux[2];
 765         unsigned gpio_param;
 766         iomux_v3_cfg_t pwm_padmux[2];
 767         unsigned pwm_param;
 768 };
 769
 770 struct ventana {
 771         /* pinmux */
 772         iomux_v3_cfg_t const *gpio_pads;
 773         int num_pads;
 774         /* DIO pinmux/val */
 775         struct dio_cfg dio_cfg[4];
 776         int num_gpios;
 777         /* various gpios (0 if non-existent) */
 778         int leds[3];
 779         int pcie_rst;
 780         int mezz_pwren;
 781         int mezz_irq;
 782         int rs485en;
 783         int gps_shdn;
 784         int vidin_en;
 785         int dioi2c_en;
 786         int pcie_sson;
 787         int usb_sel;
 788         int wdis;
 789 };
 790
 791 static struct ventana gpio_cfg[] = {
 792         /* GW5400proto */
 793         {
 794                 .gpio_pads = gw54xx_gpio_pads,
 795                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 796                 .dio_cfg = {
 797                         {
 798                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 799                                 IMX_GPIO_NR(1, 9),
 800                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 801                                 1
 802                         },
 803                         {
 804                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 805                                 IMX_GPIO_NR(1, 19),
 806                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 807                                 2
 808                         },
 809                         {
 810                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 811                                 IMX_GPIO_NR(2, 9),
 812                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 813                                 3
 814                         },
 815                         {
 816                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 817                                 IMX_GPIO_NR(2, 10),
 818                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 819                                 4
 820                         },
 821                 },
 822                 .num_gpios = 4,
 823                 .leds = {
 824                         IMX_GPIO_NR(4, 6),
 825                         IMX_GPIO_NR(4, 10),
 826                         IMX_GPIO_NR(4, 15),
 827                 },
 828                 .pcie_rst = IMX_GPIO_NR(1, 29),
 829                 .mezz_pwren = IMX_GPIO_NR(4, 7),
 830                 .mezz_irq = IMX_GPIO_NR(4, 9),
 831                 .rs485en = IMX_GPIO_NR(3, 24),
 832                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 833                 .pcie_sson = IMX_GPIO_NR(1, 20),
 834         },
 835
 836         /* GW51xx */
 837         {
 838                 .gpio_pads = gw51xx_gpio_pads,
 839                 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
 840                 .dio_cfg = {
 841                         {
 842                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 843                                 IMX_GPIO_NR(1, 16),
 844                                 { 0, 0 },
 845                                 0
 846                         },
 847                         {
 848                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 849                                 IMX_GPIO_NR(1, 19),
 850                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 851                                 2
 852                         },
 853                         {
 854                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 855                                 IMX_GPIO_NR(1, 17),
 856                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 857                                 3
 858                         },
 859                         {
 860                                 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
 861                                 IMX_GPIO_NR(1, 18),
 862                                 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
 863                                 4
 864                         },
 865                 },
 866                 .num_gpios = 4,
 867                 .leds = {
 868                         IMX_GPIO_NR(4, 6),
 869                         IMX_GPIO_NR(4, 10),
 870                 },
 871                 .pcie_rst = IMX_GPIO_NR(1, 0),
 872                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 873                 .mezz_irq = IMX_GPIO_NR(2, 18),
 874                 .gps_shdn = IMX_GPIO_NR(1, 2),
 875                 .vidin_en = IMX_GPIO_NR(5, 20),
 876                 .wdis = IMX_GPIO_NR(7, 12),
 877         },
 878
 879         /* GW52xx */
 880         {
 881                 .gpio_pads = gw52xx_gpio_pads,
 882                 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
 883                 .dio_cfg = {
 884                         {
 885                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 886                                 IMX_GPIO_NR(1, 16),
 887                                 { 0, 0 },
 888                                 0
 889                         },
 890                         {
 891                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 892                                 IMX_GPIO_NR(1, 19),
 893                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 894                                 2
 895                         },
 896                         {
 897                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 898                                 IMX_GPIO_NR(1, 17),
 899                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 900                                 3
 901                         },
 902                         {
 903                                 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 904                                 IMX_GPIO_NR(1, 20),
 905                                 { 0, 0 },
 906                                 0
 907                         },
 908                 },
 909                 .num_gpios = 4,
 910                 .leds = {
 911                         IMX_GPIO_NR(4, 6),
 912                         IMX_GPIO_NR(4, 7),
 913                         IMX_GPIO_NR(4, 15),
 914                 },
 915                 .pcie_rst = IMX_GPIO_NR(1, 29),
 916                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 917                 .mezz_irq = IMX_GPIO_NR(2, 18),
 918                 .gps_shdn = IMX_GPIO_NR(1, 27),
 919                 .vidin_en = IMX_GPIO_NR(3, 31),
 920                 .usb_sel = IMX_GPIO_NR(1, 2),
 921                 .wdis = IMX_GPIO_NR(7, 12),
 922         },
 923
 924         /* GW53xx */
 925         {
 926                 .gpio_pads = gw53xx_gpio_pads,
 927                 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
 928                 .dio_cfg = {
 929                         {
 930                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 931                                 IMX_GPIO_NR(1, 16),
 932                                 { 0, 0 },
 933                                 0
 934                         },
 935                         {
 936                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 937                                 IMX_GPIO_NR(1, 19),
 938                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 939                                 2
 940                         },
 941                         {
 942                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 943                                 IMX_GPIO_NR(1, 17),
 944                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 945                                 3
 946                         },
 947                         {
 948                                 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 949                                 IMX_GPIO_NR(1, 20),
 950                                 { 0, 0 },
 951                                 0
 952                         },
 953                 },
 954                 .num_gpios = 4,
 955                 .leds = {
 956                         IMX_GPIO_NR(4, 6),
 957                         IMX_GPIO_NR(4, 7),
 958                         IMX_GPIO_NR(4, 15),
 959                 },
 960                 .pcie_rst = IMX_GPIO_NR(1, 29),
 961                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 962                 .mezz_irq = IMX_GPIO_NR(2, 18),
 963                 .gps_shdn = IMX_GPIO_NR(1, 27),
 964                 .vidin_en = IMX_GPIO_NR(3, 31),
 965                 .wdis = IMX_GPIO_NR(7, 12),
 966         },
 967
 968         /* GW54xx */
 969         {
 970                 .gpio_pads = gw54xx_gpio_pads,
 971                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 972                 .dio_cfg = {
 973                         {
 974                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 975                                 IMX_GPIO_NR(1, 9),
 976                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 977                                 1
 978                         },
 979                         {
 980                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 981                                 IMX_GPIO_NR(1, 19),
 982                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 983                                 2
 984                         },
 985                         {
 986                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 987                                 IMX_GPIO_NR(2, 9),
 988                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 989                                 3
 990                         },
 991                         {
 992                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 993                                 IMX_GPIO_NR(2, 10),
 994                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 995                                 4
 996                         },
 997                 },
 998                 .num_gpios = 4,
 999                 .leds = {
1000                         IMX_GPIO_NR(4, 6),
1001                         IMX_GPIO_NR(4, 7),
1002                         IMX_GPIO_NR(4, 15),
1003                 },
1004                 .pcie_rst = IMX_GPIO_NR(1, 29),
1005                 .mezz_pwren = IMX_GPIO_NR(2, 19),
1006                 .mezz_irq = IMX_GPIO_NR(2, 18),
1007                 .rs485en = IMX_GPIO_NR(7, 1),
1008                 .vidin_en = IMX_GPIO_NR(3, 31),
1009                 .dioi2c_en = IMX_GPIO_NR(4,  5),
1010                 .pcie_sson = IMX_GPIO_NR(1, 20),
1011                 .wdis = IMX_GPIO_NR(5, 17),
1012         },
1013
1014         /* GW551x */
1015         {
1016                 .gpio_pads = gw551x_gpio_pads,
1017                 .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
1018                 .dio_cfg = {
1019                         {
1020                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
1021                                 IMX_GPIO_NR(1, 16),
1022                                 { 0, 0 },
1023                                 0
1024                         },
1025                         {
1026                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
1027                                 IMX_GPIO_NR(1, 19),
1028                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
1029                                 2
1030                         },
1031                         {
1032                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
1033                                 IMX_GPIO_NR(1, 17),
1034                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
1035                                 3
1036                         },
1037                         {
1038                                 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
1039                                 IMX_GPIO_NR(1, 18),
1040                                 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
1041                                 4
1042                         },
1043                 },
1044                 .num_gpios = 2,
1045                 .leds = {
1046                         IMX_GPIO_NR(4, 7),
1047                 },
1048                 .pcie_rst = IMX_GPIO_NR(1, 0),
1049                 .wdis = IMX_GPIO_NR(7, 12),
1050         },
1051
1052         /* GW552x */
1053         {
1054                 .gpio_pads = gw552x_gpio_pads,
1055                 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
1056                 .dio_cfg = {
1057                         {
1058                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
1059                                 IMX_GPIO_NR(1, 19),
1060                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
1061                                 2
1062                         },
1063                         {
1064                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
1065                                 IMX_GPIO_NR(1, 17),
1066                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
1067                                 3
1068                         },
1069                 },
1070                 .num_gpios = 4,
1071                 .leds = {
1072                         IMX_GPIO_NR(4, 6),
1073                         IMX_GPIO_NR(4, 7),
1074                         IMX_GPIO_NR(4, 15),
1075                 },
1076                 .pcie_rst = IMX_GPIO_NR(1, 29),
1077                 .wdis = IMX_GPIO_NR(7, 12),
1078         },
1079 };
1080
1081 /* setup board specific PMIC */
1082 int power_init_board(void)
1083 {
1084         struct pmic *p;
1085         u32 reg;
1086
1087         /* configure PFUZE100 PMIC */
1088         if (board_type == GW54xx || board_type == GW54proto) {
1089                 power_pfuze100_init(CONFIG_I2C_PMIC);
1090                 p = pmic_get("PFUZE100");
1091                 if (p && !pmic_probe(p)) {
1092                         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
1093                         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
1094
1095                         /* Set VGEN1 to 1.5V and enable */
1096                         pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
1097                         reg &= ~(LDO_VOL_MASK);
1098                         reg |= (LDOA_1_50V | LDO_EN);
1099                         pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
1100
1101                         /* Set SWBST to 5.0V and enable */
1102                         pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
1103                         reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
1104                         reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
1105                         pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
1106                 }
1107         }
1108
1109         /* configure LTC3676 PMIC */
1110         else {
1111                 power_ltc3676_init(CONFIG_I2C_PMIC);
1112                 p = pmic_get("LTC3676_PMIC");
1113                 if (p && !pmic_probe(p)) {
1114                         puts("PMIC:  LTC3676\n");
1115                         /*
1116                          * set board-specific scalar for max CPU frequency
1117                          * per CPU based on the LDO enabled Operating Ranges
1118                          * defined in the respective IMX6DQ and IMX6SDL
1119                          * datasheets. The voltage resulting from the R1/R2
1120                          * feedback inputs on Ventana is 1308mV. Note that this
1121                          * is a bit shy of the Vmin of 1350mV in the datasheet
1122                          * for LDO enabled mode but is as high as we can go.
1123                          *
1124                          * We will rely on an OS kernel driver to properly
1125                          * regulate these per CPU operating point and use LDO
1126                          * bypass mode when using the higher frequency
1127                          * operating points to compensate as LDO bypass mode
1128                          * allows the rails be 125mV lower.
1129                          */
1130                         /* mask PGOOD during SW1 transition */
1131                         pmic_reg_write(p, LTC3676_DVB1B,
1132                                        0x1f | LTC3676_PGOOD_MASK);
1133                         /* set SW1 (VDD_SOC) */
1134                         pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
1135
1136                         /* mask PGOOD during SW3 transition */
1137                         pmic_reg_write(p, LTC3676_DVB3B,
1138                                        0x1f | LTC3676_PGOOD_MASK);
1139                         /* set SW3 (VDD_ARM) */
1140                         pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
1141                 }
1142         }
1143
1144         return 0;
1145 }
1146
1147 /* setup GPIO pinmux and default configuration per baseboard */
1148 static void setup_board_gpio(int board)
1149 {
1150         struct ventana_board_info *info = &ventana_info;
1151         const char *s;
1152         char arg[10];
1153         size_t len;
1154         int i;
1155         int quiet = simple_strtol(getenv("quiet"), NULL, 10);
1156
1157         if (board >= GW_UNKNOWN)
1158                 return;
1159
1160         /* RS232_EN# */
1161         gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
1162
1163         /* MSATA Enable */
1164         if (is_cpu_type(MXC_CPU_MX6Q) &&
1165             test_bit(EECONFIG_SATA, info->config)) {
1166                 gpio_direction_output(GP_MSATA_SEL,
1167                                       (hwconfig("msata")) ?  1 : 0);
1168         } else {
1169                 gpio_direction_output(GP_MSATA_SEL, 0);
1170         }
1171
1172 #if !defined(CONFIG_CMD_PCI)
1173         /* GW522x Uses GPIO3_IO23 for PCIE_RST# */
1174         if (board_type == GW52xx && info->model[4] == '2')
1175                 gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23);
1176
1177         /* assert PCI_RST# (released by OS when clock is valid) */
1178         gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
1179 #endif
1180
1181         /* turn off (active-high) user LED's */
1182         for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) {
1183                 if (gpio_cfg[board].leds[i])
1184                         gpio_direction_output(gpio_cfg[board].leds[i], 1);
1185         }
1186
1187         /* Expansion Mezzanine IO */
1188         if (gpio_cfg[board].mezz_pwren)
1189                 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1190         if (gpio_cfg[board].mezz_irq)
1191                 gpio_direction_input(gpio_cfg[board].mezz_irq);
1192
1193         /* RS485 Transmit Enable */
1194         if (gpio_cfg[board].rs485en)
1195                 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1196
1197         /* GPS_SHDN */
1198         if (gpio_cfg[board].gps_shdn)
1199                 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1200
1201         /* Analog video codec power enable */
1202         if (gpio_cfg[board].vidin_en)
1203                 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1204
1205         /* DIOI2C_DIS# */
1206         if (gpio_cfg[board].dioi2c_en)
1207                 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1208
1209         /* PCICK_SSON: disable spread-spectrum clock */
1210         if (gpio_cfg[board].pcie_sson)
1211                 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1212
1213         /* USBOTG Select (PCISKT or FrontPanel) */
1214         if (gpio_cfg[board].usb_sel)
1215                 gpio_direction_output(gpio_cfg[board].usb_sel,
1216                                       (hwconfig("usb_pcisel")) ? 1 : 0);
1217
1218
1219         /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1220         if (gpio_cfg[board].wdis)
1221                 gpio_direction_output(gpio_cfg[board].wdis, 1);
1222
1223         /*
1224          * Configure DIO pinmux/padctl registers
1225          * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1226          */
1227         for (i = 0; i < 4; i++) {
1228                 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1229                 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
1230                 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1231
1232                 if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
1233                         continue;
1234                 sprintf(arg, "dio%d", i);
1235                 if (!hwconfig(arg))
1236                         continue;
1237                 s = hwconfig_subarg(arg, "padctrl", &len);
1238                 if (s) {
1239                         ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
1240                                             & 0x1ffff) | MUX_MODE_SION;
1241                 }
1242                 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1243                         if (!quiet) {
1244                                 printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
1245                                        (cfg->gpio_param/32)+1,
1246                                        cfg->gpio_param%32,
1247                                        cfg->gpio_param);
1248                         }
1249                         imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1250                                                ctrl);
1251                         gpio_direction_input(cfg->gpio_param);
1252                 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1253                            cfg->pwm_padmux) {
1254                         if (!quiet)
1255                                 printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
1256                         imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1257                                                MUX_PAD_CTRL(ctrl));
1258                 }
1259         }
1260
1261         if (!quiet) {
1262                 if (is_cpu_type(MXC_CPU_MX6Q) &&
1263                     (test_bit(EECONFIG_SATA, info->config))) {
1264                         printf("MSATA: %s\n", (hwconfig("msata") ?
1265                                "enabled" : "disabled"));
1266                 }
1267                 printf("RS232: %s\n", (hwconfig("rs232")) ?
1268                        "enabled" : "disabled");
1269         }
1270 }
1271
1272 #if defined(CONFIG_CMD_PCI)
1273 int imx6_pcie_toggle_reset(void)
1274 {
1275         if (board_type < GW_UNKNOWN) {
1276                 uint pin = gpio_cfg[board_type].pcie_rst;
1277                 gpio_direction_output(pin, 0);
1278                 mdelay(50);
1279                 gpio_direction_output(pin, 1);
1280         }
1281         return 0;
1282 }
1283
1284 /*
1285  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
1286  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
1287  * properly and assert reset for 100ms.
1288  */
1289 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
1290                          unsigned short vendor, unsigned short device,
1291                          unsigned short class)
1292 {
1293         u32 dw;
1294
1295         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
1296               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
1297         if (vendor == PCI_VENDOR_ID_PLX &&
1298             (device & 0xfff0) == 0x8600 &&
1299             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
1300                 debug("configuring PLX 860X downstream PERST#\n");
1301                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
1302                 dw |= 0xaaa8; /* GPIO1-7 outputs */
1303                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
1304
1305                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
1306                 dw |= 0xfe;   /* GPIO1-7 output high */
1307                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
1308
1309                 mdelay(100);
1310         }
1311 }
1312 #endif /* CONFIG_CMD_PCI */
1313
1314 #ifdef CONFIG_SERIAL_TAG
1315 /*
1316  * called when setting up ATAGS before booting kernel
1317  * populate serialnum from the following (in order of priority):
1318  *   serial# env var
1319  *   eeprom
1320  */
1321 void get_board_serial(struct tag_serialnr *serialnr)
1322 {
1323         char *serial = getenv("serial#");
1324
1325         if (serial) {
1326                 serialnr->high = 0;
1327                 serialnr->low = simple_strtoul(serial, NULL, 10);
1328         } else if (ventana_info.model[0]) {
1329                 serialnr->high = 0;
1330                 serialnr->low = ventana_info.serial;
1331         } else {
1332                 serialnr->high = 0;
1333                 serialnr->low = 0;
1334         }
1335 }
1336 #endif
1337
1338 /*
1339  * Board Support
1340  */
1341
1342 /* called from SPL board_init_f() */
1343 int board_early_init_f(void)
1344 {
1345         setup_iomux_uart();
1346         gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1347
1348 #if defined(CONFIG_VIDEO_IPUV3)
1349         setup_display();
1350 #endif
1351         return 0;
1352 }
1353
1354 int dram_init(void)
1355 {
1356         gd->ram_size = imx_ddr_size();
1357         return 0;
1358 }
1359
1360 int board_init(void)
1361 {
1362         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
1363
1364         clrsetbits_le32(&iomuxc_regs->gpr[1],
1365                         IOMUXC_GPR1_OTG_ID_MASK,
1366                         IOMUXC_GPR1_OTG_ID_GPIO1);
1367
1368         /* address of linux boot parameters */
1369         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1370
1371 #ifdef CONFIG_CMD_NAND
1372         setup_gpmi_nand();
1373 #endif
1374 #ifdef CONFIG_MXC_SPI
1375         setup_spi();
1376 #endif
1377         if (is_cpu_type(MXC_CPU_MX6Q)) {
1378                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1379                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1380                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1381         } else {
1382                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1383                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1384                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1385         }
1386
1387 #ifdef CONFIG_CMD_SATA
1388         setup_sata();
1389 #endif
1390         /* read Gateworks EEPROM into global struct (used later) */
1391         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1392
1393         /* board-specifc GPIO iomux */
1394         SETUP_IOMUX_PADS(gw_gpio_pads);
1395         if (board_type < GW_UNKNOWN) {
1396                 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1397                 int count = gpio_cfg[board_type].num_pads;
1398
1399                 imx_iomux_v3_setup_multiple_pads(p, count);
1400         }
1401
1402         return 0;
1403 }
1404
1405 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1406 /*
1407  * called during late init (after relocation and after board_init())
1408  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1409  * EEPROM read.
1410  */
1411 int checkboard(void)
1412 {
1413         struct ventana_board_info *info = &ventana_info;
1414         unsigned char buf[4];
1415         const char *p;
1416         int quiet; /* Quiet or minimal output mode */
1417
1418         quiet = 0;
1419         p = getenv("quiet");
1420         if (p)
1421                 quiet = simple_strtol(p, NULL, 10);
1422         else
1423                 setenv("quiet", "0");
1424
1425         puts("\nGateworks Corporation Copyright 2014\n");
1426         if (info->model[0]) {
1427                 printf("Model: %s\n", info->model);
1428                 printf("MFGDate: %02x-%02x-%02x%02x\n",
1429                        info->mfgdate[0], info->mfgdate[1],
1430                        info->mfgdate[2], info->mfgdate[3]);
1431                 printf("Serial:%d\n", info->serial);
1432         } else {
1433                 puts("Invalid EEPROM - board will not function fully\n");
1434         }
1435         if (quiet)
1436                 return 0;
1437
1438         /* Display GSC firmware revision/CRC/status */
1439         gsc_info(0);
1440
1441         /* Display RTC */
1442         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1443                 printf("RTC:   %d\n",
1444                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1445         }
1446
1447         return 0;
1448 }
1449 #endif
1450
1451 #ifdef CONFIG_CMD_BMODE
1452 /*
1453  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1454  * see Table 8-11 and Table 5-9
1455  *  BOOT_CFG1[7] = 1 (boot from NAND)
1456  *  BOOT_CFG1[5] = 0 - raw NAND
1457  *  BOOT_CFG1[4] = 0 - default pad settings
1458  *  BOOT_CFG1[3:2] = 00 - devices = 1
1459  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1460  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1461  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1462  *  BOOT_CFG2[0] = 0 - Reset time 12ms
1463  */
1464 static const struct boot_mode board_boot_modes[] = {
1465         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1466         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1467         { NULL, 0 },
1468 };
1469 #endif
1470
1471 /* late init */
1472 int misc_init_r(void)
1473 {
1474         struct ventana_board_info *info = &ventana_info;
1475         unsigned char reg;
1476
1477         /* set env vars based on EEPROM data */
1478         if (ventana_info.model[0]) {
1479                 char str[16], fdt[36];
1480                 char *p;
1481                 const char *cputype = "";
1482                 int i;
1483
1484                 /*
1485                  * FDT name will be prefixed with CPU type.  Three versions
1486                  * will be created each increasingly generic and bootloader
1487                  * env scripts will try loading each from most specific to
1488                  * least.
1489                  */
1490                 if (is_cpu_type(MXC_CPU_MX6Q) ||
1491                     is_cpu_type(MXC_CPU_MX6D))
1492                         cputype = "imx6q";
1493                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1494                          is_cpu_type(MXC_CPU_MX6SOLO))
1495                         cputype = "imx6dl";
1496                 setenv("soctype", cputype);
1497                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1498                         setenv("flash_layout", "large");
1499                 else
1500                         setenv("flash_layout", "normal");
1501                 memset(str, 0, sizeof(str));
1502                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1503                         str[i] = tolower(info->model[i]);
1504                 if (!getenv("model"))
1505                         setenv("model", str);
1506                 if (!getenv("fdt_file")) {
1507                         sprintf(fdt, "%s-%s.dtb", cputype, str);
1508                         setenv("fdt_file", fdt);
1509                 }
1510                 p = strchr(str, '-');
1511                 if (p) {
1512                         *p++ = 0;
1513
1514                         setenv("model_base", str);
1515                         if (!getenv("fdt_file1")) {
1516                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1517                                 setenv("fdt_file1", fdt);
1518                         }
1519                         if (board_type != GW551x && board_type != GW552x)
1520                                 str[4] = 'x';
1521                         str[5] = 'x';
1522                         str[6] = 0;
1523                         if (!getenv("fdt_file2")) {
1524                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1525                                 setenv("fdt_file2", fdt);
1526                         }
1527                 }
1528
1529                 /* initialize env from EEPROM */
1530                 if (test_bit(EECONFIG_ETH0, info->config) &&
1531                     !getenv("ethaddr")) {
1532                         eth_setenv_enetaddr("ethaddr", info->mac0);
1533                 }
1534                 if (test_bit(EECONFIG_ETH1, info->config) &&
1535                     !getenv("eth1addr")) {
1536                         eth_setenv_enetaddr("eth1addr", info->mac1);
1537                 }
1538
1539                 /* board serial-number */
1540                 sprintf(str, "%6d", info->serial);
1541                 setenv("serial#", str);
1542
1543                 /* memory MB */
1544                 sprintf(str, "%d", (int) (gd->ram_size >> 20));
1545                 setenv("mem_mb", str);
1546         }
1547
1548
1549         /* setup baseboard specific GPIO pinmux and config */
1550         setup_board_gpio(board_type);
1551
1552 #ifdef CONFIG_CMD_BMODE
1553         add_board_boot_modes(board_boot_modes);
1554 #endif
1555
1556         /*
1557          *  The Gateworks System Controller implements a boot
1558          *  watchdog (always enabled) as a workaround for IMX6 boot related
1559          *  errata such as:
1560          *    ERR005768 - no fix scheduled
1561          *    ERR006282 - fixed in silicon r1.2
1562          *    ERR007117 - fixed in silicon r1.3
1563          *    ERR007220 - fixed in silicon r1.3
1564          *    ERR007926 - no fix scheduled
1565          *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1566          *
1567          * Disable the boot watchdog and display/clear the timeout flag if set
1568          */
1569         i2c_set_bus_num(CONFIG_I2C_GSC);
1570         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1571                 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1572                 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1573                         puts("Error: could not disable GSC Watchdog\n");
1574         } else {
1575                 puts("Error: could not disable GSC Watchdog\n");
1576         }
1577
1578         return 0;
1579 }
1580
1581 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1582
1583 static int ft_sethdmiinfmt(void *blob, char *mode)
1584 {
1585         int off;
1586
1587         if (!mode)
1588                 return -EINVAL;
1589
1590         off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
1591         if (off < 0)
1592                 return off;
1593
1594         if (0 == strcasecmp(mode, "yuv422bt656")) {
1595                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
1596                              0x00, 0x00, 0x00 };
1597                 mode = "422_ccir";
1598                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
1599                 fdt_setprop_u32(blob, off, "vidout_trc", 1);
1600                 fdt_setprop_u32(blob, off, "vidout_blc", 1);
1601                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
1602                 printf("   set HDMI input mode to %s\n", mode);
1603         } else if (0 == strcasecmp(mode, "yuv422smp")) {
1604                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
1605                              0x82, 0x81, 0x00 };
1606                 mode = "422_smp";
1607                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
1608                 fdt_setprop_u32(blob, off, "vidout_trc", 0);
1609                 fdt_setprop_u32(blob, off, "vidout_blc", 0);
1610                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
1611                 printf("   set HDMI input mode to %s\n", mode);
1612         } else {
1613                 return -EINVAL;
1614         }
1615
1616         return 0;
1617 }
1618
1619 /*
1620  * called prior to booting kernel or by 'fdt boardsetup' command
1621  *
1622  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1623  *  - mtd partitions based on mtdparts/mtdids env
1624  *  - system-serial (board serial num from EEPROM)
1625  *  - board (full model from EEPROM)
1626  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1627  */
1628 int ft_board_setup(void *blob, bd_t *bd)
1629 {
1630         struct ventana_board_info *info = &ventana_info;
1631         struct ventana_eeprom_config *cfg;
1632         struct node_info nodes[] = {
1633                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1634                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1635         };
1636         const char *model = getenv("model");
1637         const char *display = getenv("display");
1638         int i;
1639         char rev = 0;
1640
1641         /* determine board revision */
1642         for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1643                 if (ventana_info.model[i] >= 'A') {
1644                         rev = ventana_info.model[i];
1645                         break;
1646                 }
1647         }
1648
1649         if (getenv("fdt_noauto")) {
1650                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1651                 return 0;
1652         }
1653
1654         /* Update partition nodes using info from mtdparts env var */
1655         puts("   Updating MTD partitions...\n");
1656         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1657
1658         /* Update display timings from display env var */
1659         if (display) {
1660                 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1661                                       display) >= 0)
1662                         printf("   Set display timings for %s...\n", display);
1663         }
1664
1665         if (!model) {
1666                 puts("invalid board info: Leaving FDT fully enabled\n");
1667                 return 0;
1668         }
1669         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1670
1671         /* board serial number */
1672         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1673                     strlen(getenv("serial#")) + 1);
1674
1675         /* board (model contains model from device-tree) */
1676         fdt_setprop(blob, 0, "board", info->model,
1677                     strlen((const char *)info->model) + 1);
1678
1679         /* set desired digital video capture format */
1680         ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
1681
1682         /*
1683          * disable serial2 node for GW54xx for compatibility with older
1684          * 3.10.x kernel that improperly had this node enabled in the DT
1685          */
1686         if (board_type == GW54xx) {
1687                 i = fdt_path_offset(blob,
1688                                     "/soc/aips-bus@02100000/serial@021ec000");
1689                 if (i)
1690                         fdt_del_node(blob, i);
1691         }
1692
1693         /*
1694          * disable wdog1/wdog2 nodes for GW51xx below revC to work around
1695          * errata causing wdog timer to be unreliable.
1696          */
1697         if (board_type == GW51xx && rev >= 'A' && rev < 'C') {
1698                 i = fdt_path_offset(blob,
1699                                     "/soc/aips-bus@02000000/wdog@020bc000");
1700                 if (i)
1701                         fdt_status_disabled(blob, i);
1702         }
1703
1704         /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1705         else if (board_type == GW52xx && info->model[4] == '2') {
1706                 u32 handle = 0;
1707                 u32 *range = NULL;
1708
1709                 i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
1710                 if (i)
1711                         range = (u32 *)fdt_getprop(blob, i, "reset-gpio",
1712                                                    NULL);
1713
1714                 if (range) {
1715                         i = fdt_path_offset(blob,
1716                                             "/soc/aips-bus@02000000/gpio@020a4000");
1717                         if (i)
1718                                 handle = fdt_get_phandle(blob, i);
1719                         if (handle) {
1720                                 range[0] = cpu_to_fdt32(handle);
1721                                 range[1] = cpu_to_fdt32(23);
1722                         }
1723                 }
1724         }
1725
1726         /*
1727          * isolate CSI0_DATA_EN for GW551x below revB to work around
1728          * errata causing non functional digital video in (it is not hooked up)
1729          */
1730         else if (board_type == GW551x && rev == 'A') {
1731                 u32 *range = NULL;
1732                 int len;
1733                 const u32 *handle = NULL;
1734
1735                 i = fdt_node_offset_by_compatible(blob, -1,
1736                                                   "fsl,imx-tda1997x-video");
1737                 if (i)
1738                         handle = fdt_getprop(blob, i, "pinctrl-0", NULL);
1739                 if (handle)
1740                         i = fdt_node_offset_by_phandle(blob,
1741                                                        fdt32_to_cpu(*handle));
1742                 if (i)
1743                         range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len);
1744                 if (range) {
1745                         len /= sizeof(u32);
1746                         for (i = 0; i < len; i += 6) {
1747                                 u32 mux_reg = fdt32_to_cpu(range[i+0]);
1748                                 u32 conf_reg = fdt32_to_cpu(range[i+1]);
1749                                 /* mux PAD_CSI0_DATA_EN to GPIO */
1750                                 if (is_cpu_type(MXC_CPU_MX6Q) &&
1751                                     mux_reg == 0x260 && conf_reg == 0x630)
1752                                         range[i+3] = cpu_to_fdt32(0x5);
1753                                 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1754                                     mux_reg == 0x08c && conf_reg == 0x3a0)
1755                                         range[i+3] = cpu_to_fdt32(0x5);
1756                         }
1757                         fdt_setprop_inplace(blob, i, "fsl,pins", range, len);
1758                 }
1759         }
1760
1761         /*
1762          * Peripheral Config:
1763          *  remove nodes by alias path if EEPROM config tells us the
1764          *  peripheral is not loaded on the board.
1765          */
1766         if (getenv("fdt_noconfig")) {
1767                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1768                 return 0;
1769         }
1770         cfg = econfig;
1771         while (cfg->name) {
1772                 if (!test_bit(cfg->bit, info->config)) {
1773                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1774                                                cfg->dtalias : cfg->name);
1775                 }
1776                 cfg++;
1777         }
1778
1779         return 0;
1780 }
1781 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1782