board/isee/igep0033/board.c

   1 /*
   2  * Board functions for IGEP COM AQUILA based boards
   3  *
   4  * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <errno.h>
  11 #include <spl.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/omap.h>
  15 #include <asm/arch/ddr_defs.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/gpio.h>
  18 #include <asm/arch/mmc_host_def.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/io.h>
  21 #include <asm/emif.h>
  22 #include <asm/gpio.h>
  23 #include <i2c.h>
  24 #include <miiphy.h>
  25 #include <cpsw.h>
  26 #include "board.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  31
  32 #ifdef CONFIG_SPL_BUILD
  33 static const struct ddr_data ddr3_data = {
  34         .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
  35         .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
  36         .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
  37         .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
  38 };
  39
  40 static const struct cmd_control ddr3_cmd_ctrl_data = {
  41         .cmd0csratio = K4B2G1646EBIH9_RATIO,
  42         .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  43
  44         .cmd1csratio = K4B2G1646EBIH9_RATIO,
  45         .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  46
  47         .cmd2csratio = K4B2G1646EBIH9_RATIO,
  48         .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  49 };
  50
  51 static struct emif_regs ddr3_emif_reg_data = {
  52         .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
  53         .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
  54         .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
  55         .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
  56         .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
  57         .zq_config = K4B2G1646EBIH9_ZQ_CFG,
  58         .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
  59 };
  60
  61 #define OSC    (V_OSCK/1000000)
  62 const struct dpll_params dpll_ddr = {
  63                 400, OSC-1, 1, -1, -1, -1, -1};
  64
  65 const struct dpll_params *get_dpll_ddr_params(void)
  66 {
  67         return &dpll_ddr;
  68 }
  69
  70 void set_uart_mux_conf(void)
  71 {
  72         enable_uart0_pin_mux();
  73 }
  74
  75 void set_mux_conf_regs(void)
  76 {
  77         enable_board_pin_mux();
  78 }
  79
  80 void sdram_init(void)
  81 {
  82         config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
  83                    &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  84 }
  85 #endif
  86
  87 /*
  88  * Basic board specific setup.  Pinmux has been handled already.
  89  */
  90 int board_init(void)
  91 {
  92         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  93
  94         gpmc_init();
  95
  96         return 0;
  97 }
  98
  99 #if defined(CONFIG_DRIVER_TI_CPSW)
 100 static void cpsw_control(int enabled)
 101 {
 102         /* VTP can be added here */
 103
 104         return;
 105 }
 106
 107 static struct cpsw_slave_data cpsw_slaves[] = {
 108         {
 109                 .slave_reg_ofs  = 0x208,
 110                 .sliver_reg_ofs = 0xd80,
 111                 .phy_id         = 0,
 112                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 113         },
 114 };
 115
 116 static struct cpsw_platform_data cpsw_data = {
 117         .mdio_base              = CPSW_MDIO_BASE,
 118         .cpsw_base              = CPSW_BASE,
 119         .mdio_div               = 0xff,
 120         .channels               = 8,
 121         .cpdma_reg_ofs          = 0x800,
 122         .slaves                 = 1,
 123         .slave_data             = cpsw_slaves,
 124         .ale_reg_ofs            = 0xd00,
 125         .ale_entries            = 1024,
 126         .host_port_reg_ofs      = 0x108,
 127         .hw_stats_reg_ofs       = 0x900,
 128         .bd_ram_ofs             = 0x2000,
 129         .mac_control            = (1 << 5),
 130         .control                = cpsw_control,
 131         .host_port_num          = 0,
 132         .version                = CPSW_CTRL_VERSION_2,
 133 };
 134
 135 int board_eth_init(bd_t *bis)
 136 {
 137         int rv, ret = 0;
 138         uint8_t mac_addr[6];
 139         uint32_t mac_hi, mac_lo;
 140
 141         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 142                 /* try reading mac address from efuse */
 143                 mac_lo = readl(&cdev->macid0l);
 144                 mac_hi = readl(&cdev->macid0h);
 145                 mac_addr[0] = mac_hi & 0xFF;
 146                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 147                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 148                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 149                 mac_addr[4] = mac_lo & 0xFF;
 150                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 151                 if (is_valid_ether_addr(mac_addr))
 152                         eth_setenv_enetaddr("ethaddr", mac_addr);
 153         }
 154
 155         writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
 156                &cdev->miisel);
 157
 158         rv = cpsw_register(&cpsw_data);
 159         if (rv < 0)
 160                 printf("Error %d registering CPSW switch\n", rv);
 161         else
 162                 ret += rv;
 163
 164         return ret;
 165 }
 166 #endif