board/isee/igep0033/board.c

   1 /*
   2  * Board functions for IGEP COM AQUILA/CYGNUS based boards
   3  *
   4  * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <errno.h>
  11 #include <spl.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/omap.h>
  15 #include <asm/arch/ddr_defs.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/gpio.h>
  18 #include <asm/arch/mmc_host_def.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/io.h>
  21 #include <asm/emif.h>
  22 #include <asm/gpio.h>
  23 #include <i2c.h>
  24 #include <miiphy.h>
  25 #include <cpsw.h>
  26 #include "board.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  31
  32 /* MII mode defines */
  33 #define RMII_MODE_ENABLE        0x4D
  34
  35 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  36
  37 #ifdef CONFIG_SPL_BUILD
  38 static const struct ddr_data ddr3_data = {
  39         .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
  40         .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
  41         .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
  42         .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
  43         .datadldiff0 = PHY_DLL_LOCK_DIFF,
  44 };
  45
  46 static const struct cmd_control ddr3_cmd_ctrl_data = {
  47         .cmd0csratio = K4B2G1646EBIH9_RATIO,
  48         .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
  49         .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  50
  51         .cmd1csratio = K4B2G1646EBIH9_RATIO,
  52         .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
  53         .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  54
  55         .cmd2csratio = K4B2G1646EBIH9_RATIO,
  56         .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
  57         .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  58 };
  59
  60 static struct emif_regs ddr3_emif_reg_data = {
  61         .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
  62         .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
  63         .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
  64         .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
  65         .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
  66         .zq_config = K4B2G1646EBIH9_ZQ_CFG,
  67         .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
  68 };
  69 #endif
  70
  71 /*
  72  * Early system init of muxing and clocks.
  73  */
  74 void s_init(void)
  75 {
  76         /*
  77          * Save the boot parameters passed from romcode.
  78          * We cannot delay the saving further than this,
  79          * to prevent overwrites.
  80          */
  81 #ifdef CONFIG_SPL_BUILD
  82         save_omap_boot_params();
  83 #endif
  84
  85         /* WDT1 is already running when the bootloader gets control
  86          * Disable it to avoid "random" resets
  87          */
  88         writel(0xAAAA, &wdtimer->wdtwspr);
  89         while (readl(&wdtimer->wdtwwps) != 0x0)
  90                 ;
  91         writel(0x5555, &wdtimer->wdtwspr);
  92         while (readl(&wdtimer->wdtwwps) != 0x0)
  93                 ;
  94
  95 #ifdef CONFIG_SPL_BUILD
  96         /* Setup the PLLs and the clocks for the peripherals */
  97         pll_init();
  98
  99         /* Enable RTC32K clock */
 100         rtc32k_enable();
 101
 102         enable_uart0_pin_mux();
 103
 104         uart_soft_reset();
 105         gd = &gdata;
 106
 107         preloader_console_init();
 108
 109         /* Configure board pin mux */
 110         enable_board_pin_mux();
 111
 112         config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
 113                    &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 114 #endif
 115 }
 116
 117 /*
 118  * Basic board specific setup.  Pinmux has been handled already.
 119  */
 120 int board_init(void)
 121 {
 122         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 123
 124         gpmc_init();
 125
 126         return 0;
 127 }
 128
 129 #if defined(CONFIG_DRIVER_TI_CPSW)
 130 static void cpsw_control(int enabled)
 131 {
 132         /* VTP can be added here */
 133
 134         return;
 135 }
 136
 137 static struct cpsw_slave_data cpsw_slaves[] = {
 138         {
 139                 .slave_reg_ofs  = 0x208,
 140                 .sliver_reg_ofs = 0xd80,
 141                 .phy_id         = 0,
 142                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 143         },
 144 };
 145
 146 static struct cpsw_platform_data cpsw_data = {
 147         .mdio_base              = CPSW_MDIO_BASE,
 148         .cpsw_base              = CPSW_BASE,
 149         .mdio_div               = 0xff,
 150         .channels               = 8,
 151         .cpdma_reg_ofs          = 0x800,
 152         .slaves                 = 1,
 153         .slave_data             = cpsw_slaves,
 154         .ale_reg_ofs            = 0xd00,
 155         .ale_entries            = 1024,
 156         .host_port_reg_ofs      = 0x108,
 157         .hw_stats_reg_ofs       = 0x900,
 158         .mac_control            = (1 << 5),
 159         .control                = cpsw_control,
 160         .host_port_num          = 0,
 161         .version                = CPSW_CTRL_VERSION_2,
 162 };
 163
 164 int board_eth_init(bd_t *bis)
 165 {
 166         int rv, ret = 0;
 167         uint8_t mac_addr[6];
 168         uint32_t mac_hi, mac_lo;
 169
 170         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 171                 /* try reading mac address from efuse */
 172                 mac_lo = readl(&cdev->macid0l);
 173                 mac_hi = readl(&cdev->macid0h);
 174                 mac_addr[0] = mac_hi & 0xFF;
 175                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 176                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 177                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 178                 mac_addr[4] = mac_lo & 0xFF;
 179                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 180                 if (is_valid_ether_addr(mac_addr))
 181                         eth_setenv_enetaddr("ethaddr", mac_addr);
 182         }
 183
 184         writel(RMII_MODE_ENABLE, &cdev->miisel);
 185
 186         rv = cpsw_register(&cpsw_data);
 187         if (rv < 0)
 188                 printf("Error %d registering CPSW switch\n", rv);
 189         else
 190                 ret += rv;
 191
 192         return ret;
 193 }
 194 #endif
 195