2 * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/regs-pinctrl.h>
26 #include <asm/arch/pinctrl.h>
27 #include <asm/arch/regs-clkctrl.h>
28 #include <asm/arch/regs-ocotp.h>
29 #include <asm/errno.h>
32 #include <imx_ssp_mmc.h>
34 /* This should be removed after it's added into mach-types.h */
36 static const int mach_type = MACH_TYPE_TX28;
38 DECLARE_GLOBAL_DATA_PTR;
40 #ifdef CONFIG_IMX_SSP_MMC
43 static struct pin_desc mmc0_pins_desc[] = {
44 { PINID_SSP0_DATA0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
45 { PINID_SSP0_DATA1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
46 { PINID_SSP0_DATA2, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
47 { PINID_SSP0_DATA3, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
48 { PINID_SSP0_DATA4, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
49 { PINID_SSP0_DATA5, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
50 { PINID_SSP0_DATA6, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
51 { PINID_SSP0_DATA7, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
52 { PINID_SSP0_CMD, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
53 { PINID_SSP0_DETECT, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
54 { PINID_SSP0_SCK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
57 static struct pin_desc mmc1_pins_desc[] = {
58 { PINID_GPMI_D00, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
59 { PINID_GPMI_D01, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
60 { PINID_GPMI_D02, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
61 { PINID_GPMI_D03, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
62 { PINID_GPMI_D04, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
63 { PINID_GPMI_D05, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
64 { PINID_GPMI_D06, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
65 { PINID_GPMI_D07, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
66 { PINID_GPMI_RDY1, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
67 { PINID_GPMI_RDY0, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
68 { PINID_GPMI_WRN, PIN_FUN2, PAD_8MA, PAD_3V3, 1 }
71 static struct pin_group mmc0_pins = {
72 .pins = mmc0_pins_desc,
73 .nr_pins = ARRAY_SIZE(mmc0_pins_desc)
76 static struct pin_group mmc1_pins = {
77 .pins = mmc1_pins_desc,
78 .nr_pins = ARRAY_SIZE(mmc1_pins_desc)
81 struct imx_ssp_mmc_cfg ssp_mmc_cfg[2] = {
82 {REGS_SSP0_BASE, HW_CLKCTRL_SSP0, BM_CLKCTRL_CLKSEQ_BYPASS_SSP0},
83 {REGS_SSP1_BASE, HW_CLKCTRL_SSP1, BM_CLKCTRL_CLKSEQ_BYPASS_SSP1},
88 static struct pin_desc enet_pins_desc[] = {
89 { PINID_ENET0_MDC, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
90 { PINID_ENET0_MDIO, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
91 { PINID_ENET0_RX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
92 { PINID_ENET0_RXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
93 { PINID_ENET0_RXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
94 { PINID_ENET0_TX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
95 { PINID_ENET0_TXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
96 { PINID_ENET0_TXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
97 { PINID_ENET_CLK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }
100 static struct pin_group enet_pins = {
101 .pins = enet_pins_desc,
102 .nr_pins = ARRAY_SIZE(enet_pins_desc),
105 static struct pin_desc duart_pins_desc[] = {
106 { PINID_PWM0, PIN_GPIO, PAD_8MA, PAD_3V3, 1 },
107 { PINID_PWM1, PIN_GPIO, PAD_8MA, PAD_3V3, 1 },
108 { PINID_I2C0_SCL, PIN_GPIO, PAD_8MA, PAD_3V3, 1 },
109 { PINID_I2C0_SDA, PIN_GPIO, PAD_8MA, PAD_3V3, 1 },
111 { PINID_AUART0_RTS, PIN_FUN3, PAD_8MA, PAD_3V3, 1 },
112 { PINID_AUART0_CTS, PIN_FUN3, PAD_8MA, PAD_3V3, 1 },
113 { PINID_AUART0_TX, PIN_FUN3, PAD_8MA, PAD_3V3, 1 },
114 { PINID_AUART0_RX, PIN_FUN3, PAD_8MA, PAD_3V3, 1 },
117 static struct pin_group duart_pins = {
118 .pins = duart_pins_desc,
119 .nr_pins = ARRAY_SIZE(duart_pins_desc),
125 static void duart_init(void)
127 pin_set_group(&duart_pins);
132 gd->bd->bi_arch_number = mach_type;
134 /* Address of boot parameters */
135 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
143 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
144 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
149 #ifdef CONFIG_IMX_SSP_MMC
151 #ifdef CONFIG_DYNAMIC_MMC_DEVNO
152 int get_mmc_env_devno(void)
154 unsigned long global_boot_mode;
156 global_boot_mode = REG_RD_ADDR(GLOBAL_BOOT_MODE_ADDR);
157 return ((global_boot_mode & 0xf) == BOOT_MODE_SD1) ? 1 : 0;
161 #define PINID_SSP0_GPIO_WP PINID_SSP1_SCK
162 #define PINID_SSP1_GPIO_WP PINID_GPMI_RESETN
164 u32 ssp_mmc_is_wp(struct mmc *mmc)
169 int ssp_mmc_gpio_init(bd_t *bis)
174 for (index = 0; index < CONFIG_SYS_SSP_MMC_NUM; index++) {
177 /* Set up MMC pins */
178 pin_set_group(&mmc0_pins);
182 /* Set up MMC pins */
183 pin_set_group(&mmc1_pins);
187 printf("Warning: more ssp mmc controllers configured(%d) than supported by the board(2)\n",
188 CONFIG_SYS_SSP_MMC_NUM);
191 status |= imx_ssp_mmc_initialize(bis, &ssp_mmc_cfg[index]);
197 int board_mmc_init(bd_t *bis)
199 if (!ssp_mmc_gpio_init(bis))
207 #if defined(CONFIG_MXC_FEC) && defined(CONFIG_GET_FEC_MAC_ADDR_FROM_IIM)
208 int fec_get_mac_addr(unsigned char *mac)
213 /* set this bit to open the OTP banks for reading */
214 REG_WR(REGS_OCOTP_BASE, HW_OCOTP_CTRL_SET,
215 BM_OCOTP_CTRL_RD_BANK_OPEN);
217 /* wait until OTP contents are readable */
218 while (BM_OCOTP_CTRL_BUSY & REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CTRL)) {
224 val = REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CUSTn(0));
225 mac[0] = (val >> 24) & 0xFF;
226 mac[1] = (val >> 16) & 0xFF;
227 mac[2] = (val >> 8) & 0xFF;
228 mac[3] = (val >> 0) & 0xFF;
229 val = REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CUSTn(1));
230 mac[4] = (val >> 24) & 0xFF;
231 mac[5] = (val >> 16) & 0xFF;
237 void enet_board_init(void)
239 /* Set up ENET pins */
240 pin_set_group(&enet_pins);
242 /* Power on the external phy */
243 pin_gpio_set(PINID_PWM4, 1);
244 pin_gpio_direction(PINID_PWM4, 1);
245 pin_set_type(PINID_PWM4, PIN_GPIO);
247 /* Reset the external phy */
248 pin_gpio_set(PINID_ENET0_RX_CLK, 0);
249 pin_gpio_direction(PINID_ENET0_RX_CLK, 1);
250 pin_set_type(PINID_ENET0_RX_CLK, PIN_GPIO);
252 pin_gpio_set(PINID_ENET0_RX_CLK, 1);
257 printf("Board: Ka-Ro TX28\n");