2 * Copyright (C) 2012-2013 Lothar Waßmann <LW@KARO-electronics.de>
5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
24 #include <fdt_support.h>
27 #include <linux/mtd/nand.h>
30 #include <asm/cache.h>
32 #include <asm/arch/cpu.h>
33 #include <asm/arch/hardware.h>
34 #include <asm/arch/mmc_host_def.h>
35 #include <asm/arch/mux.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/arch/clock.h>
39 #include <asm/arch/da8xx-fb.h>
41 #include "../common/karo.h"
43 DECLARE_GLOBAL_DATA_PTR;
45 #define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
46 #define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
47 #define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
48 #define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
49 #define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
50 #define TX48_MMC_CD_GPIO AM33XX_GPIO_NR(3, 15)
52 #define NO_OF_MAC_ADDR 1
62 #define PAD_CTRL_BASE 0x800
63 #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
67 * Configure the pin mux for the module
69 static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
74 for (i = 0; i < num_pins; i++)
75 writel(pin_mux[i].val, CTRL_BASE + pin_mux[i].reg_offset);
78 #define PRM_RSTST_GLOBAL_COLD_RST (1 << 0)
79 #define PRM_RSTST_GLOBAL_WARM_SW_RST (1 << 1)
80 #define PRM_RSTST_WDT1_RST (1 << 4)
81 #define PRM_RSTST_EXTERNAL_WARM_RST (1 << 5)
82 #define PRM_RSTST_ICEPICK_RST (1 << 9)
84 static u32 prm_rstst __attribute__((section(".data")));
87 * Basic board specific setup
89 static const struct pin_mux tx48_pads[] = {
90 { OFFSET(i2c0_sda), MODE(7) | RXACTIVE | PULLUDEN | PULLUP_EN, },
91 { OFFSET(i2c0_scl), MODE(7) | RXACTIVE | PULLUDEN | PULLUP_EN, },
92 { OFFSET(emu1), MODE(7), }, /* ETH PHY Reset */
95 static const struct pin_mux tx48_i2c_pads[] = {
96 { OFFSET(i2c0_sda), MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, },
97 { OFFSET(i2c0_scl), MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, },
100 static const struct gpio tx48_gpios[] = {
101 { AM33XX_GPIO_NR(3, 5), GPIOFLAG_INPUT, "I2C1_SDA", },
102 { AM33XX_GPIO_NR(3, 6), GPIOFLAG_INPUT, "I2C1_SCL", },
103 { AM33XX_GPIO_NR(3, 8), GPIOFLAG_OUTPUT_INIT_LOW, "ETH_PHY_RESET", },
106 static const struct pin_mux stk5_pads[] = {
108 { OFFSET(gpmc_a10), MODE(7) | PULLUDEN, },
110 { OFFSET(gpmc_a3), MODE(7) | PULLUDEN, },
111 /* LCD POWER_ENABLE */
112 { OFFSET(gpmc_a6), MODE(7) | PULLUDEN, },
113 /* LCD Backlight (PWM) */
114 { OFFSET(mcasp0_aclkx), MODE(7) | PULLUDEN, },
116 { OFFSET(mcasp0_fsx), MODE(7) | PULLUDEN | PULLUP_EN, },
119 static const struct gpio stk5_gpios[] = {
120 { TX48_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
121 { TX48_MMC_CD_GPIO, GPIOFLAG_INPUT, "MMC0 CD", },
124 static const struct pin_mux stk5_lcd_pads[] = {
126 { OFFSET(lcd_data0), MODE(0) | PULLUDEN, },
127 { OFFSET(lcd_data1), MODE(0) | PULLUDEN, },
128 { OFFSET(lcd_data2), MODE(0) | PULLUDEN, },
129 { OFFSET(lcd_data3), MODE(0) | PULLUDEN, },
130 { OFFSET(lcd_data4), MODE(0) | PULLUDEN, },
131 { OFFSET(lcd_data5), MODE(0) | PULLUDEN, },
132 { OFFSET(lcd_data6), MODE(0) | PULLUDEN, },
133 { OFFSET(lcd_data7), MODE(0) | PULLUDEN, },
134 { OFFSET(lcd_data8), MODE(0) | PULLUDEN, },
135 { OFFSET(lcd_data9), MODE(0) | PULLUDEN, },
136 { OFFSET(lcd_data10), MODE(0) | PULLUDEN, },
137 { OFFSET(lcd_data11), MODE(0) | PULLUDEN, },
138 { OFFSET(lcd_data12), MODE(0) | PULLUDEN, },
139 { OFFSET(lcd_data13), MODE(0) | PULLUDEN, },
140 { OFFSET(lcd_data14), MODE(0) | PULLUDEN, },
141 { OFFSET(lcd_data15), MODE(0) | PULLUDEN, },
142 /* LCD control signals */
143 { OFFSET(lcd_hsync), MODE(0) | PULLUDEN, },
144 { OFFSET(lcd_vsync), MODE(0) | PULLUDEN, },
145 { OFFSET(lcd_pclk), MODE(0) | PULLUDEN, },
146 { OFFSET(lcd_ac_bias_en), MODE(0) | PULLUDEN, },
149 static const struct gpio stk5_lcd_gpios[] = {
150 { AM33XX_GPIO_NR(1, 19), GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
151 { AM33XX_GPIO_NR(1, 22), GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
152 { AM33XX_GPIO_NR(3, 14), GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
155 static const struct pin_mux stk5v5_pads[] = {
156 /* CAN transceiver control */
157 { OFFSET(gpmc_ad8), MODE(7) | PULLUDEN, },
160 static const struct gpio stk5v5_gpios[] = {
161 { AM33XX_GPIO_NR(0, 22), GPIOFLAG_OUTPUT_INIT_HIGH, "CAN XCVR", },
165 vidinfo_t panel_info = {
166 /* set to max. size supported by SoC */
170 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
173 static struct lcd_ctrl_config lcd_cfg = {
177 #define FB_SYNC_OE_LOW_ACT (1 << 31)
178 #define FB_SYNC_CLK_LAT_FALL (1 << 30)
180 static struct fb_videomode tx48_fb_modes[] = {
182 /* Standard VGA timing */
187 .pixclock = KHZ2PICOS(25175),
194 .sync = FB_SYNC_CLK_LAT_FALL,
197 /* Emerging ETV570 640 x 480 display. Syncs low active,
198 * DE high active, 115.2 mm x 86.4 mm display area
199 * VGA compatible timing
205 .pixclock = KHZ2PICOS(25175),
212 .sync = FB_SYNC_CLK_LAT_FALL,
215 /* Emerging ET0350G0DH6 320 x 240 display.
216 * 70.08 mm x 52.56 mm display area.
222 .pixclock = KHZ2PICOS(6500),
223 .left_margin = 68 - 34,
226 .upper_margin = 18 - 3,
229 .sync = FB_SYNC_CLK_LAT_FALL,
232 /* Emerging ET0430G0DH6 480 x 272 display.
233 * 95.04 mm x 53.856 mm display area.
239 .pixclock = KHZ2PICOS(9000),
248 /* Emerging ET0500G0DH6 800 x 480 display.
249 * 109.6 mm x 66.4 mm display area.
255 .pixclock = KHZ2PICOS(33260),
256 .left_margin = 216 - 128,
258 .right_margin = 1056 - 800 - 216,
259 .upper_margin = 35 - 2,
261 .lower_margin = 525 - 480 - 35,
262 .sync = FB_SYNC_CLK_LAT_FALL,
265 /* Emerging ETQ570G0DH6 320 x 240 display.
266 * 115.2 mm x 86.4 mm display area.
272 .pixclock = KHZ2PICOS(6400),
276 .upper_margin = 16, /* 15 according to datasheet */
277 .vsync_len = 3, /* TVP -> 1>x>5 */
278 .lower_margin = 4, /* 4.5 according to datasheet */
279 .sync = FB_SYNC_CLK_LAT_FALL,
282 /* Emerging ET0700G0DH6 800 x 480 display.
283 * 152.4 mm x 91.44 mm display area.
289 .pixclock = KHZ2PICOS(33260),
290 .left_margin = 216 - 128,
292 .right_margin = 1056 - 800 - 216,
293 .upper_margin = 35 - 2,
295 .lower_margin = 525 - 480 - 35,
296 .sync = FB_SYNC_CLK_LAT_FALL,
299 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
307 .sync = FB_SYNC_CLK_LAT_FALL,
311 void *lcd_base; /* Start of framebuffer memory */
312 void *lcd_console_address; /* Start of console buffer */
320 static int lcd_enabled = 1;
321 static int lcd_bl_polarity;
323 static int lcd_backlight_polarity(void)
325 return lcd_bl_polarity;
328 void lcd_initcolregs(void)
332 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
336 void lcd_enable(void)
339 * global variable from common/lcd.c
340 * Set to 0 here to prevent messages from going to LCD
341 * rather than serial console
346 karo_load_splashimage(1);
348 debug("Switching LCD on\n");
349 gpio_set_value(TX48_LCD_PWR_GPIO, 1);
351 gpio_set_value(TX48_LCD_RST_GPIO, 1);
353 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO,
354 lcd_backlight_polarity());
358 void lcd_disable(void)
361 printf("Disabling LCD\n");
367 static void tx48_lcd_panel_setup(struct da8xx_panel *p,
368 struct fb_videomode *fb)
370 p->pxl_clk = PICOS2KHZ(fb->pixclock) * 1000;
373 p->hbp = fb->left_margin;
374 p->hsw = fb->hsync_len;
375 p->hfp = fb->right_margin;
377 p->height = fb->yres;
378 p->vbp = fb->upper_margin;
379 p->vsw = fb->vsync_len;
380 p->vfp = fb->lower_margin;
382 p->invert_pxl_clk = !!(fb->sync & FB_SYNC_CLK_LAT_FALL);
385 void lcd_panel_disable(void)
388 debug("Switching LCD off\n");
389 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO,
390 !lcd_backlight_polarity());
391 gpio_set_value(TX48_LCD_PWR_GPIO, 0);
392 gpio_set_value(TX48_LCD_RST_GPIO, 0);
396 void lcd_ctrl_init(void *lcdbase)
398 int color_depth = 24;
399 const char *video_mode = karo_get_vmode(getenv("video_mode"));
403 struct fb_videomode *p = &tx48_fb_modes[0];
404 struct fb_videomode fb_mode;
405 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
408 debug("LCD disabled\n");
412 if (had_ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
413 debug("Disabling LCD\n");
415 setenv("splashimage", NULL);
421 if (video_mode == NULL) {
422 debug("Disabling LCD\n");
427 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
429 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
431 debug("Using video mode from FDT\n");
433 if (fb_mode.xres > panel_info.vl_col ||
434 fb_mode.yres > panel_info.vl_row) {
435 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
436 fb_mode.xres, fb_mode.yres,
437 panel_info.vl_col, panel_info.vl_row);
443 debug("Trying compiled-in video modes\n");
444 while (p->name != NULL) {
445 if (strcmp(p->name, vm) == 0) {
446 debug("Using video mode: '%s'\n", p->name);
453 debug("Trying to decode video_mode: '%s'\n", vm);
454 while (*vm != '\0') {
455 if (*vm >= '0' && *vm <= '9') {
458 val = simple_strtoul(vm, &end, 0);
461 if (val > panel_info.vl_col)
462 val = panel_info.vl_col;
464 panel_info.vl_col = val;
466 } else if (!yres_set) {
467 if (val > panel_info.vl_row)
468 val = panel_info.vl_row;
470 panel_info.vl_row = val;
472 } else if (!bpp_set) {
481 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
482 end - vm, vm, color_depth);
485 } else if (!refresh_set) {
512 if (p->xres == 0 || p->yres == 0) {
513 printf("Invalid video mode: %s\n", getenv("video_mode"));
515 printf("Supported video modes are:");
516 for (p = &tx48_fb_modes[0]; p->name != NULL; p++) {
517 printf(" %s", p->name);
522 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
523 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
524 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
528 panel_info.vl_col = p->xres;
529 panel_info.vl_row = p->yres;
531 switch (color_depth) {
533 panel_info.vl_bpix = LCD_COLOR8;
536 panel_info.vl_bpix = LCD_COLOR16;
539 panel_info.vl_bpix = LCD_COLOR32;
542 p->pixclock = KHZ2PICOS(refresh *
543 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
544 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
546 debug("Pixel clock set to %lu.%03lu MHz\n",
547 PICOS2KHZ(p->pixclock) / 1000,
548 PICOS2KHZ(p->pixclock) % 1000);
553 debug("Creating new display-timing node from '%s'\n",
555 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
557 printf("Failed to create new display-timing node from '%s': %d\n",
561 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
562 tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
564 if (karo_load_splashimage(0) == 0) {
565 struct da8xx_panel da8xx_panel = { };
567 debug("Initializing FB driver\n");
568 tx48_lcd_panel_setup(&da8xx_panel, p);
569 da8xx_video_init(&da8xx_panel, &lcd_cfg, color_depth);
571 debug("Initializing LCD controller\n");
574 debug("Skipping initialization of LCD controller\n");
578 #define lcd_enabled 0
579 #endif /* CONFIG_LCD */
581 static void stk5_board_init(void)
583 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
584 tx48_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads));
587 static void stk5v3_board_init(void)
592 static void stk5v5_board_init(void)
596 gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios));
597 tx48_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads));
600 /* called with default environment! */
605 /* mach type passed to kernel */
606 #ifdef CONFIG_OF_LIBFDT
607 gd->bd->bi_arch_number = -1;
609 /* address of boot parameters */
610 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
612 if (ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
613 if (prm_rstst & PRM_RSTST_WDT1_RST)
614 printf("WDOG RESET detected\n");
616 printf("<CTRL-C> detected; safeboot enabled\n");
619 gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios));
620 tx48_set_pin_mux(tx48_pads, ARRAY_SIZE(tx48_pads));
622 for (i = 0; i < ARRAY_SIZE(tx48_gpios); i++) {
623 int gpio = tx48_gpios[i].gpio;
625 if (gpio_get_value(gpio) == 0)
626 gpio_direction_output(gpio, 1);
629 tx48_set_pin_mux(tx48_pads, ARRAY_SIZE(tx48_i2c_pads));
633 static void show_reset_cause(u32 prm_rstst)
635 const char *dlm = "";
637 printf("RESET cause: ");
638 if (prm_rstst & PRM_RSTST_GLOBAL_COLD_RST) {
639 printf("%sPOR", dlm);
642 if (prm_rstst & PRM_RSTST_GLOBAL_WARM_SW_RST) {
646 if (prm_rstst & PRM_RSTST_WDT1_RST) {
647 printf("%sWATCHDOG", dlm);
650 if (prm_rstst & PRM_RSTST_EXTERNAL_WARM_RST) {
651 printf("%sWARM", dlm);
654 if (prm_rstst & PRM_RSTST_ICEPICK_RST) {
655 printf("%sJTAG", dlm);
664 /* called with default environment! */
667 prm_rstst = readl(PRM_RSTST);
668 show_reset_cause(prm_rstst);
670 printf("Board: Ka-Ro TX48-7020\n");
676 static void tx48_set_cpu_clock(void)
678 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
679 unsigned long act_cpu_clk;
681 if (cpu_clk == 0 || cpu_clk == mpu_clk_rate() / 1000000)
684 if (had_ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
685 printf("%s detected; skipping cpu clock change\n",
686 (prm_rstst & PRM_RSTST_WDT1_RST) ?
687 "WDOG RESET" : "<CTRL-C>");
691 mpu_pll_config_val(cpu_clk);
693 act_cpu_clk = mpu_clk_rate();
694 if (cpu_clk * 1000000 != act_cpu_clk) {
695 printf("Failed to set CPU clock to %lu MHz; using %lu.%03lu MHz instead\n",
696 cpu_clk, act_cpu_clk / 1000000,
697 act_cpu_clk / 1000 % 1000);
699 printf("CPU clock set to %lu.%03lu MHz\n",
700 act_cpu_clk / 1000000, act_cpu_clk / 1000 % 1000);
704 static void tx48_init_mac(void)
706 uint8_t mac_addr[ETH_ALEN];
707 uint32_t mac_hi, mac_lo;
709 /* try reading mac address from efuse */
710 mac_lo = __raw_readl(MAC_ID0_LO);
711 mac_hi = __raw_readl(MAC_ID0_HI);
713 mac_addr[0] = mac_hi & 0xFF;
714 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
715 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
716 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
717 mac_addr[4] = mac_lo & 0xFF;
718 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
720 if (!is_valid_ethaddr(mac_addr)) {
721 printf("No valid MAC address programmed\n");
724 printf("MAC addr from fuse: %pM\n", mac_addr);
725 eth_setenv_enetaddr("ethaddr", mac_addr);
728 /* called with environment from NAND or MMC */
729 int board_late_init(void)
732 const char *baseboard;
736 tx48_set_cpu_clock();
739 setenv_ulong("safeboot", 1);
740 else if (prm_rstst & PRM_RSTST_WDT1_RST)
741 setenv_ulong("wdreset", 1);
745 baseboard = getenv("baseboard");
749 if (strncmp(baseboard, "stk5", 4) == 0) {
750 printf("Baseboard: %s\n", baseboard);
751 if ((strlen(baseboard) == 4) ||
752 strcmp(baseboard, "stk5-v3") == 0) {
754 } else if (strcmp(baseboard, "stk5-v5") == 0) {
757 printf("WARNING: Unsupported STK5 board rev.: %s\n",
761 printf("WARNING: Unsupported baseboard: '%s'\n",
772 #ifdef CONFIG_DRIVER_TI_CPSW
773 static void tx48_phy_init(void)
775 debug("%s: Resetting ethernet PHY\n", __func__);
777 gpio_direction_output(TX48_ETH_PHY_RST_GPIO, 0);
782 gpio_set_value(TX48_ETH_PHY_RST_GPIO, 1);
784 /* Wait for PHY internal POR signal to deassert */
788 static void cpsw_control(int enabled)
790 /* nothing for now */
791 /* TODO : VTP was here before */
794 static struct cpsw_slave_data cpsw_slaves[] = {
796 .slave_reg_ofs = 0x208,
797 .sliver_reg_ofs = 0xd80,
799 .phy_if = PHY_INTERFACE_MODE_RMII,
805 /* Nothing to be done here */
808 static struct cpsw_platform_data cpsw_data = {
809 .mdio_base = CPSW_MDIO_BASE,
810 .cpsw_base = CPSW_BASE,
813 .cpdma_reg_ofs = 0x800,
814 .slaves = ARRAY_SIZE(cpsw_slaves),
815 .slave_data = cpsw_slaves,
816 .ale_reg_ofs = 0xd00,
818 .host_port_reg_ofs = 0x108,
819 .hw_stats_reg_ofs = 0x900,
820 .mac_control = (1 << 5) /* MIIEN */,
821 .control = cpsw_control,
823 .version = CPSW_CTRL_VERSION_2,
826 int board_eth_init(bd_t *bis)
828 __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL);
830 return cpsw_register(&cpsw_data);
832 #endif /* CONFIG_DRIVER_TI_CPSW */
834 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
835 int cpu_mmc_init(bd_t *bis)
837 return omap_mmc_init(1, 0, 0, TX48_MMC_CD_GPIO, -1);
841 void tx48_disable_watchdog(void)
843 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
845 while (readl(&wdtimer->wdtwwps) & (1 << 4))
847 writel(0xaaaa, &wdtimer->wdtwspr);
848 while (readl(&wdtimer->wdtwwps) & (1 << 4))
850 writel(0x5555, &wdtimer->wdtwspr);
859 void show_activity(int arg)
861 static int led_state = LED_STATE_INIT;
864 if (led_state == LED_STATE_INIT) {
866 gpio_set_value(TX48_LED_GPIO, 1);
867 led_state = LED_STATE_ON;
869 if (get_timer(last) > CONFIG_SYS_HZ) {
871 if (led_state == LED_STATE_ON) {
872 gpio_set_value(TX48_LED_GPIO, 0);
874 gpio_set_value(TX48_LED_GPIO, 1);
876 led_state = 1 - led_state;
881 #ifdef CONFIG_OF_BOARD_SETUP
882 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
883 #include <jffs2/jffs2.h>
884 #include <mtd_node.h>
885 static struct node_info nodes[] = {
886 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
887 { "ti,am3352-gpmc", MTD_DEV_TYPE_NAND, },
891 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
892 #endif /* CONFIG_FDT_FIXUP_PARTITIONS */
894 static const char *tx48_touchpanels[] = {
900 int ft_board_setup(void *blob, bd_t *bd)
902 const char *baseboard = getenv("baseboard");
903 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
904 const char *video_mode = karo_get_vmode(getenv("video_mode"));
907 ret = fdt_increase_size(blob, 4096);
909 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
912 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
914 karo_fdt_fixup_touchpanel(blob, tx48_touchpanels,
915 ARRAY_SIZE(tx48_touchpanels));
916 karo_fdt_fixup_usb_otg(blob, "usb0", "phys", "vcc-supply");
917 karo_fdt_fixup_flexcan(blob, stk5_v5);
919 karo_fdt_update_fb_mode(blob, video_mode);
921 tx48_disable_watchdog();
923 if (get_cpu_rev() == 0) {
924 karo_fdt_del_prop(blob, "lltc,ltc3589-2", 0x34, "interrupts");
925 karo_fdt_del_prop(blob, "lltc,ltc3589-2", 0x34,
931 #endif /* CONFIG_OF_BOARD_SETUP */