2 * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
23 #include <fdt_support.h>
27 #include <fsl_esdhc.h>
34 #include <asm/arch/iomux-mx51.h>
35 #include <asm/arch/clock.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/crm_regs.h>
38 #include <asm/arch/sys_proto.h>
40 #include "../common/karo.h"
42 //#define IMX_GPIO_NR(b, o) ((((b) - 1) << 5) | (o))
44 #define TX51_FEC_RST_GPIO IMX_GPIO_NR(2, 14)
45 #define TX51_FEC_PWR_GPIO IMX_GPIO_NR(1, 3)
46 #define TX51_FEC_INT_GPIO IMX_GPIO_NR(3, 18)
47 #define TX51_LED_GPIO IMX_GPIO_NR(4, 10)
49 #define TX51_LCD_PWR_GPIO IMX_GPIO_NR(4, 14)
50 #define TX51_LCD_RST_GPIO IMX_GPIO_NR(4, 13)
51 #define TX51_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 2)
53 #define TX51_RESET_OUT_GPIO IMX_GPIO_NR(2, 15)
55 DECLARE_GLOBAL_DATA_PTR;
57 #define IOMUX_SION IOMUX_PAD(0, 0, MUX_CONFIG_SION, 0, 0, 0)
59 #define FEC_PAD_CTRL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
61 #define FEC_PAD_CTRL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
62 #define GPIO_PAD_CTRL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
64 static iomux_v3_cfg_t tx51_pads[] = {
65 /* NAND flash pads are set up in lowlevel_init.S */
68 MX51_PAD_EIM_A21__GPIO2_15 | GPIO_PAD_CTRL,
71 #if CONFIG_MXC_UART_BASE == UART1_BASE
72 MX51_PAD_UART1_RXD__UART1_RXD,
73 MX51_PAD_UART1_TXD__UART1_TXD,
74 MX51_PAD_UART1_RTS__UART1_RTS,
75 MX51_PAD_UART1_CTS__UART1_CTS,
77 #if CONFIG_MXC_UART_BASE == UART2_BASE
78 MX51_PAD_UART2_RXD__UART2_RXD,
79 MX51_PAD_UART2_TXD__UART2_TXD,
80 MX51_PAD_EIM_D26__UART2_RTS,
81 MX51_PAD_EIM_D25__UART2_CTS,
83 #if CONFIG_MXC_UART_BASE == UART3_BASE
84 MX51_PAD_UART3_RXD__UART3_RXD,
85 MX51_PAD_UART3_TXD__UART3_TXD,
86 MX51_PAD_EIM_D18__UART3_RTS,
87 MX51_PAD_EIM_D17__UART3_CTS,
90 MX51_PAD_I2C1_DAT__GPIO4_17 | IOMUX_SION,
91 MX51_PAD_I2C1_CLK__GPIO4_16 | IOMUX_SION,
93 /* FEC PHY GPIO functions */
94 MX51_PAD_GPIO1_3__GPIO1_3 | GPIO_PAD_CTRL, /* PHY POWER */
95 MX51_PAD_EIM_A20__GPIO2_14 | GPIO_PAD_CTRL, /* PHY RESET */
96 MX51_PAD_NANDF_CS2__GPIO3_18 | GPIO_PAD_CTRL, /* PHY INT */
99 MX51_PAD_NANDF_CS3__FEC_MDC | FEC_PAD_CTRL,
100 MX51_PAD_EIM_EB2__FEC_MDIO | FEC_PAD_CTRL,
101 MX51_PAD_NANDF_D11__FEC_RX_DV | FEC_PAD_CTRL2,
102 MX51_PAD_EIM_CS4__FEC_RX_ER | FEC_PAD_CTRL2,
103 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | FEC_PAD_CTRL2,
104 MX51_PAD_NANDF_CS7__FEC_TX_EN | FEC_PAD_CTRL,
105 MX51_PAD_NANDF_D8__FEC_TDATA0 | FEC_PAD_CTRL,
106 MX51_PAD_NANDF_CS4__FEC_TDATA1 | FEC_PAD_CTRL,
107 MX51_PAD_NANDF_CS5__FEC_TDATA2 | FEC_PAD_CTRL,
108 MX51_PAD_NANDF_CS6__FEC_TDATA3 | FEC_PAD_CTRL,
110 /* strap pins for PHY configuration */
111 MX51_PAD_NANDF_RB3__GPIO3_11 | GPIO_PAD_CTRL, /* RX_CLK/REGOFF */
112 MX51_PAD_NANDF_D9__GPIO3_31 | GPIO_PAD_CTRL, /* RXD0/Mode0 */
113 MX51_PAD_EIM_EB3__GPIO2_23 | GPIO_PAD_CTRL, /* RXD1/Mode1 */
114 MX51_PAD_EIM_CS2__GPIO2_27 | GPIO_PAD_CTRL, /* RXD2/Mode2 */
115 MX51_PAD_EIM_CS3__GPIO2_28 | GPIO_PAD_CTRL, /* RXD3/nINTSEL */
116 MX51_PAD_NANDF_RB2__GPIO3_10 | GPIO_PAD_CTRL, /* COL/RMII/CRSDV */
117 MX51_PAD_EIM_CS5__GPIO2_30 | GPIO_PAD_CTRL, /* CRS/PHYAD4 */
119 /* unusable pins on TX51 */
120 MX51_PAD_GPIO1_0__GPIO1_0,
121 MX51_PAD_GPIO1_1__GPIO1_1,
124 static const struct gpio tx51_gpios[] = {
126 { TX51_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_LOW, "RESET_OUT", },
128 /* FEC PHY control GPIOs */
129 { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */
130 { TX51_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */
131 { TX51_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, /* PHY INT (TX_ER) */
133 /* FEC PHY strap pins */
134 { IMX_GPIO_NR(3, 11), GPIOF_OUTPUT_INIT_LOW, "FEC PHY REGOFF", }, /* RX_CLK/REGOFF */
135 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE0", }, /* RXD0/Mode0 */
136 { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE1", }, /* RXD1/Mode1 */
137 { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE2", }, /* RXD2/Mode2 */
138 { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
139 { IMX_GPIO_NR(3, 10), GPIOF_OUTPUT_INIT_LOW, "FEC PHY RMII", }, /* COL/RMII/CRSDV */
140 { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
142 /* module internal I2C bus */
143 { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", },
144 { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", },
146 /* Unconnected pins */
147 { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "N/C", },
148 { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "N/C", },
154 #define WRSR_POR (1 << 4)
155 #define WRSR_TOUT (1 << 1)
156 #define WRSR_SFTW (1 << 0)
158 /* placed in section '.data' to prevent overwriting relocation info
161 static u32 wrsr __attribute__((section(".data")));
163 static void print_reset_cause(void)
165 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
166 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
170 printf("Reset cause: ");
172 srsr = readl(&src_regs->srsr);
173 wrsr = readw(wdt_base + 4);
175 if (wrsr & WRSR_POR) {
176 printf("%sPOR", dlm);
179 if (srsr & 0x00004) {
180 printf("%sCSU", dlm);
183 if (srsr & 0x00008) {
184 printf("%sIPP USER", dlm);
187 if (srsr & 0x00010) {
188 if (wrsr & WRSR_SFTW) {
189 printf("%sSOFT", dlm);
192 if (wrsr & WRSR_TOUT) {
193 printf("%sWDOG", dlm);
197 if (srsr & 0x00020) {
198 printf("%sJTAG HIGH-Z", dlm);
201 if (srsr & 0x00040) {
202 printf("%sJTAG SW", dlm);
205 if (srsr & 0x10000) {
206 printf("%sWARM BOOT", dlm);
215 static void print_cpuinfo(void)
219 cpurev = get_cpu_rev();
221 printf("CPU: Freescale i.MX51 rev%d.%d at %d MHz\n",
222 (cpurev & 0x000F0) >> 4,
223 (cpurev & 0x0000F) >> 0,
224 mxc_get_clock(MXC_ARM_CLK) / 1000000);
229 int board_early_init_f(void)
231 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
233 #ifdef CONFIG_CMD_BOOTCE
234 /* WinCE fails to enable these clocks */
235 writel(readl(&ccm_regs->CCGR2) | 0x0c000000, &ccm_regs->CCGR2); /* usboh3_ipg_ahb */
236 writel(readl(&ccm_regs->CCGR4) | 0x30000000, &ccm_regs->CCGR4); /* srtc */
237 writel(readl(&ccm_regs->CCGR6) | 0x00000300, &ccm_regs->CCGR6); /* emi_garb */
239 gpio_request_array(tx51_gpios, ARRAY_SIZE(tx51_gpios));
240 imx_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads));
242 writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
243 writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
245 writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
246 writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
247 writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
248 writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
249 writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
251 writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
252 writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
254 writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
255 writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
256 writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
257 writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
258 writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
265 /* Address of boot parameters */
266 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
274 /* dram_init must store complete ramsize in gd->ram_size */
275 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
278 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
279 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
281 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
282 CONFIG_SYS_SDRAM_CLK, ret);
284 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
285 __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
286 mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
287 CONFIG_SYS_SDRAM_CLK);
291 void dram_init_banksize(void)
293 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
294 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
296 #if CONFIG_NR_DRAM_BANKS > 1
297 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
298 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
303 #ifdef CONFIG_CMD_MMC
304 int board_mmc_getcd(struct mmc *mmc)
306 struct fsl_esdhc_cfg *cfg = mmc->priv;
308 if (cfg->cd_gpio < 0)
311 return !gpio_get_value(cfg->cd_gpio);
314 static struct fsl_esdhc_cfg esdhc_cfg[] = {
316 .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
317 .cd_gpio = IMX_GPIO_NR(3, 8),
321 .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
322 .cd_gpio = IMX_GPIO_NR(3, 6),
327 static const iomux_v3_cfg_t mmc0_pads[] = {
328 MX51_PAD_SD1_CMD__SD1_CMD,
329 MX51_PAD_SD1_CLK__SD1_CLK,
330 MX51_PAD_SD1_DATA0__SD1_DATA0,
331 MX51_PAD_SD1_DATA1__SD1_DATA1,
332 MX51_PAD_SD1_DATA2__SD1_DATA2,
333 MX51_PAD_SD1_DATA3__SD1_DATA3,
335 MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(PAD_CTL_PUE | PAD_CTL_PKE),
338 static const iomux_v3_cfg_t mmc1_pads[] = {
339 MX51_PAD_SD2_CMD__SD2_CMD,
340 MX51_PAD_SD2_CLK__SD2_CLK,
341 MX51_PAD_SD2_DATA0__SD2_DATA0,
342 MX51_PAD_SD2_DATA1__SD2_DATA1,
343 MX51_PAD_SD2_DATA2__SD2_DATA2,
344 MX51_PAD_SD2_DATA3__SD2_DATA3,
346 MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(PAD_CTL_PUE | PAD_CTL_PKE),
350 const iomux_v3_cfg_t *pads;
352 } mmc_pad_config[] = {
353 { mmc0_pads, ARRAY_SIZE(mmc0_pads), },
354 { mmc1_pads, ARRAY_SIZE(mmc1_pads), },
357 int board_mmc_init(bd_t *bis)
361 for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) {
363 struct fsl_esdhc_cfg *cfg;
365 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
368 imx_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads,
369 mmc_pad_config[i].count);
372 cfg->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
373 fsl_esdhc_initialize(bis, cfg);
375 mmc = find_mmc_device(i);
378 if (board_mmc_getcd(mmc) > 0)
383 #endif /* CONFIG_CMD_MMC */
385 #ifdef CONFIG_FEC_MXC
391 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
394 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
395 struct fuse_bank *bank = &iim->bank[1];
396 struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
401 for (i = 0; i < ETH_ALEN; i++)
402 mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]);
405 static iomux_v3_cfg_t tx51_fec_pads[] = {
406 /* reconfigure strap pins for FEC function */
407 MX51_PAD_NANDF_RB3__FEC_RX_CLK | FEC_PAD_CTRL2,
408 MX51_PAD_NANDF_D9__FEC_RDATA0 | FEC_PAD_CTRL2,
409 MX51_PAD_EIM_EB3__FEC_RDATA1 | FEC_PAD_CTRL2,
410 MX51_PAD_EIM_CS2__FEC_RDATA2 | FEC_PAD_CTRL2,
411 MX51_PAD_EIM_CS3__FEC_RDATA3 | FEC_PAD_CTRL2,
412 MX51_PAD_NANDF_RB2__FEC_COL | FEC_PAD_CTRL2,
413 MX51_PAD_EIM_CS5__FEC_CRS | FEC_PAD_CTRL,
416 /* take bit 4 of PHY address from configured PHY address or
417 * set it to 0 if PHYADDR is -1 (probe for PHY)
419 #define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5))
421 static struct gpio tx51_fec_gpios[] = {
422 { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY POWER", },
423 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode0", }, /* RXD0/Mode0 */
424 { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode1", }, /* RXD1/Mode1 */
425 { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode2", }, /* RXD2/Mode2 */
426 { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
428 { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
430 { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
434 int board_eth_init(bd_t *bis)
437 unsigned char mac[ETH_ALEN];
438 char mac_str[ETH_ALEN * 3] = "";
440 /* Power up the external phy and assert strap options */
441 gpio_request_array(tx51_fec_gpios, ARRAY_SIZE(tx51_fec_gpios));
443 /* delay at least 21ms for the PHY internal POR signal to deassert */
446 /* Deassert RESET to the external phy */
447 gpio_set_value(TX51_FEC_RST_GPIO, 1);
449 /* Without this delay the PHY won't work, though nothing in
450 * the datasheets suggests that it should be necessary!
453 imx_iomux_v3_setup_multiple_pads(tx51_fec_pads,
454 ARRAY_SIZE(tx51_fec_pads));
456 ret = cpu_eth_init(bis);
458 printf("cpu_eth_init() failed: %d\n", ret);
462 imx_get_mac_from_fuse(0, mac);
463 snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
464 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
465 setenv("ethaddr", mac_str);
469 #endif /* CONFIG_FEC_MXC */
477 void show_activity(int arg)
479 static int led_state = LED_STATE_INIT;
482 if (led_state == LED_STATE_INIT) {
484 gpio_set_value(TX51_LED_GPIO, 1);
485 led_state = LED_STATE_ON;
487 if (get_timer(last) > CONFIG_SYS_HZ) {
489 if (led_state == LED_STATE_ON) {
490 gpio_set_value(TX51_LED_GPIO, 0);
492 gpio_set_value(TX51_LED_GPIO, 1);
494 led_state = 1 - led_state;
499 static const iomux_v3_cfg_t stk5_pads[] = {
500 /* SW controlled LED on STK5 baseboard */
501 MX51_PAD_CSI2_D13__GPIO4_10,
504 MX51_PAD_GPIO1_4__GPIO1_4,
506 MX51_PAD_GPIO1_6__GPIO1_6,
507 /* USB PHY clock enable */
508 MX51_PAD_GPIO1_7__GPIO1_7,
509 /* USBH1 VBUS enable */
510 MX51_PAD_GPIO1_8__GPIO1_8,
512 MX51_PAD_GPIO1_9__GPIO1_9,
515 static const struct gpio stk5_gpios[] = {
516 { TX51_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
518 { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
519 { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", },
520 { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", },
521 { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
522 { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", },
526 static ushort tx51_cmap[256];
527 vidinfo_t panel_info = {
528 /* set to max. size supported by SoC */
532 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
536 static struct fb_videomode tx51_fb_mode = {
537 /* Standard VGA timing */
542 .pixclock = KHZ2PICOS(25175),
549 .sync = FB_SYNC_CLK_LAT_FALL,
550 .vmode = FB_VMODE_NONINTERLACED,
553 static int lcd_enabled = 1;
555 void lcd_enable(void)
558 * global variable from common/lcd.c
559 * Set to 0 here to prevent messages from going to LCD
560 * rather than serial console
564 karo_load_splashimage(1);
566 debug("Switching LCD on\n");
567 gpio_set_value(TX51_LCD_PWR_GPIO, 1);
569 gpio_set_value(TX51_LCD_RST_GPIO, 1);
571 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 0);
575 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
577 MX51_PAD_CSI2_VSYNC__GPIO4_13,
578 /* LCD POWER_ENABLE */
579 MX51_PAD_CSI2_HSYNC__GPIO4_14,
580 /* LCD Backlight (PWM) */
581 MX51_PAD_GPIO1_2__GPIO1_2,
584 MX51_PAD_DISP1_DAT0__DISP1_DAT0,
585 MX51_PAD_DISP1_DAT1__DISP1_DAT1,
586 MX51_PAD_DISP1_DAT2__DISP1_DAT2,
587 MX51_PAD_DISP1_DAT3__DISP1_DAT3,
588 MX51_PAD_DISP1_DAT4__DISP1_DAT4,
589 MX51_PAD_DISP1_DAT5__DISP1_DAT5,
590 MX51_PAD_DISP1_DAT6__DISP1_DAT6,
591 MX51_PAD_DISP1_DAT7__DISP1_DAT7,
592 MX51_PAD_DISP1_DAT8__DISP1_DAT8,
593 MX51_PAD_DISP1_DAT9__DISP1_DAT9,
594 MX51_PAD_DISP1_DAT10__DISP1_DAT10,
595 MX51_PAD_DISP1_DAT11__DISP1_DAT11,
596 MX51_PAD_DISP1_DAT12__DISP1_DAT12,
597 MX51_PAD_DISP1_DAT13__DISP1_DAT13,
598 MX51_PAD_DISP1_DAT14__DISP1_DAT14,
599 MX51_PAD_DISP1_DAT15__DISP1_DAT15,
600 MX51_PAD_DISP1_DAT16__DISP1_DAT16,
601 MX51_PAD_DISP1_DAT17__DISP1_DAT17,
602 MX51_PAD_DISP1_DAT18__DISP1_DAT18,
603 MX51_PAD_DISP1_DAT19__DISP1_DAT19,
604 MX51_PAD_DISP1_DAT20__DISP1_DAT20,
605 MX51_PAD_DISP1_DAT21__DISP1_DAT21,
606 MX51_PAD_DISP1_DAT22__DISP1_DAT22,
607 MX51_PAD_DISP1_DAT23__DISP1_DAT23,
608 MX51_PAD_DI1_PIN2__DI1_PIN2, /* HSYNC */
609 MX51_PAD_DI1_PIN3__DI1_PIN3, /* VSYNC */
612 static const struct gpio stk5_lcd_gpios[] = {
613 { TX51_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
614 { TX51_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
615 { TX51_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
618 void lcd_ctrl_init(void *lcdbase)
620 int color_depth = 24;
624 struct fb_videomode *p = &tx51_fb_mode;
625 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
627 ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
628 unsigned long di_clk_rate = 65000000;
631 debug("LCD disabled\n");
635 if (tstc() || (wrsr & WRSR_TOUT)) {
636 debug("Disabling LCD\n");
641 vm = getenv("video_mode");
643 debug("Disabling LCD\n");
647 while (*vm != '\0') {
648 if (*vm >= '0' && *vm <= '9') {
651 val = simple_strtoul(vm, &end, 0);
654 if (val > panel_info.vl_col)
655 val = panel_info.vl_col;
657 panel_info.vl_col = val;
659 } else if (!yres_set) {
660 if (val > panel_info.vl_row)
661 val = panel_info.vl_row;
663 panel_info.vl_row = val;
665 } else if (!bpp_set) {
674 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
675 end - vm, vm, color_depth);
678 } else if (!refresh_set) {
704 pix_fmt = IPU_PIX_FMT_RGB24;
705 tmp = strchr(vm, ':');
713 switch (color_depth) {
715 panel_info.vl_bpix = 3;
719 panel_info.vl_bpix = 4;
723 panel_info.vl_bpix = 5;
726 p->pixclock = KHZ2PICOS(refresh *
727 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
728 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
730 debug("Pixel clock set to %lu.%03lu MHz\n",
731 PICOS2KHZ(p->pixclock) / 1000,
732 PICOS2KHZ(p->pixclock) % 1000);
734 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
735 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
736 ARRAY_SIZE(stk5_lcd_pads));
738 debug("Initializing FB driver\n");
740 pix_fmt = IPU_PIX_FMT_RGB24;
742 if (karo_load_splashimage(0) == 0) {
743 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
744 u32 ccgr4 = readl(&ccm_regs->CCGR4);
746 /* MIPI HSC clock is required for initialization */
747 writel(ccgr4 | (3 << 12), &ccm_regs->CCGR4);
749 debug("Initializing LCD controller\n");
750 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
752 writel(ccgr4 & ~(3 << 12), &ccm_regs->CCGR4);
754 debug("Skipping initialization of LCD controller\n");
758 #define lcd_enabled 0
759 #endif /* CONFIG_LCD */
761 static void stk5_board_init(void)
763 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
764 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
767 static void stk5v3_board_init(void)
772 static void tx51_set_cpu_clock(void)
774 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
777 if (tstc() || (wrsr & WRSR_TOUT))
780 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
783 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
785 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
788 printf("CPU clock set to %u.%03u MHz\n",
789 mxc_get_clock(MXC_ARM_CLK) / 1000000,
790 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
793 int board_late_init(void)
796 const char *baseboard;
798 tx51_set_cpu_clock();
801 baseboard = getenv("baseboard");
805 if (strncmp(baseboard, "stk5", 4) == 0) {
806 printf("Baseboard: %s\n", baseboard);
807 if ((strlen(baseboard) == 4) ||
808 strcmp(baseboard, "stk5-v3") == 0) {
810 } else if (strcmp(baseboard, "stk5-v5") == 0) {
811 printf("ERROR: Baseboard '%s' incompatible with TX51 module!\n",
815 printf("WARNING: Unsupported STK5 board rev.: %s\n",
819 printf("WARNING: Unsupported baseboard: '%s'\n",
825 gpio_set_value(TX51_RESET_OUT_GPIO, 1);
833 printf("Board: Ka-Ro TX51-%sxx%s\n",
834 TX51_MOD_PREFIX, TX51_MOD_SUFFIX);
839 #if defined(CONFIG_OF_BOARD_SETUP)
840 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
841 #include <jffs2/jffs2.h>
842 #include <mtd_node.h>
843 struct node_info nodes[] = {
844 { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, },
848 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
851 void ft_board_setup(void *blob, bd_t *bd)
853 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
854 fdt_fixup_ethernet(blob);
856 karo_fdt_fixup_touchpanel(blob);
857 karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", 0x73f80000);