board/mpc8349emds/mpc8349emds.c

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  */
  24
  25 #include <common.h>
  26 #include <ioports.h>
  27 #include <mpc83xx.h>
  28 #include <asm/mpc8349_pci.h>
  29 #include <i2c.h>
  30 #include <spd.h>
  31 #include <miiphy.h>
  32 #include <command.h>
  33 #if defined(CONFIG_SPD_EEPROM)
  34 #include <spd_sdram.h>
  35 #endif
  36 int fixed_sdram(void);
  37 void sdram_init(void);
  38
  39 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
  40 void ddr_enable_ecc(unsigned int dram_size);
  41 #endif
  42
  43 int board_early_init_f (void)
  44 {
  45         volatile u8* bcsr = (volatile u8*)CFG_BCSR;
  46
  47         /* Enable flash write */
  48         bcsr[1] &= ~0x01;
  49
  50 #ifdef CFG_USE_MPC834XSYS_USB_PHY
  51         /* Use USB PHY on SYS board */
  52         bcsr[5] |= 0x02;
  53 #endif
  54
  55         return 0;
  56 }
  57
  58 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
  59
  60 long int initdram (int board_type)
  61 {
  62         volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
  63         u32 msize = 0;
  64
  65         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  66                 return -1;
  67
  68         puts("Initializing\n");
  69
  70         /* DDR SDRAM - Main SODIMM */
  71         im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
  72 #if defined(CONFIG_SPD_EEPROM)
  73         msize = spd_sdram();
  74 #else
  75         msize = fixed_sdram();
  76 #endif
  77         /*
  78          * Initialize SDRAM if it is on local bus.
  79          */
  80         sdram_init();
  81
  82 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  83         /*
  84          * Initialize and enable DDR ECC.
  85          */
  86         ddr_enable_ecc(msize * 1024 * 1024);
  87 #endif
  88         puts("   DDR RAM: ");
  89         /* return total bus SDRAM size(bytes)  -- DDR */
  90         return (msize * 1024 * 1024);
  91 }
  92
  93 #if !defined(CONFIG_SPD_EEPROM)
  94 /*************************************************************************
  95  *  fixed sdram init -- doesn't use serial presence detect.
  96  ************************************************************************/
  97 int fixed_sdram(void)
  98 {
  99         volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
 100         u32 msize = 0;
 101         u32 ddr_size;
 102         u32 ddr_size_log2;
 103
 104         msize = CFG_DDR_SIZE;
 105         for (ddr_size = msize << 20, ddr_size_log2 = 0;
 106              (ddr_size > 1);
 107              ddr_size = ddr_size>>1, ddr_size_log2++) {
 108                 if (ddr_size & 1) {
 109                         return -1;
 110                 }
 111         }
 112         im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
 113         im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 114
 115 #if (CFG_DDR_SIZE != 256)
 116 #warning Currenly any ddr size other than 256 is not supported
 117 #endif
 118         im->ddr.csbnds[2].csbnds = 0x0000000f;
 119         im->ddr.cs_config[2] = CFG_DDR_CONFIG;
 120
 121         /* currently we use only one CS, so disable the other banks */
 122         im->ddr.cs_config[0] = 0;
 123         im->ddr.cs_config[1] = 0;
 124         im->ddr.cs_config[3] = 0;
 125
 126         im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 127         im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
 128
 129         im->ddr.sdram_cfg =
 130                 SDRAM_CFG_SREN
 131 #if defined(CONFIG_DDR_2T_TIMING)
 132                 | SDRAM_CFG_2T_EN
 133 #endif
 134                 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
 135 #if defined (CONFIG_DDR_32BIT)
 136         /* for 32-bit mode burst length is 8 */
 137         im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
 138 #endif
 139         im->ddr.sdram_mode = CFG_DDR_MODE;
 140
 141         im->ddr.sdram_interval = CFG_DDR_INTERVAL;
 142         udelay(200);
 143
 144         /* enable DDR controller */
 145         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 146         return msize;
 147 }
 148 #endif/*!CFG_SPD_EEPROM*/
 149
 150
 151 int checkboard (void)
 152 {
 153         puts("Board: Freescale MPC8349EMDS\n");
 154         return 0;
 155 }
 156
 157 /*
 158  * if MPC8349EMDS is soldered with SDRAM
 159  */
 160 #if defined(CFG_BR2_PRELIM)  \
 161         && defined(CFG_OR2_PRELIM) \
 162         && defined(CFG_LBLAWBAR2_PRELIM) \
 163         && defined(CFG_LBLAWAR2_PRELIM)
 164 /*
 165  * Initialize SDRAM memory on the Local Bus.
 166  */
 167
 168 void sdram_init(void)
 169 {
 170         volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
 171         volatile lbus8349_t *lbc= &immap->lbus;
 172         uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 173
 174         puts("\n   SDRAM on Local Bus: ");
 175         print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 176
 177         /*
 178          * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 179          */
 180
 181         /* setup mtrpt, lsrt and lbcr for LB bus */
 182         lbc->lbcr = CFG_LBC_LBCR;
 183         lbc->mrtpr = CFG_LBC_MRTPR;
 184         lbc->lsrt = CFG_LBC_LSRT;
 185         asm("sync");
 186
 187         /*
 188          * Configure the SDRAM controller Machine Mode Register.
 189          */
 190         lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
 191
 192         lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
 193         asm("sync");
 194         *sdram_addr = 0xff;
 195         udelay(100);
 196
 197         lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
 198         asm("sync");
 199         /*1 times*/
 200         *sdram_addr = 0xff;
 201         udelay(100);
 202         /*2 times*/
 203         *sdram_addr = 0xff;
 204         udelay(100);
 205         /*3 times*/
 206         *sdram_addr = 0xff;
 207         udelay(100);
 208         /*4 times*/
 209         *sdram_addr = 0xff;
 210         udelay(100);
 211         /*5 times*/
 212         *sdram_addr = 0xff;
 213         udelay(100);
 214         /*6 times*/
 215         *sdram_addr = 0xff;
 216         udelay(100);
 217         /*7 times*/
 218         *sdram_addr = 0xff;
 219         udelay(100);
 220         /*8 times*/
 221         *sdram_addr = 0xff;
 222         udelay(100);
 223
 224         /* 0x58636733; mode register write operation */
 225         lbc->lsdmr = CFG_LBC_LSDMR_4;
 226         asm("sync");
 227         *sdram_addr = 0xff;
 228         udelay(100);
 229
 230         lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
 231         asm("sync");
 232         *sdram_addr = 0xff;
 233         udelay(100);
 234 }
 235 #else
 236 void sdram_init(void)
 237 {
 238         put("SDRAM on Local Bus is NOT available!\n");
 239 }
 240 #endif
 241
 242 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
 243 /*
 244  * ECC user commands
 245  */
 246 void ecc_print_status(void)
 247 {
 248         volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
 249         volatile ddr8349_t *ddr = &immap->ddr;
 250
 251         printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
 252
 253         /* Interrupts */
 254         printf("Memory Error Interrupt Enable:\n");
 255         printf("  Multiple-Bit Error Interrupt Enable: %d\n",
 256                         (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
 257         printf("  Single-Bit Error Interrupt Enable: %d\n",
 258                         (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
 259         printf("  Memory Select Error Interrupt Enable: %d\n\n",
 260                         (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
 261
 262         /* Error disable */
 263         printf("Memory Error Disable:\n");
 264         printf("  Multiple-Bit Error Disable: %d\n",
 265                         (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
 266         printf("  Sinle-Bit Error Disable: %d\n",
 267                         (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
 268         printf("  Memory Select Error Disable: %d\n\n",
 269                         (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
 270
 271         /* Error injection */
 272         printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
 273                         ddr->data_err_inject_hi, ddr->data_err_inject_lo);
 274
 275         printf("Memory Data Path Error Injection Mask ECC:\n");
 276         printf("  ECC Mirror Byte: %d\n",
 277                         (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
 278         printf("  ECC Injection Enable: %d\n",
 279                         (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
 280         printf("  ECC Error Injection Mask: 0x%02x\n\n",
 281                         ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
 282
 283         /* SBE counter/threshold */
 284         printf("Memory Single-Bit Error Management (0..255):\n");
 285         printf("  Single-Bit Error Threshold: %d\n",
 286                         (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
 287         printf("  Single-Bit Error Counter: %d\n\n",
 288                         (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
 289
 290         /* Error detect */
 291         printf("Memory Error Detect:\n");
 292         printf("  Multiple Memory Errors: %d\n",
 293                         (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
 294         printf("  Multiple-Bit Error: %d\n",
 295                         (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
 296         printf("  Single-Bit Error: %d\n",
 297                         (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
 298         printf("  Memory Select Error: %d\n\n",
 299                         (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
 300
 301         /* Capture data */
 302         printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
 303         printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
 304                         ddr->capture_data_hi, ddr->capture_data_lo);
 305         printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
 306                 ddr->capture_ecc & CAPTURE_ECC_ECE);
 307
 308         printf("Memory Error Attributes Capture:\n");
 309         printf("  Data Beat Number: %d\n",
 310                         (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
 311         printf("  Transaction Size: %d\n",
 312                         (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
 313         printf("  Transaction Source: %d\n",
 314                         (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
 315         printf("  Transaction Type: %d\n",
 316                         (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
 317         printf("  Error Information Valid: %d\n\n",
 318                         ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
 319 }
 320
 321 int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 322 {
 323         volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
 324         volatile ddr8349_t *ddr = &immap->ddr;
 325         volatile u32 val;
 326         u64 *addr, count, val64;
 327         register u64 *i;
 328
 329         if (argc > 4) {
 330                 printf ("Usage:\n%s\n", cmdtp->usage);
 331                 return 1;
 332         }
 333
 334         if (argc == 2) {
 335                 if (strcmp(argv[1], "status") == 0) {
 336                         ecc_print_status();
 337                         return 0;
 338                 } else if (strcmp(argv[1], "captureclear") == 0) {
 339                         ddr->capture_address = 0;
 340                         ddr->capture_data_hi = 0;
 341                         ddr->capture_data_lo = 0;
 342                         ddr->capture_ecc = 0;
 343                         ddr->capture_attributes = 0;
 344                         return 0;
 345                 }
 346         }
 347
 348         if (argc == 3) {
 349                 if (strcmp(argv[1], "sbecnt") == 0) {
 350                         val = simple_strtoul(argv[2], NULL, 10);
 351                         if (val > 255) {
 352                                 printf("Incorrect Counter value, should be 0..255\n");
 353                                 return 1;
 354                         }
 355
 356                         val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
 357                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
 358
 359                         ddr->err_sbe = val;
 360                         return 0;
 361                 } else if (strcmp(argv[1], "sbethr") == 0) {
 362                         val = simple_strtoul(argv[2], NULL, 10);
 363                         if (val > 255) {
 364                                 printf("Incorrect Counter value, should be 0..255\n");
 365                                 return 1;
 366                         }
 367
 368                         val = (val << ECC_ERROR_MAN_SBET_SHIFT);
 369                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
 370
 371                         ddr->err_sbe = val;
 372                         return 0;
 373                 } else if (strcmp(argv[1], "errdisable") == 0) {
 374                         val = ddr->err_disable;
 375
 376                         if (strcmp(argv[2], "+sbe") == 0) {
 377                                 val |= ECC_ERROR_DISABLE_SBED;
 378                         } else if (strcmp(argv[2], "+mbe") == 0) {
 379                                 val |= ECC_ERROR_DISABLE_MBED;
 380                         } else if (strcmp(argv[2], "+mse") == 0) {
 381                                 val |= ECC_ERROR_DISABLE_MSED;
 382                         } else if (strcmp(argv[2], "+all") == 0) {
 383                                 val |= (ECC_ERROR_DISABLE_SBED |
 384                                         ECC_ERROR_DISABLE_MBED |
 385                                         ECC_ERROR_DISABLE_MSED);
 386                         } else if (strcmp(argv[2], "-sbe") == 0) {
 387                                 val &= ~ECC_ERROR_DISABLE_SBED;
 388                         } else if (strcmp(argv[2], "-mbe") == 0) {
 389                                 val &= ~ECC_ERROR_DISABLE_MBED;
 390                         } else if (strcmp(argv[2], "-mse") == 0) {
 391                                 val &= ~ECC_ERROR_DISABLE_MSED;
 392                         } else if (strcmp(argv[2], "-all") == 0) {
 393                                 val &= ~(ECC_ERROR_DISABLE_SBED |
 394                                         ECC_ERROR_DISABLE_MBED |
 395                                         ECC_ERROR_DISABLE_MSED);
 396                         } else {
 397                                 printf("Incorrect err_disable field\n");
 398                                 return 1;
 399                         }
 400
 401                         ddr->err_disable = val;
 402                         __asm__ __volatile__ ("sync");
 403                         __asm__ __volatile__ ("isync");
 404                         return 0;
 405                 } else if (strcmp(argv[1], "errdetectclr") == 0) {
 406                         val = ddr->err_detect;
 407
 408                         if (strcmp(argv[2], "mme") == 0) {
 409                                 val |= ECC_ERROR_DETECT_MME;
 410                         } else if (strcmp(argv[2], "sbe") == 0) {
 411                                 val |= ECC_ERROR_DETECT_SBE;
 412                         } else if (strcmp(argv[2], "mbe") == 0) {
 413                                 val |= ECC_ERROR_DETECT_MBE;
 414                         } else if (strcmp(argv[2], "mse") == 0) {
 415                                 val |= ECC_ERROR_DETECT_MSE;
 416                         } else if (strcmp(argv[2], "all") == 0) {
 417                                 val |= (ECC_ERROR_DETECT_MME |
 418                                         ECC_ERROR_DETECT_MBE |
 419                                         ECC_ERROR_DETECT_SBE |
 420                                         ECC_ERROR_DETECT_MSE);
 421                         } else {
 422                                 printf("Incorrect err_detect field\n");
 423                                 return 1;
 424                         }
 425
 426                         ddr->err_detect = val;
 427                         return 0;
 428                 } else if (strcmp(argv[1], "injectdatahi") == 0) {
 429                         val = simple_strtoul(argv[2], NULL, 16);
 430
 431                         ddr->data_err_inject_hi = val;
 432                         return 0;
 433                 } else if (strcmp(argv[1], "injectdatalo") == 0) {
 434                         val = simple_strtoul(argv[2], NULL, 16);
 435
 436                         ddr->data_err_inject_lo = val;
 437                         return 0;
 438                 } else if (strcmp(argv[1], "injectecc") == 0) {
 439                         val = simple_strtoul(argv[2], NULL, 16);
 440                         if (val > 0xff) {
 441                                 printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
 442                                 return 1;
 443                         }
 444                         val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
 445
 446                         ddr->ecc_err_inject = val;
 447                         return 0;
 448                 } else if (strcmp(argv[1], "inject") == 0) {
 449                         val = ddr->ecc_err_inject;
 450
 451                         if (strcmp(argv[2], "en") == 0)
 452                                 val |= ECC_ERR_INJECT_EIEN;
 453                         else if (strcmp(argv[2], "dis") == 0)
 454                                 val &= ~ECC_ERR_INJECT_EIEN;
 455                         else
 456                                 printf("Incorrect command\n");
 457
 458                         ddr->ecc_err_inject = val;
 459                         __asm__ __volatile__ ("sync");
 460                         __asm__ __volatile__ ("isync");
 461                         return 0;
 462                 } else if (strcmp(argv[1], "mirror") == 0) {
 463                         val = ddr->ecc_err_inject;
 464
 465                         if (strcmp(argv[2], "en") == 0)
 466                                 val |= ECC_ERR_INJECT_EMB;
 467                         else if (strcmp(argv[2], "dis") == 0)
 468                                 val &= ~ECC_ERR_INJECT_EMB;
 469                         else
 470                                 printf("Incorrect command\n");
 471
 472                         ddr->ecc_err_inject = val;
 473                         return 0;
 474                 }
 475         }
 476
 477         if (argc == 4) {
 478                 if (strcmp(argv[1], "test") == 0) {
 479                         addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
 480                         count = simple_strtoul(argv[3], NULL, 16);
 481
 482                         if ((u32)addr % 8) {
 483                                 printf("Address not alligned on double word boundary\n");
 484                                 return 1;
 485                         }
 486
 487                         disable_interrupts();
 488                         icache_disable();
 489
 490                         for (i = addr; i < addr + count; i++) {
 491                                 /* enable injects */
 492                                 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
 493                                 __asm__ __volatile__ ("sync");
 494                                 __asm__ __volatile__ ("isync");
 495
 496                                 /* write memory location injecting errors */
 497                                 *i = 0x1122334455667788ULL;
 498                                 __asm__ __volatile__ ("sync");
 499
 500                                 /* disable injects */
 501                                 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
 502                                 __asm__ __volatile__ ("sync");
 503                                 __asm__ __volatile__ ("isync");
 504
 505                                 /* read data, this generates ECC error */
 506                                 val64 = *i;
 507                                 __asm__ __volatile__ ("sync");
 508
 509                                 /* disable errors for ECC */
 510                                 ddr->err_disable |= ~ECC_ERROR_ENABLE;
 511                                 __asm__ __volatile__ ("sync");
 512                                 __asm__ __volatile__ ("isync");
 513
 514                                 /* re-initialize memory, write the location again
 515                                  * NOT injecting errors this time */
 516                                 *i = 0xcafecafecafecafeULL;
 517                                 __asm__ __volatile__ ("sync");
 518
 519                                 /* enable errors for ECC */
 520                                 ddr->err_disable &= ECC_ERROR_ENABLE;
 521                                 __asm__ __volatile__ ("sync");
 522                                 __asm__ __volatile__ ("isync");
 523                         }
 524
 525                         icache_enable();
 526                         enable_interrupts();
 527
 528                         return 0;
 529                 }
 530         }
 531
 532         printf ("Usage:\n%s\n", cmdtp->usage);
 533         return 1;
 534 }
 535
 536 U_BOOT_CMD(
 537         ecc,     4,     0,      do_ecc,
 538         "ecc     - support for DDR ECC features\n",
 539         "status              - print out status info\n"
 540         "ecc captureclear        - clear capture regs data\n"
 541         "ecc sbecnt <val>        - set Single-Bit Error counter\n"
 542         "ecc sbethr <val>        - set Single-Bit Threshold\n"
 543         "ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
 544         "  [-|+]sbe - Single-Bit Error\n"
 545         "  [-|+]mbe - Multiple-Bit Error\n"
 546         "  [-|+]mse - Memory Select Error\n"
 547         "  [-|+]all - all errors\n"
 548         "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
 549         "  mme - Multiple Memory Errors\n"
 550         "  sbe - Single-Bit Error\n"
 551         "  mbe - Multiple-Bit Error\n"
 552         "  mse - Memory Select Error\n"
 553         "  all - all errors\n"
 554         "ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
 555         "ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
 556         "ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
 557         "ecc inject <en|dis>    - enable/disable error injection\n"
 558         "ecc mirror <en|dis>    - enable/disable mirror byte\n"
 559         "ecc test <addr> <cnt>  - test mem region:\n"
 560         "  - enables injects\n"
 561         "  - writes pattern injecting errors\n"
 562         "  - disables injects\n"
 563         "  - reads pattern back, generates error\n"
 564         "  - re-inits memory"
 565 );
 566 #endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */