board/phytec/pcm051/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
   5  *
   6  * Copyright (C) 2013 Lemonage Software GmbH
   7  * Author Lars Poeschel <poeschel@lemonage.de>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <errno.h>
  14 #include <spl.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/omap.h>
  18 #include <asm/arch/ddr_defs.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/mmc_host_def.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/io.h>
  24 #include <asm/emif.h>
  25 #include <asm/gpio.h>
  26 #include <i2c.h>
  27 #include <miiphy.h>
  28 #include <cpsw.h>
  29 #include "board.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  34
  35 /* MII mode defines */
  36 #define MII_MODE_ENABLE         0x0
  37 #define RGMII_MODE_ENABLE       0xA
  38 #define RMII_RGMII2_MODE_ENABLE 0x49
  39
  40 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  41
  42 #ifdef CONFIG_SPL_BUILD
  43
  44 /* DDR RAM defines */
  45 #define DDR_CLK_MHZ             303 /* DDR_DPLL_MULT value */
  46
  47 #define OSC     (V_OSCK/1000000)
  48 const struct dpll_params dpll_ddr = {
  49                 DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
  50
  51 const struct dpll_params *get_dpll_ddr_params(void)
  52 {
  53         return &dpll_ddr;
  54 }
  55
  56 static const struct ddr_data ddr3_data = {
  57         .datardsratio0 = MT41J256M8HX15E_RD_DQS,
  58         .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
  59         .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
  60         .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
  61         .datadldiff0 = PHY_DLL_LOCK_DIFF,
  62 };
  63
  64 static const struct cmd_control ddr3_cmd_ctrl_data = {
  65         .cmd0csratio = MT41J256M8HX15E_RATIO,
  66         .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
  67         .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  68
  69         .cmd1csratio = MT41J256M8HX15E_RATIO,
  70         .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
  71         .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  72
  73         .cmd2csratio = MT41J256M8HX15E_RATIO,
  74         .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
  75         .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  76 };
  77
  78 static struct emif_regs ddr3_emif_reg_data = {
  79         .sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
  80         .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
  81         .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
  82         .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
  83         .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
  84         .zq_config = MT41J256M8HX15E_ZQ_CFG,
  85         .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
  86                                 PHY_EN_DYN_PWRDN,
  87 };
  88 #endif
  89
  90 /*
  91  * early system init of muxing and clocks.
  92  */
  93 void s_init(void)
  94 {
  95         /*
  96          * Save the boot parameters passed from romcode.
  97          * We cannot delay the saving further than this,
  98          * to prevent overwrites.
  99          */
 100 #ifdef CONFIG_SPL_BUILD
 101         save_omap_boot_params();
 102 #endif
 103
 104         /*
 105          * WDT1 is already running when the bootloader gets control
 106          * Disable it to avoid "random" resets
 107          */
 108         writel(0xAAAA, &wdtimer->wdtwspr);
 109         while (readl(&wdtimer->wdtwwps) != 0x0)
 110                 ;
 111         writel(0x5555, &wdtimer->wdtwspr);
 112         while (readl(&wdtimer->wdtwwps) != 0x0)
 113                 ;
 114
 115 #ifdef CONFIG_SPL_BUILD
 116         /* Setup the PLLs and the clocks for the peripherals */
 117         pll_init();
 118
 119         /* Enable RTC32K clock */
 120         rtc32k_enable();
 121
 122         enable_uart0_pin_mux();
 123         uart_soft_reset();
 124
 125         gd = &gdata;
 126
 127         preloader_console_init();
 128
 129         /* Initalize the board header */
 130         enable_i2c0_pin_mux();
 131         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 132
 133         enable_board_pin_mux();
 134
 135         config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
 136                         &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 137 #endif
 138 }
 139
 140 /*
 141  * Basic board specific setup.  Pinmux has been handled already.
 142  */
 143 int board_init(void)
 144 {
 145         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 146
 147         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 148
 149         return 0;
 150 }
 151
 152 #ifdef CONFIG_DRIVER_TI_CPSW
 153 static void cpsw_control(int enabled)
 154 {
 155         /* VTP can be added here */
 156
 157         return;
 158 }
 159
 160 static struct cpsw_slave_data cpsw_slaves[] = {
 161         {
 162                 .slave_reg_ofs  = 0x208,
 163                 .sliver_reg_ofs = 0xd80,
 164                 .phy_id         = 0,
 165                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
 166         },
 167         {
 168                 .slave_reg_ofs  = 0x308,
 169                 .sliver_reg_ofs = 0xdc0,
 170                 .phy_id         = 1,
 171                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
 172         },
 173 };
 174
 175 static struct cpsw_platform_data cpsw_data = {
 176         .mdio_base              = CPSW_MDIO_BASE,
 177         .cpsw_base              = CPSW_BASE,
 178         .mdio_div               = 0xff,
 179         .channels               = 8,
 180         .cpdma_reg_ofs          = 0x800,
 181         .slaves                 = 1,
 182         .slave_data             = cpsw_slaves,
 183         .ale_reg_ofs            = 0xd00,
 184         .ale_entries            = 1024,
 185         .host_port_reg_ofs      = 0x108,
 186         .hw_stats_reg_ofs       = 0x900,
 187         .mac_control            = (1 << 5),
 188         .control                = cpsw_control,
 189         .host_port_num          = 0,
 190         .version                = CPSW_CTRL_VERSION_2,
 191 };
 192 #endif
 193
 194 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 195         (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
 196 int board_eth_init(bd_t *bis)
 197 {
 198         int rv, n = 0;
 199 #ifdef CONFIG_DRIVER_TI_CPSW
 200         uint8_t mac_addr[6];
 201         uint32_t mac_hi, mac_lo;
 202
 203         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 204                 printf("<ethaddr> not set. Reading from E-fuse\n");
 205                 /* try reading mac address from efuse */
 206                 mac_lo = readl(&cdev->macid0l);
 207                 mac_hi = readl(&cdev->macid0h);
 208                 mac_addr[0] = mac_hi & 0xFF;
 209                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 210                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 211                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 212                 mac_addr[4] = mac_lo & 0xFF;
 213                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 214
 215                 if (is_valid_ether_addr(mac_addr))
 216                         eth_setenv_enetaddr("ethaddr", mac_addr);
 217                 else
 218                         goto try_usbether;
 219         }
 220
 221         writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
 222
 223         rv = cpsw_register(&cpsw_data);
 224         if (rv < 0)
 225                 printf("Error %d registering CPSW switch\n", rv);
 226         else
 227                 n += rv;
 228 try_usbether:
 229 #endif
 230
 231 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
 232         rv = usb_eth_initialize(bis);
 233         if (rv < 0)
 234                 printf("Error %d registering USB_ETHER\n", rv);
 235         else
 236                 n += rv;
 237 #endif
 238         return n;
 239 }
 240 #endif