3 * Ingo Assmus <ingo.assmus@keymile.com>
5 * based on - Driver for MV64460X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 3 the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * mv_eth.c - header file for the polled mode GT ethernet driver
37 /* enable Debug outputs */
48 /* PHY DFCDL Registers */
49 #define ETH_PHY_DFCDL_CONFIG0_REG 0x2100
50 #define ETH_PHY_DFCDL_CONFIG1_REG 0x2104
51 #define ETH_PHY_DFCDL_ADDR_REG 0x2110
52 #define ETH_PHY_DFCDL_DATA0_REG 0x2114
54 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
55 #define PHY_UPDATE_TIMEOUT 10000
57 #undef MV64460_CHECKSUM_OFFLOAD
58 /*************************************************************************
59 **************************************************************************
60 **************************************************************************
61 * The first part is the high level driver of the gigE ethernet ports. *
62 **************************************************************************
63 **************************************************************************
64 *************************************************************************/
66 /* Definition for configuring driver */
67 /* #define UPDATE_STATS_BY_SOFTWARE */
68 #undef MV64460_RX_QUEUE_FILL_ON_TASK
72 #define MAGIC_ETH_RUNNING 8031971
73 #define MV64460_INTERNAL_SRAM_SIZE _256K
74 #define EXTRA_BYTES 32
75 #define WRAP ETH_HLEN + 2 + 4 + 16
76 #define BUFFER_MTU dev->mtu + WRAP
77 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
78 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
79 #ifdef MV64460_RX_FILL_ON_TASK
80 #define INT_CAUSE_MASK_ALL 0x00000000
81 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
82 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
85 /* Read/Write to/from MV64460 internal registers */
86 #define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
87 #define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
88 #define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
89 #define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
91 #define my_cpu_to_le32(x) my_le32_to_cpu((x))
93 /* Static function declarations */
94 static int mv64460_eth_real_open (struct eth_device *eth);
95 static int mv64460_eth_real_stop (struct eth_device *eth);
96 static struct net_device_stats *mv64460_eth_get_stats (struct eth_device
98 static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
99 static void mv64460_eth_update_stat (struct eth_device *dev);
100 bool db64460_eth_start (struct eth_device *eth);
101 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
102 unsigned int mib_offset);
103 int mv64460_eth_receive (struct eth_device *dev);
105 int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length);
107 int mv_miiphy_read(char *devname, unsigned char phy_addr,
108 unsigned char phy_reg, unsigned short *value);
109 int mv_miiphy_write(char *devname, unsigned char phy_addr,
110 unsigned char phy_reg, unsigned short value);
112 int phy_setup_aneg (char *devname, unsigned char addr);
114 #ifndef UPDATE_STATS_BY_SOFTWARE
115 static void mv64460_eth_print_stat (struct eth_device *dev);
117 /* Processes a received packet */
118 extern void NetReceive (volatile uchar *, int);
120 extern unsigned int INTERNAL_REG_BASE_ADDR;
122 unsigned long my_le32_to_cpu (unsigned long x)
124 return (((x & 0x000000ffU) << 24) |
125 ((x & 0x0000ff00U) << 8) |
126 ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
129 /*************************************************
130 *Helper functions - used inside the driver only *
131 *************************************************/
133 void print_globals (struct eth_device *dev)
135 printf ("Ethernet PRINT_Globals-Debug function\n");
136 printf ("Base Address for ETH_PORT_INFO: %08x\n",
137 (unsigned int) dev->priv);
138 printf ("Base Address for mv64460_eth_priv: %08x\n",
139 (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
142 printf ("GT Internal Base Address: %08x\n",
143 INTERNAL_REG_BASE_ADDR);
144 printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE);
145 printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE);
146 printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
147 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
149 (MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32);
150 printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
151 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
153 (MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32);
159 /**********************************************************************
160 * mv64460_eth_print_phy_status
162 * Prints gigabit ethenret phy status
164 * Input : pointer to ethernet interface network device structure
166 **********************************************************************/
167 void mv64460_eth_print_phy_status (struct eth_device *dev)
169 struct mv64460_eth_priv *port_private;
170 unsigned int port_num;
171 ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
172 unsigned int port_status, phy_reg_data;
175 (struct mv64460_eth_priv *) ethernet_private->port_private;
176 port_num = port_private->port_num;
178 /* Check Link status on phy */
179 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
180 if (!(phy_reg_data & 0x20)) {
181 printf ("Ethernet port changed link status to DOWN\n");
184 MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
185 printf ("Ethernet status port %d: Link up", port_num);
187 (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
188 if (port_status & BIT4)
189 printf (", Speed 1 Gbps");
192 (port_status & BIT5) ? "Speed 100 Mbps" :
198 /**********************************************************************
199 * u-boot entry functions for mv64460_eth
201 **********************************************************************/
202 int db64460_eth_probe (struct eth_device *dev)
204 return ((int) db64460_eth_start (dev));
207 int db64460_eth_poll (struct eth_device *dev)
209 return mv64460_eth_receive (dev);
212 int db64460_eth_transmit (struct eth_device *dev, volatile void *packet,
215 mv64460_eth_xmit (dev, packet, length);
219 void db64460_eth_disable (struct eth_device *dev)
221 mv64460_eth_stop (dev);
225 #define DFCDL(write,read) ((write << 6) | read)
226 unsigned int ethDfcdls[] = { DFCDL(0,0),
291 void mv_eth_phy_init(void)
295 MV_REG_WRITE(ETH_PHY_DFCDL_ADDR_REG, 0);
297 for (i = 0 ; i < 64; i++) {
298 MV_REG_WRITE(ETH_PHY_DFCDL_DATA0_REG, ethDfcdls[i]);
301 MV_REG_WRITE(ETH_PHY_DFCDL_CONFIG0_REG,0x300000);
304 void mv6446x_eth_initialize (bd_t * bis)
306 struct eth_device *dev;
307 ETH_PORT_INFO *ethernet_private;
308 struct mv64460_eth_priv *port_private;
310 char *s, *e, buf[64];
313 * Set RGMII clock drives strength
315 temp = MV_REG_READ(0x20A0);
317 MV_REG_WRITE(0x20A0, temp);
321 for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
322 dev = calloc (sizeof (*dev), 1);
324 printf ("%s: mv_enet%d allocation failure, %s\n",
325 __FUNCTION__, devnum, "eth_device structure");
329 /* must be less than NAMESIZE (16) */
330 sprintf (dev->name, "mv_enet%d", devnum);
333 printf ("Initializing %s\n", dev->name);
336 /* Extract the MAC address from the environment */
350 default: /* this should never happen */
351 printf ("%s: Invalid device number %d\n",
352 __FUNCTION__, devnum);
356 temp = getenv_r (s, buf, sizeof (buf));
357 s = (temp > 0) ? buf : NULL;
360 printf ("Setting MAC %d to %s\n", devnum, s);
362 for (x = 0; x < 6; ++x) {
363 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
365 s = (*e) ? e + 1 : e;
367 /* ronen - set the MAC addr in the HW */
368 eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
370 dev->init = (void *) db64460_eth_probe;
371 dev->halt = (void *) ethernet_phy_reset;
372 dev->send = (void *) db64460_eth_transmit;
373 dev->recv = (void *) db64460_eth_poll;
375 ethernet_private = calloc (sizeof (*ethernet_private), 1);
376 dev->priv = (void *)ethernet_private;
377 if (!ethernet_private) {
378 printf ("%s: %s allocation failure, %s\n",
379 __FUNCTION__, dev->name,
380 "Private Device Structure");
384 /* start with an zeroed ETH_PORT_INFO */
385 memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
386 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
388 /* set pointer to memory for stats data structure etc... */
389 port_private = calloc (sizeof (*ethernet_private), 1);
390 ethernet_private->port_private = (void *)port_private;
392 printf ("%s: %s allocation failure, %s\n",
393 __FUNCTION__, dev->name,
394 "Port Private Device Structure");
396 free (ethernet_private);
401 port_private->stats =
402 calloc (sizeof (struct net_device_stats), 1);
403 if (!port_private->stats) {
404 printf ("%s: %s allocation failure, %s\n",
405 __FUNCTION__, dev->name,
406 "Net stat Structure");
409 free (ethernet_private);
413 memset (ethernet_private->port_private, 0,
414 sizeof (struct mv64460_eth_priv));
417 ethernet_private->port_num = ETH_0;
420 ethernet_private->port_num = ETH_1;
423 ethernet_private->port_num = ETH_2;
426 printf ("Invalid device number %d\n", devnum);
430 port_private->port_num = devnum;
432 * Read MIB counter on the GT in order to reset them,
433 * then zero all the stats fields in memory
435 mv64460_eth_update_stat (dev);
436 memset (port_private->stats, 0,
437 sizeof (struct net_device_stats));
438 /* Extract the MAC address from the environment */
452 default: /* this should never happen */
453 printf ("%s: Invalid device number %d\n",
454 __FUNCTION__, devnum);
458 temp = getenv_r (s, buf, sizeof (buf));
459 s = (temp > 0) ? buf : NULL;
462 printf ("Setting MAC %d to %s\n", devnum, s);
464 for (x = 0; x < 6; ++x) {
465 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
467 s = (*e) ? e + 1 : e;
470 DP (printf ("Allocating descriptor and buffer rings\n"));
472 ethernet_private->p_rx_desc_area_base[0] =
473 (ETH_RX_DESC *) memalign (16,
474 RX_DESC_ALIGNED_SIZE *
475 MV64460_RX_QUEUE_SIZE + 1);
476 ethernet_private->p_tx_desc_area_base[0] =
477 (ETH_TX_DESC *) memalign (16,
478 TX_DESC_ALIGNED_SIZE *
479 MV64460_TX_QUEUE_SIZE + 1);
481 ethernet_private->p_rx_buffer_base[0] =
482 (char *) memalign (16,
483 MV64460_RX_QUEUE_SIZE *
484 MV64460_TX_BUFFER_SIZE + 1);
485 ethernet_private->p_tx_buffer_base[0] =
486 (char *) memalign (16,
487 MV64460_RX_QUEUE_SIZE *
488 MV64460_TX_BUFFER_SIZE + 1);
491 /* DEBUG OUTPUT prints adresses of globals */
496 miiphy_register(dev->name, mv_miiphy_read, mv_miiphy_write);
498 DP (printf ("%s: exit\n", __FUNCTION__));
502 /**********************************************************************
505 * This function is called when openning the network device. The function
506 * should initialize all the hardware, initialize cyclic Rx/Tx
507 * descriptors chain and buffers and allocate an IRQ to the network
510 * Input : a pointer to the network device structure
511 * / / ronen - changed the output to match net/eth.c needs
512 * Output : nonzero of success , zero if fails.
514 **********************************************************************/
516 int mv64460_eth_open (struct eth_device *dev)
518 return (mv64460_eth_real_open (dev));
521 /* Helper function for mv64460_eth_open */
522 static int mv64460_eth_real_open (struct eth_device *dev)
526 ETH_PORT_INFO *ethernet_private;
527 struct mv64460_eth_priv *port_private;
528 unsigned int port_num;
536 ethernet_private = (ETH_PORT_INFO *) dev->priv;
537 /* ronen - when we update the MAC env params we only update dev->enetaddr
538 see ./net/eth.c eth_set_enetaddr() */
539 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
542 (struct mv64460_eth_priv *) ethernet_private->port_private;
543 port_num = port_private->port_num;
546 MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
549 /* Clear the ethernet port interrupts */
550 MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
551 MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
553 /* Unmask RX buffer and TX end interrupt */
554 MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num),
555 INT_CAUSE_UNMASK_ALL);
557 /* Unmask phy and link status changes interrupts */
558 MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
559 INT_CAUSE_UNMASK_ALL_EXT);
561 /* Set phy address of the port */
562 ethernet_private->port_phy_addr = 0x1 + (port_num << 1);
563 reg = ethernet_private->port_phy_addr;
565 /* Activate the DMA channels etc */
566 eth_port_init (ethernet_private);
568 /* "Allocate" setup TX rings */
570 for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
573 port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE;
574 size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
575 ethernet_private->tx_desc_area_size[queue] = size;
577 /* first clear desc area completely */
578 memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
579 0, ethernet_private->tx_desc_area_size[queue]);
581 /* initialize tx desc ring with low level driver */
582 if (ether_init_tx_desc_ring
583 (ethernet_private, ETH_Q0,
584 port_private->tx_ring_size[queue],
585 MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
586 (unsigned int) ethernet_private->
587 p_tx_desc_area_base[queue],
588 (unsigned int) ethernet_private->
589 p_tx_buffer_base[queue]) == false)
590 printf ("### Error initializing TX Ring\n");
593 /* "Allocate" setup RX rings */
594 for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
597 /* Meantime RX Ring are fixed - but must be configurable by user */
598 port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE;
599 size = (port_private->rx_ring_size[queue] *
600 RX_DESC_ALIGNED_SIZE);
601 ethernet_private->rx_desc_area_size[queue] = size;
603 /* first clear desc area completely */
604 memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
605 0, ethernet_private->rx_desc_area_size[queue]);
606 if ((ether_init_rx_desc_ring
607 (ethernet_private, ETH_Q0,
608 port_private->rx_ring_size[queue],
609 MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
610 (unsigned int) ethernet_private->
611 p_rx_desc_area_base[queue],
612 (unsigned int) ethernet_private->
613 p_rx_buffer_base[queue])) == false)
614 printf ("### Error initializing RX Ring\n");
617 eth_port_start (ethernet_private);
619 /* Set maximum receive buffer to 9700 bytes */
620 MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num),
623 (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num))
627 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
628 * disable the leaky bucket mechanism .
631 MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
632 port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
634 #if defined(CONFIG_PHY_RESET)
636 * Reset the phy, only if its the first time through
637 * otherwise, just check the speeds & feeds
639 if (port_private->first_init == 0) {
640 port_private->first_init = 1;
641 ethernet_phy_reset (port_num);
643 /* Start/Restart autonegotiation */
644 phy_setup_aneg (dev->name, reg);
647 #endif /* defined(CONFIG_PHY_RESET) */
649 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
652 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
654 if ((reg_short & PHY_BMSR_AUTN_ABLE)
655 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
656 puts ("Waiting for PHY auto negotiation to complete");
658 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
662 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
663 puts (" TIMEOUT !\n");
667 if ((i++ % 1000) == 0) {
670 udelay (1000); /* 1 ms */
671 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
675 udelay (500000); /* another 500 ms (results in faster booting) */
678 speed = miiphy_speed (dev->name, reg);
679 duplex = miiphy_duplex (dev->name, reg);
681 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
682 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
684 port_private->eth_running = MAGIC_ETH_RUNNING;
689 static int mv64460_eth_free_tx_rings (struct eth_device *dev)
692 ETH_PORT_INFO *ethernet_private;
693 struct mv64460_eth_priv *port_private;
694 unsigned int port_num;
695 volatile ETH_TX_DESC *p_tx_curr_desc;
697 ethernet_private = (ETH_PORT_INFO *) dev->priv;
699 (struct mv64460_eth_priv *) ethernet_private->port_private;
700 port_num = port_private->port_num;
703 MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
707 DP (printf ("Clearing previously allocated TX queues... "));
708 for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
709 /* Free on TX rings */
710 for (p_tx_curr_desc =
711 ethernet_private->p_tx_desc_area_base[queue];
712 ((unsigned int) p_tx_curr_desc <= (unsigned int)
713 ethernet_private->p_tx_desc_area_base[queue] +
714 ethernet_private->tx_desc_area_size[queue]);
716 (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
717 TX_DESC_ALIGNED_SIZE)) {
718 /* this is inside for loop */
719 if (p_tx_curr_desc->return_info != 0) {
720 p_tx_curr_desc->return_info = 0;
721 DP (printf ("freed\n"));
724 DP (printf ("Done\n"));
729 static int mv64460_eth_free_rx_rings (struct eth_device *dev)
732 ETH_PORT_INFO *ethernet_private;
733 struct mv64460_eth_priv *port_private;
734 unsigned int port_num;
735 volatile ETH_RX_DESC *p_rx_curr_desc;
737 ethernet_private = (ETH_PORT_INFO *) dev->priv;
739 (struct mv64460_eth_priv *) ethernet_private->port_private;
740 port_num = port_private->port_num;
744 MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
748 DP (printf ("Clearing previously allocated RX queues... "));
749 for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
750 /* Free preallocated skb's on RX rings */
751 for (p_rx_curr_desc =
752 ethernet_private->p_rx_desc_area_base[queue];
753 (((unsigned int) p_rx_curr_desc <
754 ((unsigned int) ethernet_private->
755 p_rx_desc_area_base[queue] +
756 ethernet_private->rx_desc_area_size[queue])));
758 (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
759 RX_DESC_ALIGNED_SIZE)) {
760 if (p_rx_curr_desc->return_info != 0) {
761 p_rx_curr_desc->return_info = 0;
762 DP (printf ("freed\n"));
765 DP (printf ("Done\n"));
770 /**********************************************************************
773 * This function is used when closing the network device.
774 * It updates the hardware,
775 * release all memory that holds buffers and descriptors and release the IRQ.
776 * Input : a pointer to the device structure
777 * Output : zero if success , nonzero if fails
778 *********************************************************************/
780 int mv64460_eth_stop (struct eth_device *dev)
782 ETH_PORT_INFO *ethernet_private;
783 struct mv64460_eth_priv *port_private;
784 unsigned int port_num;
786 ethernet_private = (ETH_PORT_INFO *) dev->priv;
788 (struct mv64460_eth_priv *) ethernet_private->port_private;
789 port_num = port_private->port_num;
791 /* Disable all gigE address decoder */
792 MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
793 DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
794 mv64460_eth_real_stop (dev);
799 /* Helper function for mv64460_eth_stop */
801 static int mv64460_eth_real_stop (struct eth_device *dev)
803 ETH_PORT_INFO *ethernet_private;
804 struct mv64460_eth_priv *port_private;
805 unsigned int port_num;
807 ethernet_private = (ETH_PORT_INFO *) dev->priv;
809 (struct mv64460_eth_priv *) ethernet_private->port_private;
810 port_num = port_private->port_num;
812 mv64460_eth_free_tx_rings (dev);
813 mv64460_eth_free_rx_rings (dev);
815 eth_port_reset (ethernet_private->port_num);
816 /* Disable ethernet port interrupts */
817 MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
818 MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
819 /* Mask RX buffer and TX end interrupt */
820 MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0);
821 /* Mask phy and link status changes interrupts */
822 MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
823 MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH,
825 /* Print Network statistics */
826 #ifndef UPDATE_STATS_BY_SOFTWARE
828 * Print statistics (only if ethernet is running),
829 * then zero all the stats fields in memory
831 if (port_private->eth_running == MAGIC_ETH_RUNNING) {
832 port_private->eth_running = 0;
833 mv64460_eth_print_stat (dev);
835 memset (port_private->stats, 0, sizeof (struct net_device_stats));
837 DP (printf ("\nEthernet stopped ... \n"));
842 /**********************************************************************
843 * mv64460_eth_start_xmit
845 * This function is queues a packet in the Tx descriptor for
848 * Input : skb - a pointer to socket buffer
849 * dev - a pointer to the required port
851 * Output : zero upon success
852 **********************************************************************/
854 int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
857 ETH_PORT_INFO *ethernet_private;
858 struct mv64460_eth_priv *port_private;
859 unsigned int port_num;
861 ETH_FUNC_RET_STATUS status;
862 struct net_device_stats *stats;
863 ETH_FUNC_RET_STATUS release_result;
865 ethernet_private = (ETH_PORT_INFO *) dev->priv;
867 (struct mv64460_eth_priv *) ethernet_private->port_private;
868 port_num = port_private->port_num;
870 stats = port_private->stats;
872 /* Update packet info data structure */
873 pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
874 pkt_info.byte_cnt = dataSize;
875 pkt_info.buf_ptr = (unsigned int) dataPtr;
876 pkt_info.return_info = 0;
878 status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
879 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
880 printf ("Error on transmitting packet ..");
881 if (status == ETH_QUEUE_FULL)
882 printf ("ETH Queue is full. \n");
883 if (status == ETH_QUEUE_LAST_RESOURCE)
884 printf ("ETH Queue: using last available resource. \n");
888 /* Update statistics and start of transmittion time */
889 stats->tx_bytes += dataSize;
892 /* Check if packet(s) is(are) transmitted correctly (release everything) */
895 eth_tx_return_desc (ethernet_private, ETH_Q0,
897 switch (release_result) {
899 DP (printf ("descriptor released\n"));
900 if (pkt_info.cmd_sts & BIT0) {
901 printf ("Error in TX\n");
906 DP (printf ("transmission still in process\n"));
910 printf ("routine can not access Tx desc ring\n");
914 DP (printf ("the routine has nothing to release\n"));
916 default: /* should not happen */
919 } while (release_result == ETH_OK);
921 return 0; /* success */
924 return 1; /* Failed - higher layers will free the skb */
927 /**********************************************************************
928 * mv64460_eth_receive
930 * This function is forward packets that are received from the port's
931 * queues toward kernel core or FastRoute them to another interface.
933 * Input : dev - a pointer to the required interface
934 * max - maximum number to receive (0 means unlimted)
936 * Output : number of served packets
937 **********************************************************************/
939 int mv64460_eth_receive (struct eth_device *dev)
941 ETH_PORT_INFO *ethernet_private;
942 struct mv64460_eth_priv *port_private;
943 unsigned int port_num;
945 struct net_device_stats *stats;
947 ethernet_private = (ETH_PORT_INFO *) dev->priv;
948 port_private = (struct mv64460_eth_priv *) ethernet_private->port_private;
949 port_num = port_private->port_num;
950 stats = port_private->stats;
952 while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == ETH_OK)) {
954 if (pkt_info.byte_cnt != 0) {
955 printf ("%s: Received %d byte Packet @ 0x%x\n",
956 __FUNCTION__, pkt_info.byte_cnt,
958 if(pkt_info.buf_ptr != 0){
959 for(i=0; i < pkt_info.byte_cnt; i++){
963 printf("%02x", ((char*)pkt_info.buf_ptr)[i]);
969 /* Update statistics. Note byte count includes 4 byte CRC count */
971 stats->rx_bytes += pkt_info.byte_cnt;
974 * In case received a packet without first / last bits on OR the error
975 * summary bit is on, the packets needs to be dropeed.
978 cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
979 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
980 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
983 printf ("Received packet spread on multiple descriptors\n");
985 /* Is this caused by an error ? */
986 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
990 /* free these descriptors again without forwarding them to the higher layers */
991 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
992 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
994 if (eth_rx_return_buff
995 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
996 printf ("Error while returning the RX Desc to Ring\n");
998 DP (printf ("RX Desc returned to Ring\n"));
1000 /* /free these descriptors again */
1003 /* !!! call higher layer processing */
1005 printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
1007 /* let the upper layer handle the packet */
1008 NetReceive ((uchar *) pkt_info.buf_ptr,
1009 (int) pkt_info.byte_cnt);
1011 /* **************************************************************** */
1012 /* free descriptor */
1013 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
1014 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
1015 DP (printf ("RX: pkt_info.buf_ptr = %x\n", pkt_info.buf_ptr));
1016 if (eth_rx_return_buff
1017 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
1018 printf ("Error while returning the RX Desc to Ring\n");
1020 DP (printf ("RX: Desc returned to Ring\n"));
1023 /* **************************************************************** */
1027 mv64460_eth_get_stats (dev); /* update statistics */
1031 /**********************************************************************
1032 * mv64460_eth_get_stats
1034 * Returns a pointer to the interface statistics.
1036 * Input : dev - a pointer to the required interface
1038 * Output : a pointer to the interface's statistics
1039 **********************************************************************/
1041 static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev)
1043 ETH_PORT_INFO *ethernet_private;
1044 struct mv64460_eth_priv *port_private;
1045 unsigned int port_num;
1047 ethernet_private = (ETH_PORT_INFO *) dev->priv;
1049 (struct mv64460_eth_priv *) ethernet_private->port_private;
1050 port_num = port_private->port_num;
1052 mv64460_eth_update_stat (dev);
1054 return port_private->stats;
1058 /**********************************************************************
1059 * mv64460_eth_update_stat
1061 * Update the statistics structure in the private data structure
1063 * Input : pointer to ethernet interface network device structure
1065 **********************************************************************/
1067 static void mv64460_eth_update_stat (struct eth_device *dev)
1069 ETH_PORT_INFO *ethernet_private;
1070 struct mv64460_eth_priv *port_private;
1071 struct net_device_stats *stats;
1072 unsigned int port_num;
1073 volatile unsigned int dummy;
1075 ethernet_private = (ETH_PORT_INFO *) dev->priv;
1077 (struct mv64460_eth_priv *) ethernet_private->port_private;
1078 port_num = port_private->port_num;
1079 stats = port_private->stats;
1081 /* These are false updates */
1082 stats->rx_packets += (unsigned long)
1083 eth_read_mib_counter (ethernet_private->port_num,
1084 ETH_MIB_GOOD_FRAMES_RECEIVED);
1085 stats->tx_packets += (unsigned long)
1086 eth_read_mib_counter (ethernet_private->port_num,
1087 ETH_MIB_GOOD_FRAMES_SENT);
1088 stats->rx_bytes += (unsigned long)
1089 eth_read_mib_counter (ethernet_private->port_num,
1090 ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
1092 * Ideally this should be as follows -
1094 * stats->rx_bytes += stats->rx_bytes +
1095 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
1096 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
1098 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
1099 * is just a dummy read for proper work of the GigE port
1101 dummy = eth_read_mib_counter (ethernet_private->port_num,
1102 ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
1103 stats->tx_bytes += (unsigned long)
1104 eth_read_mib_counter (ethernet_private->port_num,
1105 ETH_MIB_GOOD_OCTETS_SENT_LOW);
1106 dummy = eth_read_mib_counter (ethernet_private->port_num,
1107 ETH_MIB_GOOD_OCTETS_SENT_HIGH);
1108 stats->rx_errors += (unsigned long)
1109 eth_read_mib_counter (ethernet_private->port_num,
1110 ETH_MIB_MAC_RECEIVE_ERROR);
1112 /* Rx dropped is for received packet with CRC error */
1113 stats->rx_dropped +=
1114 (unsigned long) eth_read_mib_counter (ethernet_private->
1116 ETH_MIB_BAD_CRC_EVENT);
1117 stats->multicast += (unsigned long)
1118 eth_read_mib_counter (ethernet_private->port_num,
1119 ETH_MIB_MULTICAST_FRAMES_RECEIVED);
1120 stats->collisions +=
1121 (unsigned long) eth_read_mib_counter (ethernet_private->
1123 ETH_MIB_COLLISION) +
1124 (unsigned long) eth_read_mib_counter (ethernet_private->
1126 ETH_MIB_LATE_COLLISION);
1127 /* detailed rx errors */
1128 stats->rx_length_errors +=
1129 (unsigned long) eth_read_mib_counter (ethernet_private->
1131 ETH_MIB_UNDERSIZE_RECEIVED)
1133 (unsigned long) eth_read_mib_counter (ethernet_private->
1135 ETH_MIB_OVERSIZE_RECEIVED);
1136 /* detailed tx errors */
1139 #ifndef UPDATE_STATS_BY_SOFTWARE
1140 /**********************************************************************
1141 * mv64460_eth_print_stat
1143 * Update the statistics structure in the private data structure
1145 * Input : pointer to ethernet interface network device structure
1147 **********************************************************************/
1149 static void mv64460_eth_print_stat (struct eth_device *dev)
1151 ETH_PORT_INFO *ethernet_private;
1152 struct mv64460_eth_priv *port_private;
1153 struct net_device_stats *stats;
1154 unsigned int port_num;
1156 ethernet_private = (ETH_PORT_INFO *) dev->priv;
1158 (struct mv64460_eth_priv *) ethernet_private->port_private;
1159 port_num = port_private->port_num;
1160 stats = port_private->stats;
1162 /* These are false updates */
1163 printf ("\n### Network statistics: ###\n");
1164 printf ("--------------------------\n");
1165 printf (" Packets received: %ld\n", stats->rx_packets);
1166 printf (" Packets send: %ld\n", stats->tx_packets);
1167 printf (" Received bytes: %ld\n", stats->rx_bytes);
1168 printf (" Send bytes: %ld\n", stats->tx_bytes);
1169 if (stats->rx_errors != 0)
1170 printf (" Rx Errors: %ld\n",
1172 if (stats->rx_dropped != 0)
1173 printf (" Rx dropped (CRC Errors): %ld\n",
1175 if (stats->multicast != 0)
1176 printf (" Rx mulicast frames: %ld\n",
1178 if (stats->collisions != 0)
1179 printf (" No. of collisions: %ld\n",
1181 if (stats->rx_length_errors != 0)
1182 printf (" Rx length errors: %ld\n",
1183 stats->rx_length_errors);
1187 /**************************************************************************
1188 *network_start - Network Kick Off Routine UBoot
1191 **************************************************************************/
1193 bool db64460_eth_start (struct eth_device *dev)
1195 return (mv64460_eth_open (dev)); /* calls real open */
1198 /*************************************************************************
1199 **************************************************************************
1200 **************************************************************************
1201 * The second part is the low level driver of the gigE ethernet ports. *
1202 **************************************************************************
1203 **************************************************************************
1204 *************************************************************************/
1206 * based on Linux code
1207 * arch/ppc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
1208 * Copyright (C) 2002 rabeeh@galileo.co.il
1210 * This program is free software; you can redistribute it and/or
1211 * modify it under the terms of the GNU General Public License
1212 * as published by the Free Software Foundation; either version 2
1213 * of the License, or (at your option) any later version.
1215 * This program is distributed in the hope that it will be useful,
1216 * but WITHOUT ANY WARRANTY; without even the implied warranty of
1217 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1218 * GNU General Public License for more details.
1220 * You should have received a copy of the GNU General Public License
1221 * along with this program; if not, write to the Free Software
1222 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
1226 /********************************************************************************
1227 * Marvell's Gigabit Ethernet controller low level driver
1230 * This file introduce low level API to Marvell's Gigabit Ethernet
1231 * controller. This Gigabit Ethernet Controller driver API controls
1232 * 1) Operations (i.e. port init, start, reset etc').
1233 * 2) Data flow (i.e. port send, receive etc').
1234 * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
1236 * This struct includes user configuration information as well as
1237 * driver internal data needed for its operations.
1239 * Supported Features:
1240 * - This low level driver is OS independent. Allocating memory for
1241 * the descriptor rings and buffers are not within the scope of
1243 * - The user is free from Rx/Tx queue managing.
1244 * - This low level driver introduce functionality API that enable
1245 * the to operate Marvell's Gigabit Ethernet Controller in a
1247 * - Simple Gigabit Ethernet port operation API.
1248 * - Simple Gigabit Ethernet port data flow API.
1249 * - Data flow and operation API support per queue functionality.
1250 * - Support cached descriptors for better performance.
1251 * - Enable access to all four DRAM banks and internal SRAM memory
1253 * - PHY access and control API.
1254 * - Port control register configuration API.
1255 * - Full control over Unicast and Multicast MAC configurations.
1259 * Initialization phase
1260 * This phase complete the initialization of the ETH_PORT_INFO
1262 * User information regarding port configuration has to be set
1263 * prior to calling the port initialization routine. For example,
1264 * the user has to assign the port_phy_addr field which is board
1265 * depended parameter.
1266 * In this phase any port Tx/Rx activity is halted, MIB counters
1267 * are cleared, PHY address is set according to user parameter and
1268 * access to DRAM and internal SRAM memory spaces.
1270 * Driver ring initialization
1271 * Allocating memory for the descriptor rings and buffers is not
1272 * within the scope of this driver. Thus, the user is required to
1273 * allocate memory for the descriptors ring and buffers. Those
1274 * memory parameters are used by the Rx and Tx ring initialization
1275 * routines in order to curve the descriptor linked list in a form
1277 * Note: Pay special attention to alignment issues when using
1278 * cached descriptors/buffers. In this phase the driver store
1279 * information in the ETH_PORT_INFO struct regarding each queue
1283 * This phase prepares the Ethernet port for Rx and Tx activity.
1284 * It uses the information stored in the ETH_PORT_INFO struct to
1285 * initialize the various port registers.
1288 * All packet references to/from the driver are done using PKT_INFO
1290 * This struct is a unified struct used with Rx and Tx operations.
1291 * This way the user is not required to be familiar with neither
1292 * Tx nor Rx descriptors structures.
1293 * The driver's descriptors rings are management by indexes.
1294 * Those indexes controls the ring resources and used to indicate
1295 * a SW resource error:
1297 * This index points to the current available resource for use. For
1298 * example in Rx process this index will point to the descriptor
1299 * that will be passed to the user upon calling the receive routine.
1300 * In Tx process, this index will point to the descriptor
1301 * that will be assigned with the user packet info and transmitted.
1303 * This index points to the descriptor that need to restore its
1304 * resources. For example in Rx process, using the Rx buffer return
1305 * API will attach the buffer returned in packet info to the
1306 * descriptor pointed by 'used'. In Tx process, using the Tx
1307 * descriptor return will merely return the user packet info with
1308 * the command status of the transmitted buffer pointed by the
1309 * 'used' index. Nevertheless, it is essential to use this routine
1310 * to update the 'used' index.
1312 * This index supports Tx Scatter-Gather. It points to the first
1313 * descriptor of a packet assembled of multiple buffers. For example
1314 * when in middle of Such packet we have a Tx resource error the
1315 * 'curr' index get the value of 'first' to indicate that the ring
1316 * returned to its state before trying to transmit this packet.
1318 * Receive operation:
1319 * The eth_port_receive API set the packet information struct,
1320 * passed by the caller, with received information from the
1321 * 'current' SDMA descriptor.
1322 * It is the user responsibility to return this resource back
1323 * to the Rx descriptor ring to enable the reuse of this source.
1324 * Return Rx resource is done using the eth_rx_return_buff API.
1326 * Transmit operation:
1327 * The eth_port_send API supports Scatter-Gather which enables to
1328 * send a packet spanned over multiple buffers. This means that
1329 * for each packet info structure given by the user and put into
1330 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1331 * bit will be set in the packet info command status field. This
1332 * API also consider restriction regarding buffer alignments and
1334 * The user must return a Tx resource after ensuring the buffer
1335 * has been transmitted to enable the Tx ring indexes to update.
1338 * This device is on-board. No jumper diagram is necessary.
1340 * EXTERNAL INTERFACE
1342 * Prior to calling the initialization routine eth_port_init() the user
1343 * must set the following fields under ETH_PORT_INFO struct:
1344 * port_num User Ethernet port number.
1345 * port_phy_addr User PHY address of Ethernet port.
1346 * port_mac_addr[6] User defined port MAC address.
1347 * port_config User port configuration value.
1348 * port_config_extend User port config extend value.
1349 * port_sdma_config User port SDMA config value.
1350 * port_serial_control User port serial control value.
1351 * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
1352 * *port_private User scratch pad for user specific data structures.
1354 * This driver introduce a set of default values:
1355 * PORT_CONFIG_VALUE Default port configuration value
1356 * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
1357 * PORT_SDMA_CONFIG_VALUE Default sdma control value
1358 * PORT_SERIAL_CONTROL_VALUE Default port serial control value
1360 * This driver data flow is done using the PKT_INFO struct which is
1361 * a unified struct for Rx and Tx operations:
1362 * byte_cnt Tx/Rx descriptor buffer byte count.
1363 * l4i_chk CPU provided TCP Checksum. For Tx operation only.
1364 * cmd_sts Tx/Rx descriptor command status.
1365 * buf_ptr Tx/Rx descriptor buffer pointer.
1366 * return_info Tx/Rx user resource return information.
1369 * EXTERNAL SUPPORT REQUIREMENTS
1371 * This driver requires the following external support:
1373 * D_CACHE_FLUSH_LINE (address, address offset)
1375 * This macro applies assembly code to flush and invalidate cache
1377 * address - address base.
1378 * address offset - address offset
1383 * This macro applies assembly code to flush the CPU pipeline.
1385 *******************************************************************************/
1389 /* SDMA command macros */
1390 #define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
1391 MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
1393 #define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
1394 MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
1395 (1 << (8 + tx_queue)))
1397 #define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
1398 MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
1400 #define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
1401 MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
1403 #define CURR_RFD_GET(p_curr_desc, queue) \
1404 ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
1406 #define CURR_RFD_SET(p_curr_desc, queue) \
1407 (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
1409 #define USED_RFD_GET(p_used_desc, queue) \
1410 ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
1412 #define USED_RFD_SET(p_used_desc, queue)\
1413 (p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
1416 #define CURR_TFD_GET(p_curr_desc, queue) \
1417 ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
1419 #define CURR_TFD_SET(p_curr_desc, queue) \
1420 (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
1422 #define USED_TFD_GET(p_used_desc, queue) \
1423 ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
1425 #define USED_TFD_SET(p_used_desc, queue) \
1426 (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
1428 #define FIRST_TFD_GET(p_first_desc, queue) \
1429 ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
1431 #define FIRST_TFD_SET(p_first_desc, queue) \
1432 (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
1435 /* Macros that save access to desc in order to find next desc pointer */
1436 #define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
1438 #define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
1440 #define LINK_UP_TIMEOUT 100000
1441 #define PHY_BUSY_TIMEOUT 10000000
1446 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
1447 static int ethernet_phy_get (ETH_PORT eth_port_num);
1449 /* Ethernet Port routines */
1450 static void eth_set_access_control (ETH_PORT eth_port_num,
1451 ETH_WIN_PARAM * param);
1452 static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
1453 ETH_QUEUE queue, int option);
1455 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1456 unsigned char mc_byte,
1457 ETH_QUEUE queue, int option);
1458 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1460 ETH_QUEUE queue, int option);
1463 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
1466 void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
1469 typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
1470 u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
1473 u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
1475 if (enable & (1 << bank))
1478 result = MV_REG_READ (MV64460_CS_0_BASE_ADDR);
1480 result = MV_REG_READ (MV64460_CS_1_BASE_ADDR);
1482 result = MV_REG_READ (MV64460_CS_2_BASE_ADDR);
1484 result = MV_REG_READ (MV64460_CS_3_BASE_ADDR);
1485 result &= 0x0000ffff;
1486 result = result << 16;
1490 u32 mv_get_dram_bank_size (MEMORY_BANK bank)
1493 u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
1495 if (enable & (1 << bank))
1498 result = MV_REG_READ (MV64460_CS_0_SIZE);
1500 result = MV_REG_READ (MV64460_CS_1_SIZE);
1502 result = MV_REG_READ (MV64460_CS_2_SIZE);
1504 result = MV_REG_READ (MV64460_CS_3_SIZE);
1506 result &= 0x0000ffff;
1507 result = result << 16;
1511 u32 mv_get_internal_sram_base (void)
1515 result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR);
1516 result &= 0x0000ffff;
1517 result = result << 16;
1521 /*******************************************************************************
1522 * eth_port_init - Initialize the Ethernet port driver
1525 * This function prepares the ethernet port to start its activity:
1526 * 1) Completes the ethernet port driver struct initialization toward port
1528 * 2) Resets the device to a quiescent state in case of warm reboot.
1529 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1530 * 4) Clean MAC tables. The reset status of those tables is unknown.
1531 * 5) Set PHY address.
1532 * Note: Call this routine prior to eth_port_start routine and after setting
1533 * user values in the user fields of Ethernet port control struct (i.e.
1537 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1545 *******************************************************************************/
1546 static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
1549 ETH_WIN_PARAM win_param;
1551 p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
1552 p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
1553 p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
1554 p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
1556 p_eth_port_ctrl->port_rx_queue_command = 0;
1557 p_eth_port_ctrl->port_tx_queue_command = 0;
1559 /* Zero out SW structs */
1560 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1561 CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1562 USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1563 p_eth_port_ctrl->rx_resource_err[queue] = false;
1566 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1567 CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1568 USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1569 FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1570 p_eth_port_ctrl->tx_resource_err[queue] = false;
1573 eth_port_reset (p_eth_port_ctrl->port_num);
1575 /* Set access parameters for DRAM bank 0 */
1576 win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
1577 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1578 win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
1579 #ifndef CONFIG_NOT_COHERENT_CACHE
1580 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1582 win_param.high_addr = 0;
1584 win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
1585 win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
1586 if (win_param.size == 0)
1587 win_param.enable = 0;
1589 win_param.enable = 1; /* Enable the access */
1590 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1592 /* Set the access control for address window (EPAPR) READ & WRITE */
1593 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1595 /* Set access parameters for DRAM bank 1 */
1596 win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
1597 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1598 win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
1599 #ifndef CONFIG_NOT_COHERENT_CACHE
1600 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1602 win_param.high_addr = 0;
1604 win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
1605 win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
1606 if (win_param.size == 0)
1607 win_param.enable = 0;
1609 win_param.enable = 1; /* Enable the access */
1610 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1612 /* Set the access control for address window (EPAPR) READ & WRITE */
1613 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1615 /* Set access parameters for DRAM bank 2 */
1616 win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
1617 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1618 win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
1619 #ifndef CONFIG_NOT_COHERENT_CACHE
1620 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1622 win_param.high_addr = 0;
1624 win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
1625 win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
1626 if (win_param.size == 0)
1627 win_param.enable = 0;
1629 win_param.enable = 1; /* Enable the access */
1630 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1632 /* Set the access control for address window (EPAPR) READ & WRITE */
1633 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1635 /* Set access parameters for DRAM bank 3 */
1636 win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
1637 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1638 win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
1639 #ifndef CONFIG_NOT_COHERENT_CACHE
1640 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1642 win_param.high_addr = 0;
1644 win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
1645 win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
1646 if (win_param.size == 0)
1647 win_param.enable = 0;
1649 win_param.enable = 1; /* Enable the access */
1650 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1652 /* Set the access control for address window (EPAPR) READ & WRITE */
1653 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1655 /* Set access parameters for Internal SRAM */
1656 win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
1657 win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
1658 win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
1659 win_param.high_addr = 0;
1660 win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
1661 win_param.size = MV64460_INTERNAL_SRAM_SIZE; /* Get bank size */
1662 win_param.enable = 1; /* Enable the access */
1663 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1665 /* Set the access control for address window (EPAPR) READ & WRITE */
1666 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1668 eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
1670 ethernet_phy_set (p_eth_port_ctrl->port_num,
1671 p_eth_port_ctrl->port_phy_addr);
1677 /*******************************************************************************
1678 * eth_port_start - Start the Ethernet port activity.
1681 * This routine prepares the Ethernet port for Rx and Tx activity:
1682 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1683 * has been initialized a descriptor's ring (using ether_init_tx_desc_ring
1684 * for Tx and ether_init_rx_desc_ring for Rx)
1685 * 2. Initialize and enable the Ethernet configuration port by writing to
1686 * the port's configuration and command registers.
1687 * 3. Initialize and enable the SDMA by writing to the SDMA's
1688 * configuration and command registers.
1689 * After completing these steps, the ethernet port SDMA can starts to
1690 * perform Rx and Tx activities.
1692 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1693 * to calling this function (use ether_init_tx_desc_ring for Tx queues and
1694 * ether_init_rx_desc_ring for Rx queues).
1697 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1700 * Ethernet port is ready to receive and transmit.
1703 * false if the port PHY is not up.
1706 *******************************************************************************/
1707 static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
1710 volatile ETH_TX_DESC *p_tx_curr_desc;
1711 volatile ETH_RX_DESC *p_rx_curr_desc;
1712 unsigned int phy_reg_data;
1713 ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
1716 /* Assignment of Tx CTRP of given queue */
1717 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1718 CURR_TFD_GET (p_tx_curr_desc, queue);
1719 MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
1722 ((unsigned int) p_tx_curr_desc));
1726 /* Assignment of Rx CRDP of given queue */
1727 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1728 CURR_RFD_GET (p_rx_curr_desc, queue);
1729 MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
1732 ((unsigned int) p_rx_curr_desc));
1734 if (p_rx_curr_desc != NULL)
1735 /* Add the assigned Ethernet address to the port's address table */
1736 eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
1737 p_eth_port_ctrl->port_mac_addr,
1741 /* Assign port configuration and command. */
1742 MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
1743 p_eth_port_ctrl->port_config);
1745 MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
1746 p_eth_port_ctrl->port_config_extend);
1748 MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1749 p_eth_port_ctrl->port_serial_control);
1751 MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1752 ETH_SERIAL_PORT_ENABLE);
1754 /* Assign port SDMA configuration */
1755 MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
1756 p_eth_port_ctrl->port_sdma_config);
1758 MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
1759 (eth_port_num), 0x3fffffff);
1760 MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
1761 (eth_port_num), 0x03fffcff);
1762 /* Turn off the port/queue bandwidth limitation */
1763 MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
1765 /* Enable port Rx. */
1766 MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
1767 p_eth_port_ctrl->port_rx_queue_command);
1769 /* Check if link is up */
1770 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
1772 if (!(phy_reg_data & 0x20))
1778 /*******************************************************************************
1779 * eth_port_uc_addr_set - This function Set the port Unicast address.
1782 * This function Set the port Ethernet MAC address.
1785 * ETH_PORT eth_port_num Port number.
1786 * char * p_addr Address to be set
1787 * ETH_QUEUE queue Rx queue number for this MAC address.
1790 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1791 * To set the unicast table with the proper information.
1796 *******************************************************************************/
1797 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
1798 unsigned char *p_addr, ETH_QUEUE queue)
1803 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1804 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
1805 (p_addr[2] << 8) | (p_addr[3] << 0);
1807 MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
1808 MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
1810 /* Accept frames of this address */
1811 eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
1816 /*******************************************************************************
1817 * eth_port_uc_addr - This function Set the port unicast address table
1820 * This function locates the proper entry in the Unicast table for the
1821 * specified MAC nibble and sets its properties according to function
1825 * ETH_PORT eth_port_num Port number.
1826 * unsigned char uc_nibble Unicast MAC Address last nibble.
1827 * ETH_QUEUE queue Rx queue number for this MAC address.
1828 * int option 0 = Add, 1 = remove address.
1831 * This function add/removes MAC addresses from the port unicast address
1835 * true is output succeeded.
1836 * false if option parameter is invalid.
1838 *******************************************************************************/
1839 static bool eth_port_uc_addr (ETH_PORT eth_port_num,
1840 unsigned char uc_nibble,
1841 ETH_QUEUE queue, int option)
1843 unsigned int unicast_reg;
1844 unsigned int tbl_offset;
1845 unsigned int reg_offset;
1847 /* Locate the Unicast table entry */
1848 uc_nibble = (0xf & uc_nibble);
1849 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
1850 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
1853 case REJECT_MAC_ADDR:
1854 /* Clear accepts frame bit at specified unicast DA table entry */
1856 MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
1860 unicast_reg &= (0x0E << (8 * reg_offset));
1862 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
1864 + tbl_offset), unicast_reg);
1867 case ACCEPT_MAC_ADDR:
1868 /* Set accepts frame bit at unicast DA filter table entry */
1870 MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
1874 unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
1876 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
1878 + tbl_offset), unicast_reg);
1889 /*******************************************************************************
1890 * eth_port_mc_addr - Multicast address settings.
1893 * This API controls the MV device MAC multicast support.
1894 * The MV device supports multicast using two tables:
1895 * 1) Special Multicast Table for MAC addresses of the form
1896 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1897 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1898 * Table entries in the DA-Filter table.
1899 * In this case, the function calls eth_port_smc_addr() routine to set the
1900 * Special Multicast Table.
1901 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1902 * is used as an index to the Other Multicast Table entries in the
1904 * In this case, the function calculates the CRC-8bit value and calls
1905 * eth_port_omc_addr() routine to set the Other Multicast Table.
1907 * ETH_PORT eth_port_num Port number.
1908 * unsigned char *p_addr Unicast MAC Address.
1909 * ETH_QUEUE queue Rx queue number for this MAC address.
1910 * int option 0 = Add, 1 = remove address.
1916 * true is output succeeded.
1917 * false if add_address_table_entry( ) failed.
1919 *******************************************************************************/
1920 static void eth_port_mc_addr (ETH_PORT eth_port_num,
1921 unsigned char *p_addr,
1922 ETH_QUEUE queue, int option)
1926 unsigned char crc_result = 0;
1932 if ((p_addr[0] == 0x01) &&
1933 (p_addr[1] == 0x00) &&
1934 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
1936 eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
1938 /* Calculate CRC-8 out of the given address */
1939 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1940 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1941 (p_addr[4] << 8) | (p_addr[5] << 0);
1943 for (i = 0; i < 32; i++)
1944 mac_array[i] = (mac_l >> i) & 0x1;
1945 for (i = 32; i < 48; i++)
1946 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1949 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
1950 mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
1951 mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
1952 mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1953 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1954 mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
1955 mac_array[6] ^ mac_array[0];
1957 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1958 mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
1959 mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
1960 mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1961 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
1962 mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
1963 mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
1964 mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1965 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
1968 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
1969 mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
1970 mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
1971 mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1972 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
1973 mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
1974 mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
1975 mac_array[2] ^ mac_array[1] ^ mac_array[0];
1977 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
1978 mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
1979 mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
1980 mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1981 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
1982 mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
1983 mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
1984 mac_array[2] ^ mac_array[1];
1986 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1987 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
1988 mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
1989 mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1990 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
1991 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1992 mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
1995 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
1996 mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
1997 mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
1998 mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1999 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
2000 mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
2001 mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
2004 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
2005 mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
2006 mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
2007 mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2008 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
2009 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
2010 mac_array[6] ^ mac_array[5] ^ mac_array[4];
2012 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
2013 mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
2014 mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
2015 mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2016 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
2017 mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
2018 mac_array[6] ^ mac_array[5];
2020 for (i = 0; i < 8; i++)
2021 crc_result = crc_result | (crc[i] << i);
2023 eth_port_omc_addr (eth_port_num, crc_result, queue, option);
2028 /*******************************************************************************
2029 * eth_port_smc_addr - Special Multicast address settings.
2032 * This routine controls the MV device special MAC multicast support.
2033 * The Special Multicast Table for MAC addresses supports MAC of the form
2034 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
2035 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2036 * Table entries in the DA-Filter table.
2037 * This function set the Special Multicast Table appropriate entry
2038 * according to the argument given.
2041 * ETH_PORT eth_port_num Port number.
2042 * unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
2043 * ETH_QUEUE queue Rx queue number for this MAC address.
2044 * int option 0 = Add, 1 = remove address.
2050 * true is output succeeded.
2051 * false if option parameter is invalid.
2053 *******************************************************************************/
2054 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
2055 unsigned char mc_byte,
2056 ETH_QUEUE queue, int option)
2058 unsigned int smc_table_reg;
2059 unsigned int tbl_offset;
2060 unsigned int reg_offset;
2062 /* Locate the SMC table entry */
2063 tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
2064 reg_offset = mc_byte % 4; /* Entry offset within the above register */
2068 case REJECT_MAC_ADDR:
2069 /* Clear accepts frame bit at specified Special DA table entry */
2071 MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
2072 smc_table_reg &= (0x0E << (8 * reg_offset));
2074 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
2077 case ACCEPT_MAC_ADDR:
2078 /* Set accepts frame bit at specified Special DA table entry */
2080 MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
2081 smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
2083 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
2092 /*******************************************************************************
2093 * eth_port_omc_addr - Multicast address settings.
2096 * This routine controls the MV device Other MAC multicast support.
2097 * The Other Multicast Table is used for multicast of another type.
2098 * A CRC-8bit is used as an index to the Other Multicast Table entries
2099 * in the DA-Filter table.
2100 * The function gets the CRC-8bit value from the calling routine and
2101 * set the Other Multicast Table appropriate entry according to the
2102 * CRC-8 argument given.
2105 * ETH_PORT eth_port_num Port number.
2106 * unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
2107 * ETH_QUEUE queue Rx queue number for this MAC address.
2108 * int option 0 = Add, 1 = remove address.
2114 * true is output succeeded.
2115 * false if option parameter is invalid.
2117 *******************************************************************************/
2118 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
2120 ETH_QUEUE queue, int option)
2122 unsigned int omc_table_reg;
2123 unsigned int tbl_offset;
2124 unsigned int reg_offset;
2126 /* Locate the OMC table entry */
2127 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
2128 reg_offset = crc8 % 4; /* Entry offset within the above register */
2132 case REJECT_MAC_ADDR:
2133 /* Clear accepts frame bit at specified Other DA table entry */
2135 MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
2136 omc_table_reg &= (0x0E << (8 * reg_offset));
2138 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
2141 case ACCEPT_MAC_ADDR:
2142 /* Set accepts frame bit at specified Other DA table entry */
2144 MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
2145 omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
2147 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
2157 /*******************************************************************************
2158 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2161 * Go through all the DA filter tables (Unicast, Special Multicast & Other
2162 * Multicast) and set each entry to 0.
2165 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2168 * Multicast and Unicast packets are rejected.
2173 *******************************************************************************/
2174 static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
2178 /* Clear DA filter unicast table (Ex_dFUT) */
2179 for (table_index = 0; table_index <= 0xC; table_index += 4)
2180 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
2181 (eth_port_num) + table_index), 0);
2183 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2184 /* Clear DA filter special multicast table (Ex_dFSMT) */
2185 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
2186 /* Clear DA filter other multicast table (Ex_dFOMT) */
2187 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
2191 /*******************************************************************************
2192 * eth_clear_mib_counters - Clear all MIB counters
2195 * This function clears all MIB counters of a specific ethernet port.
2196 * A read from the MIB counter will reset the counter.
2199 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2202 * After reading all MIB counters, the counters resets.
2205 * MIB counter value.
2207 *******************************************************************************/
2208 static void eth_clear_mib_counters (ETH_PORT eth_port_num)
2213 /* Perform dummy reads from MIB counters */
2214 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2216 dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE
2217 (eth_port_num) + i));
2222 /*******************************************************************************
2223 * eth_read_mib_counter - Read a MIB counter
2226 * This function reads a MIB counter of a specific ethernet port.
2227 * NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
2228 * following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
2229 * register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
2230 * ETH_MIB_GOOD_OCTETS_SENT_HIGH
2233 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2234 * unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
2237 * After reading the MIB counter, the counter resets.
2240 * MIB counter value.
2242 *******************************************************************************/
2243 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
2244 unsigned int mib_offset)
2246 return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num)
2250 /*******************************************************************************
2251 * ethernet_phy_set - Set the ethernet port PHY address.
2254 * This routine set the ethernet port PHY address according to given
2258 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2261 * Set PHY Address Register with given PHY address parameter.
2266 *******************************************************************************/
2267 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
2269 unsigned int reg_data;
2271 reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
2273 reg_data &= ~(0x1F << (5 * eth_port_num));
2274 reg_data |= (phy_addr << (5 * eth_port_num));
2276 MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data);
2281 /*******************************************************************************
2282 * ethernet_phy_get - Get the ethernet port PHY address.
2285 * This routine returns the given ethernet port PHY address.
2288 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2296 *******************************************************************************/
2297 static int ethernet_phy_get (ETH_PORT eth_port_num)
2299 unsigned int reg_data;
2301 reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
2303 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2306 /***********************************************************/
2307 /* (Re)start autonegotiation */
2308 /***********************************************************/
2309 int phy_setup_aneg (char *devname, unsigned char addr)
2311 unsigned short ctl, adv;
2313 /* Setup standard advertise */
2314 miiphy_read (devname, addr, PHY_ANAR, &adv);
2315 adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
2316 PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
2318 miiphy_write (devname, addr, PHY_ANAR, adv);
2320 miiphy_read (devname, addr, PHY_1000BTCR, &adv);
2322 miiphy_write (devname, addr, PHY_1000BTCR, adv);
2324 /* Start/Restart aneg */
2325 miiphy_read (devname, addr, PHY_BMCR, &ctl);
2326 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
2327 miiphy_write (devname, addr, PHY_BMCR, ctl);
2332 /*******************************************************************************
2333 * ethernet_phy_reset - Reset Ethernet port PHY.
2336 * This routine utilize the SMI interface to reset the ethernet port PHY.
2337 * The routine waits until the link is up again or link up is timeout.
2340 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2343 * The ethernet port PHY renew its link.
2348 *******************************************************************************/
2349 static bool ethernet_phy_reset (ETH_PORT eth_port_num)
2351 unsigned int time_out = 50;
2352 unsigned int phy_reg_data;
2354 eth_port_read_smi_reg (eth_port_num, 20, &phy_reg_data);
2355 phy_reg_data |= 0x0083; /* Set bit 7 to 1 for different RGMII timing */
2356 eth_port_write_smi_reg (eth_port_num, 20, phy_reg_data);
2359 eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
2360 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2361 eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
2363 /* Poll on the PHY LINK */
2365 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
2367 if (time_out-- == 0)
2370 while (!(phy_reg_data & 0x20));
2375 /*******************************************************************************
2376 * eth_port_reset - Reset Ethernet port
2379 * This routine resets the chip by aborting any SDMA engine activity and
2380 * clearing the MIB counters. The Receiver and the Transmit unit are in
2381 * idle state after this command is performed and the port is disabled.
2384 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2387 * Channel activity is halted.
2392 *******************************************************************************/
2393 static void eth_port_reset (ETH_PORT eth_port_num)
2395 unsigned int reg_data;
2397 /* Stop Tx port activity. Check port Tx activity. */
2399 MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
2402 if (reg_data & 0xFF) {
2403 /* Issue stop command for active channels only */
2404 MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
2405 (eth_port_num), (reg_data << 8));
2407 /* Wait for all Tx activity to terminate. */
2409 /* Check port cause register that all Tx queues are stopped */
2412 (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
2415 while (reg_data & 0xFF);
2418 /* Stop Rx port activity. Check port Rx activity. */
2420 MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
2423 if (reg_data & 0xFF) {
2424 /* Issue stop command for active channels only */
2425 MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
2426 (eth_port_num), (reg_data << 8));
2428 /* Wait for all Rx activity to terminate. */
2430 /* Check port cause register that all Rx queues are stopped */
2433 (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
2436 while (reg_data & 0xFF);
2439 /* Clear all MIB counters */
2440 eth_clear_mib_counters (eth_port_num);
2442 /* Reset the Enable bit in the Configuration Register */
2444 MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG
2446 reg_data &= ~ETH_SERIAL_PORT_ENABLE;
2447 MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
2453 #if 0 /* Not needed here */
2454 /*******************************************************************************
2455 * ethernet_set_config_reg - Set specified bits in configuration register.
2458 * This function sets specified bits in the given ethernet
2459 * configuration register.
2462 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2463 * unsigned int value 32 bit value.
2466 * The set bits in the value parameter are set in the configuration
2472 *******************************************************************************/
2473 static void ethernet_set_config_reg (ETH_PORT eth_port_num,
2476 unsigned int eth_config_reg;
2479 MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num));
2480 eth_config_reg |= value;
2481 MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
2489 /*******************************************************************************
2490 * ethernet_reset_config_reg - Reset specified bits in configuration register.
2493 * This function resets specified bits in the given Ethernet
2494 * configuration register.
2497 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2498 * unsigned int value 32 bit value.
2501 * The set bits in the value parameter are reset in the configuration
2507 *******************************************************************************/
2508 static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
2511 unsigned int eth_config_reg;
2513 eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
2515 eth_config_reg &= ~value;
2516 MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
2523 #if 0 /* Not needed here */
2524 /*******************************************************************************
2525 * ethernet_get_config_reg - Get the port configuration register
2528 * This function returns the configuration register value of the given
2532 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2538 * Port configuration register value.
2540 *******************************************************************************/
2541 static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
2543 unsigned int eth_config_reg;
2545 eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
2547 return eth_config_reg;
2552 /*******************************************************************************
2553 * eth_port_read_smi_reg - Read PHY registers
2556 * This routine utilize the SMI interface to interact with the PHY in
2557 * order to perform PHY register read.
2560 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2561 * unsigned int phy_reg PHY register address offset.
2562 * unsigned int *value Register value buffer.
2565 * Write the value of a specified PHY register into given buffer.
2568 * false if the PHY is busy or read data is not in valid state.
2571 *******************************************************************************/
2572 static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
2573 unsigned int phy_reg, unsigned int *value)
2575 unsigned int reg_value;
2576 unsigned int time_out = PHY_BUSY_TIMEOUT;
2579 phy_addr = ethernet_phy_get (eth_port_num);
2581 /* first check that it is not busy */
2583 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2584 if (time_out-- == 0) {
2588 while (reg_value & ETH_SMI_BUSY);
2592 MV_REG_WRITE (MV64460_ETH_SMI_REG,
2593 (phy_addr << 16) | (phy_reg << 21) |
2594 ETH_SMI_OPCODE_READ);
2596 time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
2599 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2600 if (time_out-- == 0) {
2604 while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
2606 /* Wait for the data to update in the SMI register */
2607 #define PHY_UPDATE_TIMEOUT 10000
2608 for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
2610 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2612 *value = reg_value & 0xffff;
2617 int mv_miiphy_read(char *devname, unsigned char phy_addr,
2618 unsigned char phy_reg, unsigned short *value)
2620 unsigned int reg_value;
2621 unsigned int time_out = PHY_BUSY_TIMEOUT;
2623 /* first check that it is not busy */
2625 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2626 if (time_out-- == 0) {
2630 while (reg_value & ETH_SMI_BUSY);
2633 MV_REG_WRITE (MV64460_ETH_SMI_REG,
2634 (phy_addr << 16) | (phy_reg << 21) |
2635 ETH_SMI_OPCODE_READ);
2637 time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
2640 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2641 if (time_out-- == 0) {
2645 while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
2647 /* Wait for the data to update in the SMI register */
2648 for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
2650 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2652 *value = reg_value & 0xffff;
2657 /*******************************************************************************
2658 * eth_port_write_smi_reg - Write to PHY registers
2661 * This routine utilize the SMI interface to interact with the PHY in
2662 * order to perform writes to PHY registers.
2665 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2666 * unsigned int phy_reg PHY register address offset.
2667 * unsigned int value Register value.
2670 * Write the given value to the specified PHY register.
2673 * false if the PHY is busy.
2676 *******************************************************************************/
2677 static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
2678 unsigned int phy_reg, unsigned int value)
2680 unsigned int reg_value;
2681 unsigned int time_out = PHY_BUSY_TIMEOUT;
2684 phy_addr = ethernet_phy_get (eth_port_num);
2686 /* first check that it is not busy */
2688 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2689 if (time_out-- == 0) {
2693 while (reg_value & ETH_SMI_BUSY);
2696 MV_REG_WRITE (MV64460_ETH_SMI_REG,
2697 (phy_addr << 16) | (phy_reg << 21) |
2698 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2702 int mv_miiphy_write(char *devname, unsigned char phy_addr,
2703 unsigned char phy_reg, unsigned short value)
2705 unsigned int reg_value;
2706 unsigned int time_out = PHY_BUSY_TIMEOUT;
2708 /* first check that it is not busy */
2710 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2711 if (time_out-- == 0) {
2715 while (reg_value & ETH_SMI_BUSY);
2718 MV_REG_WRITE (MV64460_ETH_SMI_REG,
2719 (phy_addr << 16) | (phy_reg << 21) |
2720 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2724 /*******************************************************************************
2725 * eth_set_access_control - Config address decode parameters for Ethernet unit
2728 * This function configures the address decode parameters for the Gigabit
2729 * Ethernet Controller according the given parameters struct.
2732 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2733 * ETH_WIN_PARAM *param Address decode parameter struct.
2736 * An access window is opened using the given access parameters.
2741 *******************************************************************************/
2742 static void eth_set_access_control (ETH_PORT eth_port_num,
2743 ETH_WIN_PARAM * param)
2745 unsigned int access_prot_reg;
2747 /* Set access control register */
2748 access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG
2750 access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
2751 access_prot_reg |= (param->access_ctrl << (param->win * 2));
2752 MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num),
2755 /* Set window Size reg (SR) */
2756 MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 +
2757 (ETH_SIZE_REG_GAP * param->win)),
2758 (((param->size / 0x10000) - 1) << 16));
2760 /* Set window Base address reg (BA) */
2761 MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
2762 (param->target | param->attributes | param->base_addr));
2763 /* High address remap reg (HARR) */
2765 MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 +
2766 (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
2769 /* Base address enable reg (BARER) */
2770 if (param->enable == 1)
2771 MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
2774 MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
2778 /*******************************************************************************
2779 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
2782 * This function prepares a Rx chained list of descriptors and packet
2783 * buffers in a form of a ring. The routine must be called after port
2784 * initialization routine and before port start routine.
2785 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2786 * devices in the system (i.e. DRAM). This function uses the ethernet
2787 * struct 'virtual to physical' routine (set by the user) to set the ring
2788 * with physical addresses.
2791 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2792 * ETH_QUEUE rx_queue Number of Rx queue.
2793 * int rx_desc_num Number of Rx descriptors
2794 * int rx_buff_size Size of Rx buffer
2795 * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
2796 * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
2799 * The routine updates the Ethernet port control struct with information
2800 * regarding the Rx descriptors and buffers.
2803 * false if the given descriptors memory area is not aligned according to
2804 * Ethernet SDMA specifications.
2807 *******************************************************************************/
2808 static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2812 unsigned int rx_desc_base_addr,
2813 unsigned int rx_buff_base_addr)
2815 ETH_RX_DESC *p_rx_desc;
2816 ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
2817 unsigned int buffer_addr;
2818 int ix; /* a counter */
2821 p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
2822 p_rx_prev_desc = p_rx_desc;
2823 buffer_addr = rx_buff_base_addr;
2825 /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2826 if (rx_buff_base_addr & 0xF)
2829 /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2830 if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
2833 /* Rx buffers must be 64-bit aligned. */
2834 if ((rx_buff_base_addr + rx_buff_size) & 0x7)
2837 /* initialize the Rx descriptors ring */
2838 for (ix = 0; ix < rx_desc_num; ix++) {
2839 p_rx_desc->buf_size = rx_buff_size;
2840 p_rx_desc->byte_cnt = 0x0000;
2841 p_rx_desc->cmd_sts =
2842 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2843 p_rx_desc->next_desc_ptr =
2844 ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
2845 p_rx_desc->buf_ptr = buffer_addr;
2846 p_rx_desc->return_info = 0x00000000;
2847 D_CACHE_FLUSH_LINE (p_rx_desc, 0);
2848 buffer_addr += rx_buff_size;
2849 p_rx_prev_desc = p_rx_desc;
2850 p_rx_desc = (ETH_RX_DESC *)
2851 ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
2854 /* Closing Rx descriptors ring */
2855 p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
2856 D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
2858 /* Save Rx desc pointer to driver struct. */
2859 CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2860 USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2862 p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
2863 (ETH_RX_DESC *) rx_desc_base_addr;
2864 p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
2865 rx_desc_num * RX_DESC_ALIGNED_SIZE;
2867 p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
2872 /*******************************************************************************
2873 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
2876 * This function prepares a Tx chained list of descriptors and packet
2877 * buffers in a form of a ring. The routine must be called after port
2878 * initialization routine and before port start routine.
2879 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2880 * devices in the system (i.e. DRAM). This function uses the ethernet
2881 * struct 'virtual to physical' routine (set by the user) to set the ring
2882 * with physical addresses.
2885 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2886 * ETH_QUEUE tx_queue Number of Tx queue.
2887 * int tx_desc_num Number of Tx descriptors
2888 * int tx_buff_size Size of Tx buffer
2889 * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
2890 * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
2893 * The routine updates the Ethernet port control struct with information
2894 * regarding the Tx descriptors and buffers.
2897 * false if the given descriptors memory area is not aligned according to
2898 * Ethernet SDMA specifications.
2901 *******************************************************************************/
2902 static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2906 unsigned int tx_desc_base_addr,
2907 unsigned int tx_buff_base_addr)
2910 ETH_TX_DESC *p_tx_desc;
2911 ETH_TX_DESC *p_tx_prev_desc;
2912 unsigned int buffer_addr;
2913 int ix; /* a counter */
2916 /* save the first desc pointer to link with the last descriptor */
2917 p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
2918 p_tx_prev_desc = p_tx_desc;
2919 buffer_addr = tx_buff_base_addr;
2921 /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2922 if (tx_buff_base_addr & 0xF)
2925 /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2926 if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
2927 || (tx_buff_size < TX_BUFFER_MIN_SIZE))
2930 /* Initialize the Tx descriptors ring */
2931 for (ix = 0; ix < tx_desc_num; ix++) {
2932 p_tx_desc->byte_cnt = 0x0000;
2933 p_tx_desc->l4i_chk = 0x0000;
2934 p_tx_desc->cmd_sts = 0x00000000;
2935 p_tx_desc->next_desc_ptr =
2936 ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
2938 p_tx_desc->buf_ptr = buffer_addr;
2939 p_tx_desc->return_info = 0x00000000;
2940 D_CACHE_FLUSH_LINE (p_tx_desc, 0);
2941 buffer_addr += tx_buff_size;
2942 p_tx_prev_desc = p_tx_desc;
2943 p_tx_desc = (ETH_TX_DESC *)
2944 ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
2947 /* Closing Tx descriptors ring */
2948 p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
2949 D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
2950 /* Set Tx desc pointer in driver struct. */
2951 CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2952 USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2954 /* Init Tx ring base and size parameters */
2955 p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
2956 (ETH_TX_DESC *) tx_desc_base_addr;
2957 p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
2958 (tx_desc_num * TX_DESC_ALIGNED_SIZE);
2960 /* Add the queue to the list of Tx queues of this port */
2961 p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
2966 /*******************************************************************************
2967 * eth_port_send - Send an Ethernet packet
2970 * This routine send a given packet described by p_pktinfo parameter. It
2971 * supports transmitting of a packet spaned over multiple buffers. The
2972 * routine updates 'curr' and 'first' indexes according to the packet
2973 * segment passed to the routine. In case the packet segment is first,
2974 * the 'first' index is update. In any case, the 'curr' index is updated.
2975 * If the routine get into Tx resource error it assigns 'curr' index as
2976 * 'first'. This way the function can abort Tx process of multiple
2977 * descriptors per packet.
2980 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2981 * ETH_QUEUE tx_queue Number of Tx queue.
2982 * PKT_INFO *p_pkt_info User packet buffer.
2985 * Tx ring 'curr' and 'first' indexes are updated.
2988 * ETH_QUEUE_FULL in case of Tx resource error.
2989 * ETH_ERROR in case the routine can not access Tx desc ring.
2990 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2993 *******************************************************************************/
2994 static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
2996 PKT_INFO * p_pkt_info)
2998 volatile ETH_TX_DESC *p_tx_desc_first;
2999 volatile ETH_TX_DESC *p_tx_desc_curr;
3000 volatile ETH_TX_DESC *p_tx_next_desc_curr;
3001 volatile ETH_TX_DESC *p_tx_desc_used;
3002 unsigned int command_status;
3004 /* Do not process Tx ring in case of Tx ring resource error */
3005 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
3006 return ETH_QUEUE_FULL;
3008 /* Get the Tx Desc ring indexes */
3009 CURR_TFD_GET (p_tx_desc_curr, tx_queue);
3010 USED_TFD_GET (p_tx_desc_used, tx_queue);
3012 if (p_tx_desc_curr == NULL)
3015 /* The following parameters are used to save readings from memory */
3016 p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
3017 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
3019 if (command_status & (ETH_TX_FIRST_DESC)) {
3020 /* Update first desc */
3021 FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
3022 p_tx_desc_first = p_tx_desc_curr;
3024 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
3025 command_status |= ETH_BUFFER_OWNED_BY_DMA;
3028 /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
3029 /* boundary. We use the memory allocated for Tx descriptor. This memory */
3030 /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
3031 if (p_pkt_info->byte_cnt <= 8) {
3032 printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
3035 p_tx_desc_curr->buf_ptr =
3036 (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
3037 eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
3038 p_pkt_info->byte_cnt);
3040 p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
3042 p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
3043 p_tx_desc_curr->return_info = p_pkt_info->return_info;
3045 if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
3046 /* Set last desc with DMA ownership and interrupt enable. */
3047 p_tx_desc_curr->cmd_sts = command_status |
3048 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
3050 if (p_tx_desc_curr != p_tx_desc_first)
3051 p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
3053 /* Flush CPU pipe */
3055 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
3056 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
3059 /* Apply send command */
3060 ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
3062 /* Finish Tx packet. Update first desc in case of Tx resource error */
3063 p_tx_desc_first = p_tx_next_desc_curr;
3064 FIRST_TFD_SET (p_tx_desc_first, tx_queue);
3067 p_tx_desc_curr->cmd_sts = command_status;
3068 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
3071 /* Check for ring index overlap in the Tx desc ring */
3072 if (p_tx_next_desc_curr == p_tx_desc_used) {
3073 /* Update the current descriptor */
3074 CURR_TFD_SET (p_tx_desc_first, tx_queue);
3076 p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
3077 return ETH_QUEUE_LAST_RESOURCE;
3079 /* Update the current descriptor */
3080 CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
3085 /*******************************************************************************
3086 * eth_tx_return_desc - Free all used Tx descriptors
3089 * This routine returns the transmitted packet information to the caller.
3090 * It uses the 'first' index to support Tx desc return in case a transmit
3091 * of a packet spanned over multiple buffer still in process.
3092 * In case the Tx queue was in "resource error" condition, where there are
3093 * no available Tx resources, the function resets the resource error flag.
3096 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
3097 * ETH_QUEUE tx_queue Number of Tx queue.
3098 * PKT_INFO *p_pkt_info User packet buffer.
3101 * Tx ring 'first' and 'used' indexes are updated.
3104 * ETH_ERROR in case the routine can not access Tx desc ring.
3105 * ETH_RETRY in case there is transmission in process.
3106 * ETH_END_OF_JOB if the routine has nothing to release.
3109 *******************************************************************************/
3110 static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
3113 PKT_INFO * p_pkt_info)
3115 volatile ETH_TX_DESC *p_tx_desc_used = NULL;
3116 volatile ETH_TX_DESC *p_tx_desc_first = NULL;
3117 unsigned int command_status;
3120 /* Get the Tx Desc ring indexes */
3121 USED_TFD_GET (p_tx_desc_used, tx_queue);
3122 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
3126 if (p_tx_desc_used == NULL)
3129 command_status = p_tx_desc_used->cmd_sts;
3131 /* Still transmitting... */
3132 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
3133 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
3137 /* Stop release. About to overlap the current available Tx descriptor */
3138 if ((p_tx_desc_used == p_tx_desc_first) &&
3139 (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
3140 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
3141 return ETH_END_OF_JOB;
3144 /* Pass the packet information to the caller */
3145 p_pkt_info->cmd_sts = command_status;
3146 p_pkt_info->return_info = p_tx_desc_used->return_info;
3147 p_tx_desc_used->return_info = 0;
3149 /* Update the next descriptor to release. */
3150 USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
3152 /* Any Tx return cancels the Tx resource error status */
3153 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
3154 p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
3156 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
3162 /*******************************************************************************
3163 * eth_port_receive - Get received information from Rx ring.
3166 * This routine returns the received data to the caller. There is no
3167 * data copying during routine operation. All information is returned
3168 * using pointer to packet information struct passed from the caller.
3169 * If the routine exhausts Rx ring resources then the resource error flag
3173 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
3174 * ETH_QUEUE rx_queue Number of Rx queue.
3175 * PKT_INFO *p_pkt_info User packet buffer.
3178 * Rx ring current and used indexes are updated.
3181 * ETH_ERROR in case the routine can not access Rx desc ring.
3182 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
3183 * ETH_END_OF_JOB if there is no received data.
3186 *******************************************************************************/
3187 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
3189 PKT_INFO * p_pkt_info)
3191 volatile ETH_RX_DESC *p_rx_curr_desc;
3192 volatile ETH_RX_DESC *p_rx_next_curr_desc;
3193 volatile ETH_RX_DESC *p_rx_used_desc;
3194 unsigned int command_status;
3196 /* Do not process Rx ring in case of Rx ring resource error */
3197 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
3198 printf ("\nRx Queue is full ...\n");
3199 return ETH_QUEUE_FULL;
3202 /* Get the Rx Desc ring 'curr and 'used' indexes */
3203 CURR_RFD_GET (p_rx_curr_desc, rx_queue);
3204 USED_RFD_GET (p_rx_used_desc, rx_queue);
3207 if (p_rx_curr_desc == NULL)
3210 /* The following parameters are used to save readings from memory */
3211 p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
3212 command_status = p_rx_curr_desc->cmd_sts;
3214 /* Nothing to receive... */
3215 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
3216 /* DP(printf("Rx: command_status: %08x\n", command_status)); */
3217 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
3218 /* DP(printf("\nETH_END_OF_JOB ...\n"));*/
3219 return ETH_END_OF_JOB;
3222 p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
3223 p_pkt_info->cmd_sts = command_status;
3224 p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
3225 p_pkt_info->return_info = p_rx_curr_desc->return_info;
3226 p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
3228 /* Clean the return info field to indicate that the packet has been */
3229 /* moved to the upper layers */
3230 p_rx_curr_desc->return_info = 0;
3232 /* Update 'curr' in data structure */
3233 CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
3235 /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
3236 if (p_rx_next_curr_desc == p_rx_used_desc)
3237 p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
3239 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
3245 /*******************************************************************************
3246 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
3249 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
3250 * next 'used' descriptor and attached the returned buffer to it.
3251 * In case the Rx ring was in "resource error" condition, where there are
3252 * no available Rx resources, the function resets the resource error flag.
3255 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
3256 * ETH_QUEUE rx_queue Number of Rx queue.
3257 * PKT_INFO *p_pkt_info Information on the returned buffer.
3260 * New available Rx resource in Rx descriptor ring.
3263 * ETH_ERROR in case the routine can not access Rx desc ring.
3266 *******************************************************************************/
3267 static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
3270 PKT_INFO * p_pkt_info)
3272 volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
3274 /* Get 'used' Rx descriptor */
3275 USED_RFD_GET (p_used_rx_desc, rx_queue);
3278 if (p_used_rx_desc == NULL)
3281 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
3282 p_used_rx_desc->return_info = p_pkt_info->return_info;
3283 p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
3284 p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE; /* Reset Buffer size */
3286 /* Flush the write pipe */
3289 /* Return the descriptor to DMA ownership */
3290 p_used_rx_desc->cmd_sts =
3291 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3293 /* Flush descriptor and CPU pipe */
3294 D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
3297 /* Move the used descriptor pointer to the next descriptor */
3298 USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
3300 /* Any Rx return cancels the Rx resource error status */
3301 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
3302 p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
3307 /*******************************************************************************
3308 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
3311 * This routine sets the RX coalescing interrupt mechanism parameter.
3312 * This parameter is a timeout counter, that counts in 64 t_clk
3313 * chunks ; that when timeout event occurs a maskable interrupt
3315 * The parameter is calculated using the tClk of the MV-643xx chip
3316 * , and the required delay of the interrupt in usec.
3319 * ETH_PORT eth_port_num Ethernet port number
3320 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3321 * unsigned int delay Delay in usec
3324 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3327 * The interrupt coalescing value set in the gigE port.
3329 *******************************************************************************/
3331 static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
3337 coal = ((t_clk / 1000000) * delay) / 64;
3338 /* Set RX Coalescing mechanism */
3339 MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
3340 ((coal & 0x3fff) << 8) |
3342 (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num))
3348 /*******************************************************************************
3349 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
3352 * This routine sets the TX coalescing interrupt mechanism parameter.
3353 * This parameter is a timeout counter, that counts in 64 t_clk
3354 * chunks ; that when timeout event occurs a maskable interrupt
3356 * The parameter is calculated using the t_cLK frequency of the
3357 * MV-643xx chip and the required delay in the interrupt in uSec
3360 * ETH_PORT eth_port_num Ethernet port number
3361 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3362 * unsigned int delay Delay in uSeconds
3365 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3368 * The interrupt coalescing value set in the gigE port.
3370 *******************************************************************************/
3372 static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
3378 coal = ((t_clk / 1000000) * delay) / 64;
3379 /* Set TX Coalescing mechanism */
3380 MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
3386 /*******************************************************************************
3387 * eth_b_copy - Copy bytes from source to destination
3390 * This function supports the eight bytes limitation on Tx buffer size.
3391 * The routine will zero eight bytes starting from the destination address
3392 * followed by copying bytes from the source address to the destination.
3395 * unsigned int src_addr 32 bit source address.
3396 * unsigned int dst_addr 32 bit destination address.
3397 * int byte_count Number of bytes to copy.
3405 *******************************************************************************/
3406 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
3409 /* Zero the dst_addr area */
3410 *(unsigned int *) dst_addr = 0x0;
3412 while (byte_count != 0) {
3413 *(char *) dst_addr = *(char *) src_addr;