2 * Copyright (C) 2012 Samsung Electronics
4 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/dwmmc.h>
17 #include <asm/arch/mmc.h>
18 #include <asm/arch/pinmux.h>
19 #include <asm/arch/power.h>
20 #include <asm/arch/sromc.h>
21 #include <power/pmic.h>
22 #include <power/max77686_pmic.h>
23 #include <power/tps65090_pmic.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #ifdef CONFIG_SOUND_MAX98095
29 static void board_enable_audio_codec(void)
31 /* Enable MAX98095 Codec */
32 gpio_request(EXYNOS5_GPIO_X17, "max98095_enable");
33 gpio_direction_output(EXYNOS5_GPIO_X17, 1);
34 gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
40 #ifdef CONFIG_SOUND_MAX98095
41 board_enable_audio_codec();
46 #if defined(CONFIG_POWER)
47 #ifdef CONFIG_POWER_MAX77686
48 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
53 ret = pmic_reg_read(p, reg, &val);
55 debug("%s: PMIC %d register read failed\n", __func__, reg);
59 ret = pmic_reg_write(p, reg, val);
61 debug("%s: PMIC %d register write failed\n", __func__, reg);
67 static int max77686_init(void)
71 if (pmic_init(I2C_PMIC))
74 p = pmic_get("MAX77686_PMIC");
81 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
84 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
85 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
89 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
90 MAX77686_BUCK1OUT_1V)) {
91 debug("%s: PMIC %d register write failed\n", __func__,
92 MAX77686_REG_PMIC_BUCK1OUT);
96 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
97 MAX77686_BUCK1CTRL_EN))
101 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
102 MAX77686_BUCK2DVS1_1_3V)) {
103 debug("%s: PMIC %d register write failed\n", __func__,
104 MAX77686_REG_PMIC_BUCK2DVS1);
108 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
109 MAX77686_BUCK2CTRL_ON))
113 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
114 MAX77686_BUCK3DVS1_1_0125V)) {
115 debug("%s: PMIC %d register write failed\n", __func__,
116 MAX77686_REG_PMIC_BUCK3DVS1);
120 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
121 MAX77686_BUCK3CTRL_ON))
125 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
126 MAX77686_BUCK4DVS1_1_2V)) {
127 debug("%s: PMIC %d register write failed\n", __func__,
128 MAX77686_REG_PMIC_BUCK4DVS1);
132 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
133 MAX77686_BUCK3CTRL_ON))
137 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
138 MAX77686_LD02CTRL1_1_5V | EN_LDO))
142 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
143 MAX77686_LD03CTRL1_1_8V | EN_LDO))
147 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
148 MAX77686_LD05CTRL1_1_8V | EN_LDO))
152 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
153 MAX77686_LD10CTRL1_1_8V | EN_LDO))
158 #endif /* CONFIG_POWER_MAX77686 */
160 int exynos_power_init(void)
164 #ifdef CONFIG_POWER_MAX77686
165 ret = max77686_init();
169 #ifdef CONFIG_POWER_TPS65090
171 * The TPS65090 may not be in the device tree. If so, it is not
174 ret = tps65090_init();
175 if (ret == 0 || ret == -ENODEV)
181 #endif /* CONFIG_POWER */
184 static int board_dp_bridge_setup(void)
186 const int max_tries = 10;
190 * TODO(sjg): Use device tree for GPIOs when exynos GPIO
191 * numbering patch is in mainline.
193 debug("%s\n", __func__);
194 node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_NXP_PTN3460);
196 debug("%s: No node for DP bridge in device tree\n", __func__);
200 /* Setup the GPIOs */
202 /* PD is ACTIVE_LOW, and initially de-asserted */
203 gpio_request(EXYNOS5_GPIO_Y25, "dp_bridge_pd");
204 gpio_set_pull(EXYNOS5_GPIO_Y25, S5P_GPIO_PULL_NONE);
205 gpio_direction_output(EXYNOS5_GPIO_Y25, 1);
207 /* Reset is ACTIVE_LOW */
208 gpio_request(EXYNOS5_GPIO_X15, "dp_bridge_reset");
209 gpio_set_pull(EXYNOS5_GPIO_X15, S5P_GPIO_PULL_NONE);
210 gpio_direction_output(EXYNOS5_GPIO_X15, 0);
213 gpio_set_value(EXYNOS5_GPIO_X15, 1);
215 gpio_request(EXYNOS5_GPIO_X07, "dp_bridge_hpd");
216 gpio_direction_input(EXYNOS5_GPIO_X07);
219 * We need to wait for 90ms after bringing up the bridge since there
220 * is a phantom "high" on the HPD chip during its bootup. The phantom
221 * high comes within 7ms of de-asserting PD and persists for at least
222 * 15ms. The real high comes roughly 50ms after PD is de-asserted. The
223 * phantom high makes it hard for us to know when the NXP chip is up.
227 for (num_tries = 0; num_tries < max_tries; num_tries++) {
228 /* Check HPD. If it's high, we're all good. */
229 if (gpio_get_value(EXYNOS5_GPIO_X07))
232 debug("%s: eDP bridge failed to come up; try %d of %d\n",
233 __func__, num_tries, max_tries);
236 /* Immediately go into bridge reset if the hp line is not high */
240 void exynos_cfg_lcd_gpio(void)
243 gpio_request(EXYNOS5_GPIO_B20, "lcd_backlight");
244 gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
245 gpio_set_value(EXYNOS5_GPIO_B20, 1);
248 gpio_request(EXYNOS5_GPIO_X15, "lcd_power");
249 gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
250 gpio_set_value(EXYNOS5_GPIO_X15, 1);
252 /* Set Hotplug detect for DP */
253 gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
256 void exynos_set_dp_phy(unsigned int onoff)
258 set_dp_phy_ctrl(onoff);
261 void exynos_backlight_on(unsigned int on)
263 debug("%s(%u)\n", __func__, on);
268 #ifdef CONFIG_POWER_TPS65090
271 ret = tps65090_fet_enable(1); /* Enable FET1, backlight */
275 /* T5 in the LCD timing spec (defined as > 10ms) */
278 /* board_dp_backlight_pwm */
279 gpio_direction_output(EXYNOS5_GPIO_B20, 1);
281 /* T6 in the LCD timing spec (defined as > 10ms) */
284 /* board_dp_backlight_en */
285 gpio_request(EXYNOS5_GPIO_X30, "board_dp_backlight_en");
286 gpio_direction_output(EXYNOS5_GPIO_X30, 1);
290 void exynos_lcd_power_on(void)
294 debug("%s\n", __func__);
296 #ifdef CONFIG_POWER_TPS65090
297 /* board_dp_lcd_vdd */
298 tps65090_fet_enable(6); /* Enable FET6, lcd panel */
301 ret = board_dp_bridge_setup();
302 if (ret && ret != -ENODEV)
303 printf("LCD bridge failed to enable: %d\n", ret);