board/samsung/smdk5250/smdk5250.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <cros_ec.h>
   9 #include <fdtdec.h>
  10 #include <asm/io.h>
  11 #include <errno.h>
  12 #include <i2c.h>
  13 #include <lcd.h>
  14 #include <netdev.h>
  15 #include <spi.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/dwmmc.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/mmc.h>
  20 #include <asm/arch/pinmux.h>
  21 #include <asm/arch/power.h>
  22 #include <asm/arch/sromc.h>
  23 #include <asm/arch/dp_info.h>
  24 #include <power/pmic.h>
  25 #include <power/max77686_pmic.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef CONFIG_USB_EHCI_EXYNOS
  30 static int board_usb_vbus_init(void)
  31 {
  32         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  33                                                 samsung_get_base_gpio_part1();
  34
  35         /* Enable VBUS power switch */
  36         s5p_gpio_direction_output(&gpio1->x2, 6, 1);
  37
  38         /* VBUS turn ON time */
  39         mdelay(3);
  40
  41         return 0;
  42 }
  43 #endif
  44
  45 #ifdef CONFIG_SOUND_MAX98095
  46 static void  board_enable_audio_codec(void)
  47 {
  48         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  49                                                 samsung_get_base_gpio_part1();
  50
  51         /* Enable MAX98095 Codec */
  52         s5p_gpio_direction_output(&gpio1->x1, 7, 1);
  53         s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
  54 }
  55 #endif
  56
  57 int exynos_init(void)
  58 {
  59 #ifdef CONFIG_USB_EHCI_EXYNOS
  60         board_usb_vbus_init();
  61 #endif
  62 #ifdef CONFIG_SOUND_MAX98095
  63         board_enable_audio_codec();
  64 #endif
  65         return 0;
  66 }
  67
  68 int board_eth_init(bd_t *bis)
  69 {
  70 #ifdef CONFIG_SMC911X
  71         u32 smc_bw_conf, smc_bc_conf;
  72         struct fdt_sromc config;
  73         fdt_addr_t base_addr;
  74
  75         /* Non-FDT configuration - bank number and timing parameters*/
  76         config.bank = CONFIG_ENV_SROM_BANK;
  77         config.width = 2;
  78
  79         config.timing[FDT_SROM_TACS] = 0x01;
  80         config.timing[FDT_SROM_TCOS] = 0x01;
  81         config.timing[FDT_SROM_TACC] = 0x06;
  82         config.timing[FDT_SROM_TCOH] = 0x01;
  83         config.timing[FDT_SROM_TAH] = 0x0C;
  84         config.timing[FDT_SROM_TACP] = 0x09;
  85         config.timing[FDT_SROM_PMC] = 0x01;
  86         base_addr = CONFIG_SMC911X_BASE;
  87
  88         /* Ethernet needs data bus width of 16 bits */
  89         if (config.width != 2) {
  90                 debug("%s: Unsupported bus width %d\n", __func__,
  91                         config.width);
  92                 return -1;
  93         }
  94         smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
  95                         | SROMC_BYTE_ENABLE(config.bank);
  96
  97         smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |\
  98                         SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
  99                         SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
 100                         SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
 101                         SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |\
 102                         SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
 103                         SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
 104
 105         /* Select and configure the SROMC bank */
 106         exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
 107         s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
 108         return smc911x_initialize(0, base_addr);
 109 #endif
 110         return 0;
 111 }
 112
 113 #ifdef CONFIG_DISPLAY_BOARDINFO
 114 int checkboard(void)
 115 {
 116         printf("\nBoard: SMDK5250\n");
 117         return 0;
 118 }
 119 #endif
 120
 121 #ifdef CONFIG_GENERIC_MMC
 122 int board_mmc_init(bd_t *bis)
 123 {
 124         int err, ret = 0, index, bus_width;
 125         u32 base;
 126
 127         err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 128         if (err)
 129                 debug("SDMMC0 not configured\n");
 130         ret |= err;
 131
 132         /*EMMC: dwmmc Channel-0 with 8 bit bus width */
 133         index = 0;
 134         base =  samsung_get_base_mmc() + (0x10000 * index);
 135         bus_width = 8;
 136         err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
 137         if (err)
 138                 debug("dwmmc Channel-0 init failed\n");
 139         ret |= err;
 140
 141         err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
 142         if (err)
 143                 debug("SDMMC2 not configured\n");
 144         ret |= err;
 145
 146         /*SD: dwmmc Channel-2 with 4 bit bus width */
 147         index = 2;
 148         base = samsung_get_base_mmc() + (0x10000 * index);
 149         bus_width = 4;
 150         err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
 151         if (err)
 152                 debug("dwmmc Channel-2 init failed\n");
 153         ret |= err;
 154
 155         return ret;
 156 }
 157 #endif
 158
 159 void board_i2c_init(const void *blob)
 160 {
 161         int i;
 162
 163         for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
 164                 exynos_pinmux_config((PERIPH_ID_I2C0 + i),
 165                                      PINMUX_FLAG_NONE);
 166         }
 167 }
 168
 169 #ifdef CONFIG_LCD
 170 void exynos_cfg_lcd_gpio(void)
 171 {
 172         struct exynos5_gpio_part1 *gpio1 =
 173                 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 174
 175         /* For Backlight */
 176         s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
 177         s5p_gpio_set_value(&gpio1->b2, 0, 1);
 178
 179         /* LCD power on */
 180         s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
 181         s5p_gpio_set_value(&gpio1->x1, 5, 1);
 182
 183         /* Set Hotplug detect for DP */
 184         s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
 185 }
 186
 187 void exynos_set_dp_phy(unsigned int onoff)
 188 {
 189         set_dp_phy_ctrl(onoff);
 190 }
 191
 192 vidinfo_t panel_info = {
 193         .vl_freq        = 60,
 194         .vl_col         = 2560,
 195         .vl_row         = 1600,
 196         .vl_width       = 2560,
 197         .vl_height      = 1600,
 198         .vl_clkp        = CONFIG_SYS_LOW,
 199         .vl_hsp         = CONFIG_SYS_LOW,
 200         .vl_vsp         = CONFIG_SYS_LOW,
 201         .vl_dp          = CONFIG_SYS_LOW,
 202         .vl_bpix        = 4,    /* LCD_BPP = 2^4, for output conosle on LCD */
 203
 204         /* wDP panel timing infomation */
 205         .vl_hspw        = 32,
 206         .vl_hbpd        = 80,
 207         .vl_hfpd        = 48,
 208
 209         .vl_vspw        = 6,
 210         .vl_vbpd        = 37,
 211         .vl_vfpd        = 3,
 212         .vl_cmd_allow_len = 0xf,
 213
 214         .win_id         = 3,
 215         .dual_lcd_enabled = 0,
 216
 217         .init_delay     = 0,
 218         .power_on_delay = 0,
 219         .reset_delay    = 0,
 220         .interface_mode = FIMD_RGB_INTERFACE,
 221         .dp_enabled     = 1,
 222 };
 223
 224 static struct edp_device_info edp_info = {
 225         .disp_info = {
 226                 .h_res = 2560,
 227                 .h_sync_width = 32,
 228                 .h_back_porch = 80,
 229                 .h_front_porch = 48,
 230                 .v_res = 1600,
 231                 .v_sync_width  = 6,
 232                 .v_back_porch = 37,
 233                 .v_front_porch = 3,
 234                 .v_sync_rate = 60,
 235         },
 236         .lt_info = {
 237                 .lt_status = DP_LT_NONE,
 238         },
 239         .video_info = {
 240                 .master_mode = 0,
 241                 .bist_mode = DP_DISABLE,
 242                 .bist_pattern = NO_PATTERN,
 243                 .h_sync_polarity = 0,
 244                 .v_sync_polarity = 0,
 245                 .interlaced = 0,
 246                 .color_space = COLOR_RGB,
 247                 .dynamic_range = VESA,
 248                 .ycbcr_coeff = COLOR_YCBCR601,
 249                 .color_depth = COLOR_8,
 250         },
 251 };
 252
 253 static struct exynos_dp_platform_data dp_platform_data = {
 254         .edp_dev_info   = &edp_info,
 255 };
 256
 257 void init_panel_info(vidinfo_t *vid)
 258 {
 259         vid->rgb_mode   = MODE_RGB_P;
 260         exynos_set_dp_platform_data(&dp_platform_data);
 261 }
 262 #endif