board/samsung/smdk5250/smdk5250.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <fdtdec.h>
  25 #include <asm/io.h>
  26 #include <errno.h>
  27 #include <i2c.h>
  28 #include <lcd.h>
  29 #include <netdev.h>
  30 #include <spi.h>
  31 #include <asm/arch/cpu.h>
  32 #include <asm/arch/gpio.h>
  33 #include <asm/arch/mmc.h>
  34 #include <asm/arch/pinmux.h>
  35 #include <asm/arch/power.h>
  36 #include <asm/arch/sromc.h>
  37 #include <asm/arch/dp_info.h>
  38 #include <power/pmic.h>
  39 #include <power/max77686_pmic.h>
  40 #include <tmu.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 #if defined CONFIG_EXYNOS_TMU
  45 /*
  46  * Boot Time Thermal Analysis for SoC temperature threshold breach
  47  */
  48 static void boot_temp_check(void)
  49 {
  50         int temp;
  51
  52         switch (tmu_monitor(&temp)) {
  53         /* Status TRIPPED ans WARNING means corresponding threshold breach */
  54         case TMU_STATUS_TRIPPED:
  55                 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
  56                 set_ps_hold_ctrl();
  57                 hang();
  58                 break;
  59         case TMU_STATUS_WARNING:
  60                 puts("EXYNOS_TMU: WARNING! Temperature very high\n");
  61                 break;
  62         /*
  63          * TMU_STATUS_INIT means something is wrong with temperature sensing
  64          * and TMU status was changed back from NORMAL to INIT.
  65          */
  66         case TMU_STATUS_INIT:
  67         default:
  68                 debug("EXYNOS_TMU: Unknown TMU state\n");
  69         }
  70 }
  71 #endif
  72
  73 #ifdef CONFIG_USB_EHCI_EXYNOS
  74 int board_usb_vbus_init(void)
  75 {
  76         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  77                                                 samsung_get_base_gpio_part1();
  78
  79         /* Enable VBUS power switch */
  80         s5p_gpio_direction_output(&gpio1->x2, 6, 1);
  81
  82         /* VBUS turn ON time */
  83         mdelay(3);
  84
  85         return 0;
  86 }
  87 #endif
  88
  89 #ifdef CONFIG_SOUND_MAX98095
  90 static void  board_enable_audio_codec(void)
  91 {
  92         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  93                                                 samsung_get_base_gpio_part1();
  94
  95         /* Enable MAX98095 Codec */
  96         s5p_gpio_direction_output(&gpio1->x1, 7, 1);
  97         s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
  98 }
  99 #endif
 100
 101 int board_init(void)
 102 {
 103         gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
 104
 105 #if defined CONFIG_EXYNOS_TMU
 106         if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
 107                 debug("%s: Failed to init TMU\n", __func__);
 108                 return -1;
 109         }
 110         boot_temp_check();
 111 #endif
 112
 113 #ifdef CONFIG_EXYNOS_SPI
 114         spi_init();
 115 #endif
 116 #ifdef CONFIG_USB_EHCI_EXYNOS
 117         board_usb_vbus_init();
 118 #endif
 119 #ifdef CONFIG_SOUND_MAX98095
 120         board_enable_audio_codec();
 121 #endif
 122         return 0;
 123 }
 124
 125 int dram_init(void)
 126 {
 127         gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
 128                         + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
 129                         + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
 130                         + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
 131                         + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
 132                         + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
 133                         + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
 134                         + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
 135         return 0;
 136 }
 137
 138 #if defined(CONFIG_POWER)
 139 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
 140 {
 141         u32 val;
 142         int ret = 0;
 143
 144         ret = pmic_reg_read(p, reg, &val);
 145         if (ret) {
 146                 debug("%s: PMIC %d register read failed\n", __func__, reg);
 147                 return -1;
 148         }
 149         val |= regval;
 150         ret = pmic_reg_write(p, reg, val);
 151         if (ret) {
 152                 debug("%s: PMIC %d register write failed\n", __func__, reg);
 153                 return -1;
 154         }
 155         return 0;
 156 }
 157
 158 int power_init_board(void)
 159 {
 160         struct pmic *p;
 161
 162         set_ps_hold_ctrl();
 163
 164         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 165
 166         if (pmic_init(I2C_PMIC))
 167                 return -1;
 168
 169         p = pmic_get("MAX77686_PMIC");
 170         if (!p)
 171                 return -ENODEV;
 172
 173         if (pmic_probe(p))
 174                 return -1;
 175
 176         if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
 177                 return -1;
 178
 179         if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
 180                                 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
 181                 return -1;
 182
 183         /* VDD_MIF */
 184         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
 185                                                 MAX77686_BUCK1OUT_1V)) {
 186                 debug("%s: PMIC %d register write failed\n", __func__,
 187                                                 MAX77686_REG_PMIC_BUCK1OUT);
 188                 return -1;
 189         }
 190
 191         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
 192                                                 MAX77686_BUCK1CTRL_EN))
 193                 return -1;
 194
 195         /* VDD_ARM */
 196         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
 197                                         MAX77686_BUCK2DVS1_1_3V)) {
 198                 debug("%s: PMIC %d register write failed\n", __func__,
 199                                                 MAX77686_REG_PMIC_BUCK2DVS1);
 200                 return -1;
 201         }
 202
 203         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
 204                                         MAX77686_BUCK2CTRL_ON))
 205                 return -1;
 206
 207         /* VDD_INT */
 208         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
 209                                         MAX77686_BUCK3DVS1_1_0125V)) {
 210                 debug("%s: PMIC %d register write failed\n", __func__,
 211                                                 MAX77686_REG_PMIC_BUCK3DVS1);
 212                 return -1;
 213         }
 214
 215         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
 216                                         MAX77686_BUCK3CTRL_ON))
 217                 return -1;
 218
 219         /* VDD_G3D */
 220         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
 221                                         MAX77686_BUCK4DVS1_1_2V)) {
 222                 debug("%s: PMIC %d register write failed\n", __func__,
 223                                                 MAX77686_REG_PMIC_BUCK4DVS1);
 224                 return -1;
 225         }
 226
 227         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
 228                                         MAX77686_BUCK3CTRL_ON))
 229                 return -1;
 230
 231         /* VDD_LDO2 */
 232         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
 233                                 MAX77686_LD02CTRL1_1_5V | EN_LDO))
 234                 return -1;
 235
 236         /* VDD_LDO3 */
 237         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
 238                                 MAX77686_LD03CTRL1_1_8V | EN_LDO))
 239                 return -1;
 240
 241         /* VDD_LDO5 */
 242         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
 243                                 MAX77686_LD05CTRL1_1_8V | EN_LDO))
 244                 return -1;
 245
 246         /* VDD_LDO10 */
 247         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
 248                                 MAX77686_LD10CTRL1_1_8V | EN_LDO))
 249                 return -1;
 250
 251         return 0;
 252 }
 253 #endif
 254
 255 void dram_init_banksize(void)
 256 {
 257         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 258         gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
 259                                                         PHYS_SDRAM_1_SIZE);
 260         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 261         gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
 262                                                         PHYS_SDRAM_2_SIZE);
 263         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
 264         gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
 265                                                         PHYS_SDRAM_3_SIZE);
 266         gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 267         gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
 268                                                         PHYS_SDRAM_4_SIZE);
 269         gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
 270         gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
 271                                                         PHYS_SDRAM_5_SIZE);
 272         gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
 273         gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
 274                                                         PHYS_SDRAM_6_SIZE);
 275         gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
 276         gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
 277                                                         PHYS_SDRAM_7_SIZE);
 278         gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
 279         gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
 280                                                         PHYS_SDRAM_8_SIZE);
 281 }
 282
 283 #ifdef CONFIG_OF_CONTROL
 284 static int decode_sromc(const void *blob, struct fdt_sromc *config)
 285 {
 286         int err;
 287         int node;
 288
 289         node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
 290         if (node < 0) {
 291                 debug("Could not find SROMC node\n");
 292                 return node;
 293         }
 294
 295         config->bank = fdtdec_get_int(blob, node, "bank", 0);
 296         config->width = fdtdec_get_int(blob, node, "width", 2);
 297
 298         err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
 299                         FDT_SROM_TIMING_COUNT);
 300         if (err < 0) {
 301                 debug("Could not decode SROMC configuration\n");
 302                 return -FDT_ERR_NOTFOUND;
 303         }
 304
 305         return 0;
 306 }
 307 #endif
 308
 309 int board_eth_init(bd_t *bis)
 310 {
 311 #ifdef CONFIG_SMC911X
 312         u32 smc_bw_conf, smc_bc_conf;
 313         struct fdt_sromc config;
 314         fdt_addr_t base_addr;
 315         int node;
 316
 317 #ifdef CONFIG_OF_CONTROL
 318         node = decode_sromc(gd->fdt_blob, &config);
 319         if (node < 0) {
 320                 debug("%s: Could not find sromc configuration\n", __func__);
 321                 return 0;
 322         }
 323         node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
 324         if (node < 0) {
 325                 debug("%s: Could not find lan9215 configuration\n", __func__);
 326                 return 0;
 327         }
 328
 329         /* We now have a node, so any problems from now on are errors */
 330         base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
 331         if (base_addr == FDT_ADDR_T_NONE) {
 332                 debug("%s: Could not find lan9215 address\n", __func__);
 333                 return -1;
 334         }
 335 #else
 336         /* Non-FDT configuration - bank number and timing parameters*/
 337         config.bank = CONFIG_ENV_SROM_BANK;
 338         config.width = 2;
 339
 340         config.timing[FDT_SROM_TACS] = 0x01;
 341         config.timing[FDT_SROM_TCOS] = 0x01;
 342         config.timing[FDT_SROM_TACC] = 0x06;
 343         config.timing[FDT_SROM_TCOH] = 0x01;
 344         config.timing[FDT_SROM_TAH] = 0x0C;
 345         config.timing[FDT_SROM_TACP] = 0x09;
 346         config.timing[FDT_SROM_PMC] = 0x01;
 347         base_addr = CONFIG_SMC911X_BASE;
 348 #endif
 349
 350         /* Ethernet needs data bus width of 16 bits */
 351         if (config.width != 2) {
 352                 debug("%s: Unsupported bus width %d\n", __func__,
 353                         config.width);
 354                 return -1;
 355         }
 356         smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
 357                         | SROMC_BYTE_ENABLE(config.bank);
 358
 359         smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |\
 360                         SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
 361                         SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
 362                         SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
 363                         SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |\
 364                         SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
 365                         SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
 366
 367         /* Select and configure the SROMC bank */
 368         exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
 369         s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
 370         return smc911x_initialize(0, base_addr);
 371 #endif
 372         return 0;
 373 }
 374
 375 #ifdef CONFIG_DISPLAY_BOARDINFO
 376 int checkboard(void)
 377 {
 378 #ifdef CONFIG_OF_CONTROL
 379         const char *board_name;
 380
 381         board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
 382         if (board_name == NULL)
 383                 printf("\nUnknown Board\n");
 384         else
 385                 printf("\nBoard: %s\n", board_name);
 386 #else
 387         printf("\nBoard: SMDK5250\n");
 388 #endif
 389         return 0;
 390 }
 391 #endif
 392
 393 #ifdef CONFIG_GENERIC_MMC
 394 int board_mmc_init(bd_t *bis)
 395 {
 396         int err;
 397
 398         err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 399         if (err) {
 400                 debug("SDMMC0 not configured\n");
 401                 return err;
 402         }
 403
 404         err = s5p_mmc_init(0, 8);
 405         return err;
 406 }
 407 #endif
 408
 409 static int board_uart_init(void)
 410 {
 411         int err;
 412
 413         err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
 414         if (err) {
 415                 debug("UART0 not configured\n");
 416                 return err;
 417         }
 418
 419         err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
 420         if (err) {
 421                 debug("UART1 not configured\n");
 422                 return err;
 423         }
 424
 425         err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
 426         if (err) {
 427                 debug("UART2 not configured\n");
 428                 return err;
 429         }
 430
 431         err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
 432         if (err) {
 433                 debug("UART3 not configured\n");
 434                 return err;
 435         }
 436
 437         return 0;
 438 }
 439
 440 #ifdef CONFIG_BOARD_EARLY_INIT_F
 441 int board_early_init_f(void)
 442 {
 443         int err;
 444         err = board_uart_init();
 445         if (err) {
 446                 debug("UART init failed\n");
 447                 return err;
 448         }
 449 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 450         board_i2c_init(gd->fdt_blob);
 451 #endif
 452         return err;
 453 }
 454 #endif
 455
 456 #ifdef CONFIG_LCD
 457 void cfg_lcd_gpio(void)
 458 {
 459         struct exynos5_gpio_part1 *gpio1 =
 460                 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 461
 462         /* For Backlight */
 463         s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
 464         s5p_gpio_set_value(&gpio1->b2, 0, 1);
 465
 466         /* LCD power on */
 467         s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
 468         s5p_gpio_set_value(&gpio1->x1, 5, 1);
 469
 470         /* Set Hotplug detect for DP */
 471         s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
 472 }
 473
 474 vidinfo_t panel_info = {
 475         .vl_freq        = 60,
 476         .vl_col         = 2560,
 477         .vl_row         = 1600,
 478         .vl_width       = 2560,
 479         .vl_height      = 1600,
 480         .vl_clkp        = CONFIG_SYS_LOW,
 481         .vl_hsp         = CONFIG_SYS_LOW,
 482         .vl_vsp         = CONFIG_SYS_LOW,
 483         .vl_dp          = CONFIG_SYS_LOW,
 484         .vl_bpix        = 4,    /* LCD_BPP = 2^4, for output conosle on LCD */
 485
 486         /* wDP panel timing infomation */
 487         .vl_hspw        = 32,
 488         .vl_hbpd        = 80,
 489         .vl_hfpd        = 48,
 490
 491         .vl_vspw        = 6,
 492         .vl_vbpd        = 37,
 493         .vl_vfpd        = 3,
 494         .vl_cmd_allow_len = 0xf,
 495
 496         .win_id         = 3,
 497         .cfg_gpio       = cfg_lcd_gpio,
 498         .backlight_on   = NULL,
 499         .lcd_power_on   = NULL,
 500         .reset_lcd      = NULL,
 501         .dual_lcd_enabled = 0,
 502
 503         .init_delay     = 0,
 504         .power_on_delay = 0,
 505         .reset_delay    = 0,
 506         .interface_mode = FIMD_RGB_INTERFACE,
 507         .dp_enabled     = 1,
 508 };
 509
 510 static struct edp_device_info edp_info = {
 511         .disp_info = {
 512                 .h_res = 2560,
 513                 .h_sync_width = 32,
 514                 .h_back_porch = 80,
 515                 .h_front_porch = 48,
 516                 .v_res = 1600,
 517                 .v_sync_width  = 6,
 518                 .v_back_porch = 37,
 519                 .v_front_porch = 3,
 520                 .v_sync_rate = 60,
 521         },
 522         .lt_info = {
 523                 .lt_status = DP_LT_NONE,
 524         },
 525         .video_info = {
 526                 .master_mode = 0,
 527                 .bist_mode = DP_DISABLE,
 528                 .bist_pattern = NO_PATTERN,
 529                 .h_sync_polarity = 0,
 530                 .v_sync_polarity = 0,
 531                 .interlaced = 0,
 532                 .color_space = COLOR_RGB,
 533                 .dynamic_range = VESA,
 534                 .ycbcr_coeff = COLOR_YCBCR601,
 535                 .color_depth = COLOR_8,
 536         },
 537 };
 538
 539 static struct exynos_dp_platform_data dp_platform_data = {
 540         .phy_enable     = set_dp_phy_ctrl,
 541         .edp_dev_info   = &edp_info,
 542 };
 543
 544 void init_panel_info(vidinfo_t *vid)
 545 {
 546         vid->rgb_mode   = MODE_RGB_P,
 547
 548         exynos_set_dp_platform_data(&dp_platform_data);
 549 }
 550 #endif